Memory device and memory system

Abstract

The memory device includes a first memory block pair. The first memory block pair stores first stored data bits and compares the first stored data bits with a first input bit to generate a first current signal. The first memory block pair includes a first memory block and a second memory block. The first memory block generates a plurality of first string current signals based on a first string select line signal. The second memory block generates a plurality of second string current signals based on a second string select line signal, wherein the first string select line signal and the second string select line signal carry the first input bit, and the first memory block pair further adds the first string current signal and the second string current signal to generate the first current signal.

Description

Technical Field

[0001] This disclosure relates to a memory technology, and more particularly to a memory device and memory system. Prior Technology

[0002] Euclidean distance is the shortest distance between two points in Euclidean space and can be used as a general ruler and compass to measure the similarity between two data points. Euclidean distance is also applied in various fields, such as geometry, data mining, deep learning, and others. However, memory devices used to calculate Euclidean distance can be unstable and complex to operate. Therefore, designing a stable and easy-to-operate memory device for calculating Euclidean distance is an important issue in this field. Summary of the Invention

[0003] This disclosure includes a memory device. The memory device includes a first memory block pair. The first memory block pair is used to store first stored data bits and to compare the first stored data bits with a first input bit to generate a first current signal. The first memory block pair includes a first memory block and a second memory block. The first memory block is used to generate a plurality of first string current signals based on a first string select line signal. The second memory block is used to generate a plurality of second string current signals based on a second string select line signal, wherein the first string select line signal and the second string select line signal are used to carry the first input bit, and the first memory block pair is further used to add the first string current signal and the second string current signal to generate the first current signal.

[0004] In some embodiments, the first memory block is further used to add the first string current signal to generate a second current signal, and the second memory block is further used to add the second string current signal to generate a third current signal. When the first stored data bit has a first logic value and the first input bit has a first logic value or a second logic value, each of the second current signal and the third current signal has a first current level.

[0005] In some embodiments, when the first stored data bit has a second logic value and the first input bit has a first logic value or a second logic value, the second current signal and the third current signal have a second current level and a first current level, respectively, and the second current level is greater than the first current level.

[0006] In some embodiments, when the first stored data bit has a third logic value and the first input bit has a first logic value or a second logic value, the second current signal and the third current signal have a third current level and a first current level, respectively, and the third current level is greater than the second current level.

[0007] In some embodiments, when the first stored data bit has a fourth logic value and the first input bit has a first logic value or a second logic value, the second current signal and the third current signal have a fourth current level and a first current level, respectively, and the fourth current level is greater than the third current level.

[0008] In some embodiments, when the first stored data bit has a second logic value and the first input bit has a third logic value or a fourth logic value, the second current signal and the third current signal have a first current level and a third current level, respectively.

[0009] In some embodiments, when the first input bit has a first logic value or a second logic value, the first string select line signal and the second string select line signal have a first voltage level and a second voltage level, respectively; and when the first input bit has a third logic value or a fourth logic value, the first string select line signal and the second string select line signal have a second voltage level and a first voltage level, respectively.

[0010] In some embodiments, the first memory block includes a first memory string and a second memory string. When the first stored data bit has a first logic value, each of the first memory string and the second memory string has a first resistance value, and when the first stored data bit has a second logic value, the first memory string and the second memory string have a second resistance value and a first resistance value, respectively.

[0011] In some embodiments, when the first stored data bit has a third logic value, each of the first memory string and the second memory string has a second resistance value.

[0012] In some embodiments, the first memory block further includes a third memory string, which has a first resistance value when the first stored data bit has a third logic value, and each of the first memory string, the second memory string, and the third memory string has a second resistance value when the first stored data bit has a fourth logic value.

[0013] This disclosure includes a memory device. The memory device comprises a first memory block and a second memory block. The first memory block generates a plurality of first string current signals based on a first string select line signal, and sums the first string current signals to generate a first current signal. The second memory block generates a plurality of second string current signals based on a second string select line signal, and sums the second string current signals to generate a second current signal. The first string select line signal and the second string select line signal carry first input bits, and the first memory block and the second memory block further store first stored data bits. When the logic value of the first input bit is equal to the logic value of the first stored data bit, the current level of the first current signal is equal to the current level of the second current signal.

[0014] In some embodiments, when the logic value of the first input bit is different from the logic value of the first stored data bit, the current level of the first current signal is different from the current level of the second current signal.

[0015] In some embodiments, the first memory block and the second memory block respectively include a first switching element and a second switching element. When the first stored data bit has a first logic value, the first switching element and the second switching element respectively have a first critical voltage level and a second critical voltage level. When the first stored data bit has a second logic value, each of the first switching element and the second switching element has a second critical voltage level.

[0016] In some embodiments, when the first stored data bit has a third logic value, the first switching element and the second switching element have a second critical voltage level and a first critical voltage level, respectively.

[0017] In some embodiments, the first memory block and the second memory block further include a third switching element and a fourth switching element, respectively. When the first stored data bit has a first logic value, the third switching element and the fourth switching element have a first critical voltage level and a second critical voltage level, respectively. When the first stored data bit has a second logic value, the third switching element and the fourth switching element have a first critical voltage level and a second critical voltage level, respectively.

[0018] In some embodiments, when the first stored data bit has a third logic value, each of the first and third switching elements has a second critical voltage level, and each of the second and fourth switching elements has a first critical voltage level.

[0019] In some embodiments, the first memory block and the second memory block further include a third switching element and a fourth switching element, respectively. The third switching element and the fourth switching element are respectively used to receive a first string select line signal and a second string select line signal. When the first input bit has a first logic value or a second logic value, the first string select line signal and the second string select line signal have a first voltage level and a second voltage level, respectively. When the first input bit has a third logic value or a fourth logic value, the first string select line signal and the second string select line signal have a second voltage level and a first voltage level, respectively. The first logic value, the second logic value, the third logic value, and the fourth logic value are different from each other.

[0020] This disclosure includes a memory system. The memory system comprises a plurality of first memory blocks and a plurality of second memory blocks. The first memory blocks are used to store a plurality of first stored data bits and to compare the plurality of first stored data bits with a plurality of input bits to generate a first bit line signal. The second memory blocks are used to store a plurality of second stored data bits and to compare the second stored data bits with input bits to generate a second bit line signal. The first and second memory blocks are further used to receive a plurality of string select line signals, and the string select line signals are used to carry input bits.

[0021] In some embodiments, the first memory block includes a third memory block and a fourth memory block for receiving a first string select line signal and a second string select line signal, respectively. The third memory block and the fourth memory block are used to store the third stored data bit in the first stored data bit. In response to the first input bit in the input bit having a first logic value or a second logic value, the first string select line signal and the second string select line signal have a first voltage level and a second voltage level, respectively, and the first voltage level is greater than the second voltage level.

[0022] In some embodiments, the second memory block includes a fifth memory block and a sixth memory block for receiving a first string select line signal and a second string select line signal, respectively. The fifth memory block and the sixth memory block are used to store a fourth storage data bit in the second storage data bits. In response to a third storage data bit having a third logic value, the third memory block and the fourth memory block are used to generate a first current signal having a first current level. In response to a fourth storage data bit having a first logic value, the fifth memory block and the sixth memory block are used to generate a second current signal having a second current level, and the first current level is greater than the second current level. Simple Explanation of the Diagram

[0023] Figure 1A is a schematic diagram of a portion of a memory device according to some embodiments of the present invention. Figures 1B through 1H are schematic diagrams illustrating other scenarios of memory devices according to some embodiments of the present invention. Figure 2A is a schematic diagram of a memory device according to some embodiments of this case. Figures 2B to 2C are schematic diagrams illustrating the memory blocks shown in Figure 2A according to some embodiments of this case. Figures 2D to 2F are schematic diagrams illustrating other scenarios of the memory device shown in Figure 2A according to some embodiments of this case. Figure 3 is a schematic diagram illustrating the memory device shown in Figure 2A performing a four-level approximate Euclidean operation on the input bits, according to some embodiments of this case. Figure 4A is a schematic diagram illustrating a memory device performing a search operation according to some embodiments of this case. Figures 4B to 4H are schematic diagrams illustrating other scenarios of a memory device performing a search operation according to some embodiments of this case. Figures 5A to 5C are tables illustrating the search operation of a memory device according to some embodiments of this case. Figure 6A is a schematic diagram of a memory system according to some embodiments of the present invention. Figure 6B is a schematic diagram illustrating further details of a memory device according to some embodiments of the present invention. Figures 6C to 6F are schematic diagrams illustrating further details of memory blocks according to some embodiments of this case. Implementation

[0024] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the scope of this document.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this case pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context and this case, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0027] The following diagrams will disclose several embodiments of this invention. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this invention. That is, these practical details are not necessary in the embodiments disclosed herein. Furthermore, for the sake of simplicity, some conventional structures and components will be shown in the diagrams in a simple schematic manner.

[0028] Figure 1A is a schematic diagram of a portion of a memory device 100 according to some embodiments of the present invention. In some embodiments, the memory device 100 may include a plurality of memory strings, such as memory string MS1. Memory string MS1 is used to generate a string current signal IS1.

[0029] As shown in Figure 1A, the memory string MS1 may contain multiple switching elements, such as switching elements TS and T0~T95. However, the embodiments disclosed herein are not limited thereto. In various embodiments, the memory string MS1 may contain various numbers of switching elements; that is, 95 may be replaced with other positive integers.

[0030] In some embodiments, switching elements T0~T95 and TS are connected in series and arranged sequentially. The control terminals of switching elements T0~T95 and TS are used to receive character line signals WL0~WL95 and character string select line signal SSL, respectively.

[0031] In some embodiments, switching elements T0-T95 can store corresponding data bits and have corresponding threshold voltage levels HVT or LVT. The threshold voltage level HVT is greater than the threshold voltage level LVT. For example, the threshold voltage level HVT is between 3 volts and 4 volts, and the threshold voltage level LVT is between 0 volts and 1 volt. Details of the switching elements and data bits are further described below in the embodiments relating to Figures 2A to 2D.

[0032] In some embodiments, the string select line signal SSL may carry corresponding input bits and have corresponding voltage levels HVSSL or LVSSL. When the string select line signal SSL has a voltage level HVSSL, the switching element TS is turned on. When the string select line signal SSL has a voltage level LVSSL, the switching element TS is turned off. In some embodiments, the voltage level HVSSL is greater than the voltage level LVSSL. For example, the voltage level HVSSL is approximately equal to 3 volts, and the voltage level LVSSL is approximately equal to 0 volts. Details of the string select line signal SSL and the input bits are further described below in the embodiments relating to Figure 3.

[0033] In various embodiments, one of the character line signals WL0 to WL95 has a read voltage level VREAD to read the corresponding stored data bit. For example, in the embodiment shown in Figure 1A, the character line signal WL95 has a read voltage level VREAD to read the stored data bit corresponding to the switching element T95. In some embodiments, the read voltage level VREAD is greater than the critical voltage level LVT and less than the critical voltage level HVT. For example, the read voltage level VREAD may be 2 volts.

[0034] Correspondingly, when the switching element has a critical voltage level LVT and the control terminal of the switching element has a read voltage level VREAD, the switching element is turned on. When the switching element has a critical voltage level HVT and the control terminal of the switching element has a read voltage level VREAD, the switching element is turned off.

[0035] On the other hand, in the embodiment shown in Figure 1A, each of the character line signals WL0 to WL94 has a through voltage level VPASS, causing each of the switching elements T0 to T94 to be turned on. The character string select line signal SSL has a voltage level HVSSL, causing the switching element TS to be turned on. At this time, the resistance value of the character string resistor RSTR1 of the memory character string MS1 depends on the critical voltage level of the switching element T95. In some embodiments, the through voltage level VPASS is greater than the critical voltage level HVT. For example, the through voltage level VPASS may be between 6 volts and 7 volts.

[0036] In the embodiment shown in Figure 1A, the switching element T95 has a critical voltage level LVT, such that the word string resistor RSTR1 has a resistance value r. Correspondingly, the word string current signal IS1 has a current level ISL1.

[0037] Figure 1B is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. In the embodiment shown in Figure 1B, each of the character line signals WL0 to WL94 has a voltage level VPASS that turns on each of the switching elements T0 to T94. The character string select line signal SSL has a voltage level HVSSL that turns on the switching element TS.

[0038] At this point, in response to the critical voltage level HVT of switching element T95 and the read voltage level VREAD of word line signal WL95, switching element T95 is turned off, causing the word string resistor RSTR1 to have a resistance value R. The resistance value R corresponds to the memory word string with the switching element turned off. Correspondingly, the word string current signal IS1 has a current level ISL2. Referring to Figures 1A and 1B, the resistance value R is greater than the resistance value r. Correspondingly, the current level ISL2 is less than the current level ISL1 and can be considered as a zero current level.

[0039] Figure 1C is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 1C, each of the character line signals WL0 to WL94 has a pass voltage level VPASS, causing each of the switching elements T0 to T94 to be turned on. In response to the switching element T95 having a critical voltage level LVT and the character line signal WL95 having a read voltage level VREAD, the switching element T95 is turned on. At this time, the character string select line signal SSL has a voltage level LVSSL, causing the switching element TS to be turned off. Correspondingly, the character string resistor RSTR1 has a resistance value R. The character string current signal IS1 has a current level ISL2.

[0040] Figure 1D is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 1D, each of the character line signals WL0 to WL94 has a pass voltage level VPASS, causing each of the switching elements T0 to T94 to be turned on. In response to the switching element T95 having a critical voltage level HVT and the character line signal WL95 having a read voltage level VREAD, the switching element T95 is turned off. At this time, the character string select line signal SSL has a voltage level HVSSL, causing the switching element TS to be turned on. Correspondingly, the character string resistor RSTR1 has a resistance value R. The character string current signal IS1 has a current level ISL2.

[0041] Figure 1E is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 1E, the memory device 100 is used to read stored data bits of the corresponding switching element T93. Correspondingly, the word line signal WL93 has a read voltage level VREAD. Each of the word line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. In response to the switching element T93 having a critical voltage level LVT and the word line signal WL93 having a read voltage level VREAD, the switching element T93 is turned on. At this time, the string select line signal SSL has a voltage level HVSSL, causing the switching element TS to be turned on. Correspondingly, the string resistor RSTR1 has a resistance value r. The string current signal IS1 has a current level ISL1.

[0042] Figure 1F is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 1F, each of the character line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. In response to the switching element T93 having a critical voltage level HVT and the character line signal WL93 having a read voltage level VREAD, the switching element T93 is turned off. At this time, the character string select line signal SSL has a voltage level HVSSL, causing the switching element TS to be turned on. Correspondingly, the character string resistor RSTR1 has a resistance value R. The character string current signal IS1 has a current level ISL2.

[0043] Figure 1G is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 1G, each of the word line signals WL0~WL92 and WL94~WL95 has a voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. In response to the switching element T93 having a critical voltage level LVT and the word line signal WL93 having a read voltage level VREAD, the switching element T93 is turned on. At this time, the string select line signal SSL has a voltage level LVSSL, causing the switching element TS to be turned off. Correspondingly, the string resistor RSTR1 has a resistance value R. The string current signal IS1 has a current level ISL2.

[0044] Figure 1H is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 1H, each of the word line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. In response to the switching element T93 having a critical voltage level HVT and the word line signal WL93 having a read voltage level VREAD, the switching element T93 is turned off. At this time, the string select line signal SSL has a voltage level LVSSL, causing the switching element TS to be turned off. Correspondingly, the string resistor RSTR1 has a resistance value R. The string current signal IS1 has a current level ISL2.

[0045] Figure 2A is a schematic diagram of a memory device 200 according to some embodiments of the present invention. As shown in Figure 2A, the memory device 200 includes a memory block pair BKP1. In some embodiments, the memory block pair BKP1 is used to store storage data bits SDT1.

[0046] Memory block pair BKP1 includes memory blocks BK1 and BK1'. Memory block BK1 includes sub-blocks SBK1_1 to SBK1_9, and memory block BK1' includes sub-blocks SBK1_1' to SBK1_9'. Sub-blocks SBK1_1 to SBK1_9 and sub-blocks SBK1_1' to SBK1_9' respectively contain memory strings MS1_1 to MS1_9 and MS1_1' to MS1_9'. However, the embodiments disclosed herein are not limited thereto. In various embodiments, a sub-block may contain a variety of numbers of memory strings.

[0047] Please refer to Figures 1A to 2A. The configuration of each of the memory strings MS1_1~MS1_9 and MS1_1'~MS1_9' is similar to that of the memory string MS1. Therefore, for the sake of brevity, some descriptions will not be repeated. Details of the memory strings MS1_1~MS1_9 and MS1_1'~MS1_9' are further explained in the embodiments described below with respect to Figures 2B and 2C.

[0048] Figure 2B is a schematic diagram of the memory block BK1 shown in Figure 2A, illustrated according to some embodiments of this invention. As shown in Figure 2B, the memory string MS1_1 includes switching elements T1_1_0~T1_1_95 and TS1_1 that are connected in series and arranged sequentially. The memory string MS1_2 includes switching elements T1_2_0~T1_2_95 and TS1_2 that are connected in series and arranged sequentially, and so on. The memory string MS1_8 includes switching elements T1_8_0~T1_8_95 and TS1_8 that are connected in series and arranged sequentially. The memory string MS1_9 includes switching elements T1_9_0~T1_9_95 and TS1_9 that are connected in series and arranged sequentially.

[0049] In some embodiments, each of the control terminals of switching elements TS1_1 to TS1_9 is used to receive the string selection line signal SSL. Each of the control terminals of switching elements T1_1_0 to T1_9_0 is used to receive the character line signal WL0. Each of the control terminals of switching elements T1_1_1 to T1_9_1 is used to receive the character line signal WL1, and so on. Each of the control terminals of switching elements T1_1_93 to T1_9_93 is used to receive the character line signal WL93. Each of the control terminals of switching elements T1_1_94 to T1_9_94 is used to receive the character line signal WL94. Each of the control terminals of switching elements T1_1_95 to T1_9_95 is used to receive the character line signal WL95.

[0050] Figure 2C is a schematic diagram of the memory block BK1' shown in Figure 2A, illustrated according to some embodiments of this invention. As shown in Figure 2C, the memory string MS1_1' includes switching elements T1_1_0'~T1_1_95' and TS1_1' that are connected in series and arranged in sequence. The memory string MS1_2' includes switching elements T1_2_0'~T1_2_95' and TS1_2' that are connected in series and arranged in sequence, and so on. The memory string MS1_8' includes switching elements T1_8_0'~T1_8_95' and TS1_8' that are connected in series and arranged in sequence. The memory string MS1_9' includes switching elements T1_9_0'~T1_9_95' and TS1_9' that are connected in series and arranged in sequence.

[0051] In some embodiments, each of the control terminals of switching elements TS1_1' to TS1_9' is used to receive the character string select line signal SSL'. Each of the control terminals of switching elements T1_1_0' to T1_9_0' is used to receive the character line signal WL0. Each of the control terminals of switching elements T1_1_1' to T1_9_1' is used to receive the character line signal WL1, and so on. Each of the control terminals of switching elements T1_1_93' to T1_9_93' is used to receive the character line signal WL93. Each of the control terminals of switching elements T1_1_94' to T1_9_94' is used to receive the character line signal WL94. Each of the control terminals of switching elements T1_1_95' to T1_9_95' is used to receive the character line signal WL95.

[0052] In the embodiments shown in Figures 2C and 2B, the memory device 200 performs a search operation on the memory cells of the 95th layer. In other words, the memory device 200 performs a search operation on the stored data bits SDT1 stored in the switching elements T1_1_95 to T1_9_95 and T1_1_95' to T1_9_95'. Correspondingly, the word line signal WL95 has a read voltage level VREAD, and each of the word line signals WL0 to WL94 has a pass voltage level VPASS.

[0053] In other embodiments, the memory device 200 may also perform search operations on memory cells in other layers to read stored data bits stored in those layers. For example, referring to Figures 1E to 1H and Figures 2B to 2C, the memory device 200 may also perform search operations on memory cells in layer 93. In this case, the character line signal WL93 has a read voltage level VREAD, and each of the character line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS.

[0054] In the embodiments shown in Figures 2C and 2B, the stored data bit SDT1 has a logic value of 0. Correspondingly, each of the switching elements T1_1_95 to T1_9_95 has a critical voltage level HVT, and each of the switching elements T1_1_95' to T1_9_95' has a critical voltage level LVT.

[0055] In response to the character line signal WL93 having a read voltage level VREAD, each of the switching elements T1_1_95 to T1_9_95 is turned off, and each of the switching elements T1_1_95' to T1_9_95' is turned on. Correspondingly, each of the memory strings MS1_1 to MS1_9 has a resistance value R, and each of the memory strings MS1_1' to MS1_9' has a resistance value r. In other words, memory block BK1 has nine memory strings MS1_1 to MS1_9 with resistance values ​​R, and memory block BK1' has nine memory strings MS1_1' to MS1_9' with resistance values ​​r.

[0056] Figure 2D is a schematic diagram illustrating another scenario of the memory device 200 shown in Figure 2A according to some embodiments of this case. Please refer to Figures 2B to 2D; the embodiment shown in Figure 2D is a variation of the embodiments shown in Figures 2C and 2B. Therefore, for the sake of brevity, some descriptions will not be repeated, and some reference numerals are not shown in Figure 2D. For example, the reference numerals for memory strings MS1_1~MS1_9 and MS1_1'~MS1_9' are not shown in Figure 2D.

[0057] In the embodiment shown in Figure 2D, the stored data bit SDT1 has a logic value of 1. Correspondingly, each of the switching elements T1_2_95~T1_9_95 and T1_5_95'~T1_9_95' has a critical voltage level HVT and is turned off, and each of the switching elements T1_1_95 and T1_2_95'~T1_4_95' has a critical voltage level LVT and is turned on.

[0058] At this point, each of the memory strings MS1_2~MS1_9 and MS1_5'~MS1_9' has a resistance value R, and each of the memory strings MS1_1 and MS1_1'~MS1_4' has a resistance value r. In other words, memory block BK1 has 8 memory strings MS1_2~MS1_9 with resistance value R and 1 memory string MS1_1 with resistance value r, and memory block BK1' has 5 memory strings MS1_5'~MS1_9' with resistance value R and 4 memory strings MS1_1'~MS1_4' with resistance value r.

[0059] Figure 2E is a schematic diagram illustrating another scenario of the memory device 200 shown in Figure 2A according to some embodiments of this case. Please refer to Figures 2B to 2E; the embodiment shown in Figure 2E is a variation of the embodiments shown in Figures 2C and 2B. Therefore, for the sake of brevity, some descriptions will not be repeated, and some reference numerals are not shown in Figure 2E. For example, the reference numerals for memory strings MS1_1~MS1_9 and MS1_1'~MS1_9' are not shown in Figure 2E.

[0060] In the embodiment shown in Figure 2E, the stored data bit SDT1 has a logic value of 2. Correspondingly, each of the switching elements T1_5_95~T1_9_95 and T1_2_95'~T1_9_95' has a critical voltage level HVT and is turned off, and each of the switching elements T1_1_95~T1_4_95 and T1_1_95' has a critical voltage level LVT and is turned on.

[0061] At this point, each of the memory strings MS1_5~MS1_9 and MS1_2'~MS1_9' has a resistance value R, and each of the memory strings MS1_1' and MS1_1~MS1_4 has a resistance value r. In other words, memory block BK1 has 5 memory strings MS1_5~MS1_9 with resistance value R and 4 memory strings MS1_1~MS1_4 with resistance value r, and memory block BK1' has 8 memory strings MS1_2'~MS1_9' with resistance value R and 1 memory string MS1_1' with resistance value r.

[0062] Figure 2F is a schematic diagram illustrating another scenario of the memory device 200 shown in Figure 2A according to some embodiments of this case. Please refer to Figures 2B to 2F; the embodiment shown in Figure 2F is a variation of the embodiments shown in Figures 2C and 2B. Therefore, for the sake of brevity, some descriptions will not be repeated, and some reference numerals are not shown in Figure 2F. For example, the reference numerals for memory strings MS1_1~MS1_9 and MS1_1'~MS1_9' are not shown in Figure 2F.

[0063] In the embodiment shown in Figure 2F, the stored data bit SDT1 has a logic value of 3. Correspondingly, each of the switching elements T1_1_95' to T1_9_95' has a critical voltage level HVT and is turned off, and each of the switching elements T1_1_95 to T1_9_95 has a critical voltage level LVT and is turned on.

[0064] At this point, each of the memory strings MS1_1' to MS1_9' has a resistance value R, and each of the memory strings MS1_1 to MS1_9 has a resistance value r. In other words, memory block BK1 has 9 memory strings MS1_1 to MS1_9 with resistance value r, and memory block BK1' has 9 memory strings MS1_1' to MS1_9' with resistance value R.

[0065] In summary, by using pairs of nine sub-blocks SBK1_1~SBK1_9 and nine sub-blocks SBK1_1'~SBK1_9', the memory device 200 can perform four levels of Euclidean operations (i.e., logic values ​​0, 1, 2, and 3). However, the embodiments disclosed herein are not limited to this. In various embodiments, the memory device 200 can perform various numbers of levels of Euclidean operations. For example, in some embodiments, the memory device 200 may also include 16 pairs of sub-blocks to perform five levels of Euclidean operations (i.e., logic values ​​0, 1, 2, 3, and 4).

[0066] Figure 3 is a schematic diagram 300 illustrating the memory device 200 shown in Figure 2A performing a four-level approximate Euclidean operation on the input bit IBT1, according to some embodiments of this case.

[0067] As shown in Figure 300, when input bit IBT1 has a logic value of 0 or 1, input bit IBT1 has an encoded value of 0. When input bit IBT1 has a logic value of 2 or 3, input bit IBT1 has an encoded value of 3. In addition, input bit IBT1 can also have a wildcard encoded value.

[0068] Please refer to Figures 2A and 3. The string select line signals SSL and SSL' can carry the input bit IBT1. When the input bit IBT1 has the encoded value 0, the string select line signals SSL and SSL' have voltage levels HVSSL and LVSSL respectively, which turns on each of the switching elements TS1_1 to TS1_9 in memory block BK1 and turns off each of the switching elements TS1_1' to TS1_9' in memory block BK1'.

[0069] When input bit IBT1 has the encoded value 3, the string selection line signals SSL and SSL' have voltage levels LVSSL and HVSSL respectively, causing each of the switching elements TS1_1 to TS1_9 to be turned off, and each of the switching elements TS1_1' to TS1_9' to be turned on.

[0070] When input bit IBT1 has a wildcard code value, each of the string select line signals SSL and SSL' has a voltage level LVSSL, causing each of the switching elements TS1_1~TS1_9 and TS1_1'~TS1_9' to be turned off. In some embodiments, the wildcard code value of input bit IBT1 is used for high-level matching. In this case, the current signals generated by memory blocks BK1 and BK1' have a zero voltage level.

[0071] Figure 4A is a schematic diagram illustrating a search operation of a memory device 200 according to some embodiments of this invention. Please refer to Figures 2A to 4A; the embodiment shown in Figure 4A is a variation of the embodiments shown in Figures 2A to 2F. Therefore, for the sake of brevity, some descriptions will not be repeated, and some reference numerals are not shown in Figure 4A. For example, the reference numerals for memory strings and some switching elements are not shown in Figure 4A.

[0072] During the search operation, the memory device 200 compares the input bit IBT1 and the stored data bit SDT1, so that the memory strings MS1_1 to MS1_9 generate string current signals IS1_1 to IS1_9 respectively, and the memory strings MS1_1' to MS1_9' generate string current signals IS1_1' to IS1_9' respectively.

[0073] In some embodiments, memory block BK1 is used to sum the string current signals IS1_1 to IS1_9 to generate current signal IB1. Memory block BK1' is used to sum the string current signals IS1_1' to IS1_9' to generate current signal IB1'. In some embodiments, memory device 200 is used to sum current signals IB1 and IB1' to generate current signal IT1.

[0074] In other words, the current level of current signal IB1 is equal to the sum of the current levels of the string current signals IS1_1 to IS1_9, and the current level of current signal IB1' is equal to the sum of the current levels of the string current signals IS1_1' to IS1_9'. The current level of current signal IT1 is equal to the sum of the current levels of current signals IB1 and IB1'.

[0075] In the embodiment shown in Figure 4A, the input bit IBT1 has a logic value of 0 or 1, and therefore has an encoded value of 0. Correspondingly, the string select line signals SSL and SSL' have voltage levels HVSSL and LVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned on and each of the switching elements TS1_1' to TS1_9' is turned off.

[0076] On the other hand, the data storage bit SDT1 has a logic value of 0. Correspondingly, each of the switching elements T1_1_95 to T1_9_95 has a critical voltage level HVT, and each of the switching elements T1_1_95' to T1_9_95' has a critical voltage level LVT.

[0077] In response to the turn-off of each of the switching elements TS1_1' to TS1_9', each of the string current signals IS1_1' to IS1_9' has a current level ISL2. In response to the turn-off of each of the switching elements T1_1_95 to T1_9_95, which has a critical voltage level HVT, each of the string current signals IS1_1 to IS1_9 has a current level ISL2.

[0078] In other words, the current levels of current signals IB1 and IB1' are each equal to 0 times the current level ISL1. Correspondingly, the current level of current signal IT1 is also equal to 0 times the current level ISL1.

[0079] Figure 4B is a schematic diagram illustrating another scenario of a search operation performed by the memory device 200 according to some embodiments of this case. Please refer to Figures 4B and 4A. The embodiment shown in Figure 4B is a variation of the embodiment shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0080] In the embodiment shown in Figure 4B, the input bit IBT1 has a logic value of 0 or 1, and therefore has an encoded value of 0. Correspondingly, the string select line signals SSL and SSL' have voltage levels HVSSL and LVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned on and each of the switching elements TS1_1' to TS1_9' is turned off.

[0081] On the other hand, the data storage bit SDT1 has a logic value of 1. Correspondingly, each of the switching elements T1_2_95~T1_9_95 and T1_5_95'~T1_9_95' has a critical voltage level HVT, and each of the switching elements T1_1_95 and T1_2_95'~T1_4_95' has a critical voltage level LVT.

[0082] In response to the off state of switching elements TS1_1'~TS1_9', each of the string current signals IS1_1'~IS1_9' has a current level ISL2. In response to the off state of switching elements T1_2_95~T1_9_95, each of the string current signals IS1_2~IS1_9 has a current level ISL2. In response to the off state of switching element T1_1_95, which has a critical voltage level LVT, and switching element TS1_1 being turned on, the string current signal IS1_1 has a current level ISL1.

[0083] In other words, the current level of current signal IB1 is equal to 1 times the current level ISL1, and the current level of current signal IB1' is equal to 0 times the current level ISL1. Correspondingly, the current level of current signal IT1 is equal to 1 times the current level ISL1.

[0084] Figure 4C is a schematic diagram illustrating another scenario of a search operation performed by the memory device 200 according to some embodiments of this case. Please refer to Figures 4C and 4A. The embodiment shown in Figure 4C is a variation of the embodiment shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0085] In the embodiment shown in Figure 4C, the input bit IBT1 has a logic value of 0 or 1, and therefore has an encoded value of 0. Correspondingly, the string select line signals SSL and SSL' have voltage levels HVSSL and LVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned on and each of the switching elements TS1_1' to TS1_9' is turned off.

[0086] On the other hand, the data storage bit SDT1 has a logic value of 2. Correspondingly, each of the switching elements T1_5_95~T1_9_95 and T1_2_95'~T1_9_95' has a critical voltage level HVT, and each of the switching elements T1_1_95~T1_4_95 and T1_1_95' has a critical voltage level LVT.

[0087] In response to the off state of switching elements TS1_1'~TS1_9', each of the string current signals IS1_1'~IS1_9' has a current level ISL2. In response to the off state of switching elements T1_5_95~T1_9_95, each of the string current signals IS1_5~IS1_9 has a current level ISL2. In response to the off state of switching elements T1_1_95~T1_4_95, each of the string current signals IS1_1~IS1_4 has a current level ISL1.

[0088] In other words, the current level of current signal IB1 is equal to 4 times the current level ISL1, and the current level of current signal IB1' is equal to 0 times the current level ISL1. Correspondingly, the current level of current signal IT1 is equal to 4 times the current level ISL1.

[0089] Figure 4D is a schematic diagram illustrating another scenario of a search operation performed by the memory device 200 according to some embodiments of this case. Please refer to Figures 4D and 4A. The embodiment shown in Figure 4D is a variation of the embodiment shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0090] In the embodiment shown in Figure 4D, input bit IBT1 has a logic value of 0 or 1, and therefore has an encoded value of 0. Correspondingly, the string select line signals SSL and SSL' have voltage levels HVSSL and LVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned on and each of the switching elements TS1_1' to TS1_9' is turned off.

[0091] On the other hand, the data storage bit SDT1 has a logic value of 3. Correspondingly, each of the switching elements T1_1_95' ~ T1_9_95' has a critical voltage level HVT, and each of the switching elements T1_1_95 ~ T1_9_95 has a critical voltage level LVT.

[0092] In response to the switching elements TS1_1'~TS1_9' being turned off, each of the string current signals IS1_1'~IS1_9' has a current level ISL2. In response to each of the switching elements T1_1_95~T1_9_95 having a critical voltage level LVT and each of the switching elements TS1_1~TS1_9 being turned on, each of the string current signals IS1_1~IS1_9 has a current level ISL1.

[0093] In other words, the current level of current signal IB1 is equal to 9 times the current level ISL1, and the current level of current signal IB1' is equal to 0 times the current level ISL1. Correspondingly, the current level of current signal IT1 is equal to 9 times the current level ISL1.

[0094] Figure 4E is a schematic diagram illustrating another scenario of a search operation performed by the memory device 200 according to some embodiments of this case. Please refer to Figures 4E and 4A. The embodiment shown in Figure 4E is a variation of the embodiment shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0095] In the embodiment shown in Figure 4E, input bit IBT1 has a logic value of 2 or 3, and therefore has an encoded value of 3. Correspondingly, the string select line signals SSL and SSL' have voltage levels LVSSL and HVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned off and each of the switching elements TS1_1' to TS1_9' is turned on.

[0096] On the other hand, the data storage bit SDT1 has a logic value of 0. Correspondingly, each of the switching elements T1_1_95 to T1_9_95 has a critical voltage level HVT, and each of the switching elements T1_1_95' to T1_9_95' has a critical voltage level LVT.

[0097] In response to the off state of switching elements TS1_1~TS1_9, each of the string current signals IS1_1~IS1_9 has a current level ISL2. In response to the on state of each of the switching elements T1_1_95'~T1_9_95' having a critical voltage level LVT and each of the switching elements TS1_1'~TS1_9' being turned on, each of the string current signals IS1_1'~IS1_9' has a current level ISL1.

[0098] In other words, the current level of current signal IB1 is equal to 0 times the current level ISL1, and the current level of current signal IB1' is equal to 9 times the current level ISL1. Correspondingly, the current level of current signal IT1 is equal to 9 times the current level ISL1.

[0099] Figure 4F is a schematic diagram illustrating another scenario of a search operation performed by the memory device 200 according to some embodiments of this case. Please refer to Figures 4F and 4A. The embodiment shown in Figure 4F is a variation of the embodiment shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0100] In the embodiment shown in Figure 4F, input bit IBT1 has a logic value of 2 or 3, and therefore has an encoded value of 3. Correspondingly, the string select line signals SSL and SSL' have voltage levels LVSSL and HVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned off and each of the switching elements TS1_1' to TS1_9' is turned on.

[0101] On the other hand, the data storage bit SDT1 has a logic value of 1. Correspondingly, each of the switching elements T1_2_95~T1_9_95 and T1_5_95'~T1_9_95' has a critical voltage level HVT, and each of the switching elements T1_1_95 and T1_1_95'~T1_4_95' has a critical voltage level LVT.

[0102] In response to the off state of switching elements TS1_1~TS1_9, each of the string current signals IS1_1~IS1_9 has a current level ISL2. In response to the critical voltage level HVT of each of the switching elements T1_5_95'~T1_9_95', each of the string current signals IS1_5'~IS1_9' has a current level ISL2. In response to the critical voltage level LVT of each of the switching elements T1_1_95'~T1_4_95' and the on state of each of the switching elements TS1_1'~TS1_4', the string current signal IS1_1 has a current level ISL1.

[0103] In other words, the current level of current signal IB1 is equal to 0 times the current level ISL1, and the current level of current signal IB1' is equal to 4 times the current level ISL1. Correspondingly, the current level of current signal IT1 is equal to 4 times the current level ISL1.

[0104] Figure 4G is a schematic diagram illustrating another scenario of a search operation performed by the memory device 200 according to some embodiments of this case. Please refer to Figures 4G and 4A. The embodiment shown in Figure 4G is a variation of the embodiment shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0105] In the embodiment shown in Figure 4G, input bit IBT1 has a logic value of 2 or 3, and therefore has an encoded value of 3. Correspondingly, the string select line signals SSL and SSL' have voltage levels LVSSL and HVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned off and each of the switching elements TS1_1' to TS1_9' is turned on.

[0106] On the other hand, the data storage bit SDT1 has a logic value of 2. Correspondingly, each of the switching elements T1_5_95~T1_9_95 and T1_2_95'~T1_9_95' has a critical voltage level HVT, and each of the switching elements T1_1_95~T1_4_95 and T1_1_95' has a critical voltage level LVT.

[0107] In response to the off state of switching elements TS1_1~TS1_9, each of the string current signals IS1_1~IS1_9 has a current level ISL2. In response to the off state of switching elements T1_2_95'~T1_9_95', each of the string current signals IS1_2'~IS1_9' has a current level ISL2. In response to the on state of switching element T1_1_95' having a critical voltage level LVT and switching element TS1_1' being turned on, the string current signal IS1_1 has a current level ISL1.

[0108] In other words, the current level of current signal IB1 is equal to 0 times the current level ISL1, and the current level of current signal IB1' is equal to 1 times the current level ISL1. Correspondingly, the current level of current signal IT1 is equal to 1 times the current level ISL1.

[0109] Figure 4H is a schematic diagram illustrating another scenario of a search operation performed by the memory device 200 according to some embodiments of this case. Please refer to Figures 4H and 4A. The embodiment shown in Figure 4H is a variation of the embodiment shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0110] In the embodiment shown in Figure 4H, input bit IBT1 has a logic value of 2 or 3, and therefore has an encoded value of 3. Correspondingly, the string select line signals SSL and SSL' have voltage levels LVSSL and HVSSL, respectively, such that each of the switching elements TS1_1 to TS1_9 is turned off and each of the switching elements TS1_1' to TS1_9' is turned on.

[0111] On the other hand, the data storage bit SDT1 has a logic value of 3. Correspondingly, each of the switching elements T1_1_95' ~ T1_9_95' has a critical voltage level HVT, and each of the switching elements T1_1_95 ~ T1_9_95 has a critical voltage level LVT.

[0112] In response to the turn-off of switching elements TS1_1~TS1_9, each of the string current signals IS1_1~IS1_9 has a current level ISL2. In response to the turn-off of switching elements T1_1_95'~T1_9_95', each of the string current signals IS1_1'~IS1_9' has a current level ISL2.

[0113] In other words, the current level of current signal IB1 is equal to 0 times the current level ISL1, and the current level of current signal IB1' is equal to 0 times the current level ISL1. Correspondingly, the current level of current signal IT1 is equal to 0 times the current level ISL1.

[0114] In summary, the current level of the current signal IT1 is proportional to the square of the difference between the encoded value of the input bit IBT1 and the logic value of the stored data bit SDT1.

[0115] For example, in the embodiment shown in Figure 4A, there is a difference of 0 between the encoded value 0 of the input bit IBT1 and the logic value 0 of the stored data bit SDT1. In the embodiment shown in Figure 4H, there is a difference of 0 between the encoded value 3 of the input bit IBT1 and the logic value 3 of the stored data bit SDT1. Correspondingly, in both of the above scenarios, the current level of the current signal IT1 is proportional to the square of 0, that is, 0 times the current level ISL1.

[0116] In the embodiment shown in Figure 4B, there is a difference of 1 between the encoded value 0 of the input bit IBT1 and the logic value 1 of the stored data bit SDT1. In the embodiment shown in Figure 4G, there is a difference of 1 between the encoded value 3 of the input bit IBT1 and the logic value 2 of the stored data bit SDT1. Correspondingly, in both of the above scenarios, the current level of the current signal IT1 is proportional to the square of 1, that is, 1 times the current level ISL1.

[0117] In the embodiment shown in Figure 4C, there is a difference of 2 between the encoded value 0 of the input bit IBT1 and the logic value 2 of the stored data bit SDT1. In the embodiment shown in Figure 4F, there is a difference of 2 between the encoded value 3 of the input bit IBT1 and the logic value 1 of the stored data bit SDT1. Correspondingly, in both of the above scenarios, the current level of the current signal IT1 is proportional to the square of 2, that is, 4 times the current level ISL1.

[0118] In the embodiment shown in Figure 4D, there is a difference of 3 between the encoded value 0 of the input bit IBT1 and the logic value 3 of the stored data bit SDT1. In the embodiment shown in Figure 4E, there is a difference of 3 between the encoded value 3 of the input bit IBT1 and the logic value 0 of the stored data bit SDT1. Correspondingly, in both of the above scenarios, the current level of the current signal IT1 is proportional to the square of 3, that is, 9 times the current level ISL1.

[0119] Figure 5A is a table 500A illustrating a search operation of a memory device 200 according to some embodiments of this invention. As shown in Table 500A, when input bit IBT1 has a logic value of 0 or 1, the switching elements TS1_1 to TS1_9 in memory block BK1 are turned on by the string select line signal SSL, and the switching elements TS1_1' to TS1_9' in memory block BK1' are turned off by the string select line signal SSL'. When input bit IBT1 has a logic value of 2 or 3, the switching elements TS1_1 to TS1_9 in memory block BK1 are turned off by the string select line signal SSL, and the switching elements TS1_1' to TS1_9' in memory block BK1' are turned on by the string select line signal SSL'.

[0120] On the other hand, when the stored data bit SDT1 has a logic value of 0, memory block BK1 has 9 switching elements with critical voltage level HVT, and memory block BK1' has 9 switching elements with critical voltage level LVT.

[0121] When the stored data bit SDT1 has a logic value of 1, memory block BK1 has 8 switching elements with critical voltage level HVT and 1 switching element with critical voltage level LVT, and memory block BK1' has 5 switching elements with critical voltage level HVT and 4 switching elements with critical voltage level LVT.

[0122] When the stored data bit SDT1 has a logic value of 2, memory block BK1 has 5 switching elements with critical voltage level HVT and 4 switching elements with critical voltage level LVT, and memory block BK1' has 8 switching elements with critical voltage level HVT and 1 switching element with critical voltage level LVT.

[0123] When the stored data bit SDT1 has a logic value of 3, memory block BK1 has 9 switching elements with critical voltage level LVT, and memory block BK1' has 9 switching elements with critical voltage level HVT.

[0124] As shown in Figure 5A, the current signal IT1 has different current levels in different scenarios. When the input bit IBT1 has a logic value of 0 or 1, and the stored data bit SDT1 has logic values ​​0-3, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 0, 1, 4, and 9, respectively. When the input bit IBT1 has a logic value of 2 or 3, and the stored data bit SDT1 has logic values ​​0-3, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 9, 4, 1, and 0, respectively.

[0125] In the embodiment shown in Figure 5A, the memory device 200 does not have a wildcard code value. In other embodiments, the memory device 200 may also have a wildcard code value, such as the embodiment shown in Figure 5B below.

[0126] Figure 5B is a table 500B illustrating a search operation of a memory device 200 according to some embodiments of this invention. Referring to Figures 5A and 5B, table 500B is a variation of table 500A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0127] Compared to Table 500A, in the embodiment of Table 500B, when input bit IBT1 has a logic value of 1 or logic value 2, input bit IBT1 has a wildcard coded value. Referring to Figures 3 and 5B, when input bit IBT1 has a wildcard coded value, each of the string selection line signals SSL and SSL' has a voltage level LVSSL, causing the corresponding switching element to turn off.

[0128] In other words, when the input bit IBT1 has a logic value of 1 or 2, the switching elements TS1_1 to TS1_9 in memory block BK1 are turned off by the string selection line signal SSL, and the switching elements TS1_1' to TS1_9' in memory block BK1' are turned off by the string selection line signal SSL'.

[0129] Correspondingly, when the input bit IBT1 has a logic value of 1 or 2, in response to the logic value of the stored data bit SDT1 from 0 to 3, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 0.

[0130] Figure 5C illustrates a table 500C showing a search operation performed by a memory device 200 according to some embodiments of this invention. Referring to Figures 5B and 5C, table 500C is a variation of table 500B. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0131] In the embodiment shown in Figure 5C, the memory cell has 5 levels. In other words, each of the input bit IBT1 and the stored data bit SDT1 can have logic values ​​from 0 to 4. Referring to Figures 4A to 5C, when the memory cell has 5 levels, each of the memory blocks BK1 and BK1' contains 16 memory strings to store logic values ​​from 0 to 4.

[0132] When the stored data bit SDT1 has a logic value of 0, memory block BK1 contains 16 switching elements with critical voltage level HVT, and memory block BK1' contains 16 switching elements with critical voltage level LVT.

[0133] When the stored data bit SDT1 has a logic value of 1, memory block BK1 contains 15 switching elements with critical voltage level HVT and 1 switching element with critical voltage level LVT, and memory block BK1' contains 7 switching elements with critical voltage level HVT and 9 switching elements with critical voltage level LVT.

[0134] When the stored data bit SDT1 has a logic value of 2, memory block BK1 contains 12 switching elements with critical voltage level HVT and 4 switching elements with critical voltage level LVT, and memory block BK1' contains 12 switching elements with critical voltage level HVT and 4 switching elements with critical voltage level LVT.

[0135] When the stored data bit SDT1 has a logic value of 3, memory block BK1 contains 7 switching elements with critical voltage level HVT and 9 switching elements with critical voltage level LVT, and memory block BK1' contains 15 switching elements with critical voltage level HVT and 1 switching element with critical voltage level LVT.

[0136] When the stored data bit SDT1 has a logic value of 4, memory block BK1 contains 16 switching elements with a critical voltage level LVT, and memory block BK1' contains 16 switching elements with a critical voltage level HVT.

[0137] On the other hand, when input bit IBT1 has a logic value of 0 or 1, the switching elements in memory block BK1 are turned on by the string select line signal SSL, and the switching elements in memory block BK1' are turned off by the string select line signal SSL'. When input bit IBT1 has a logic value of 2, the switching elements in memory blocks BK1 and BK1' are turned off by the string select line signals SSL and SSL'. When input bit IBT1 has a logic value of 3 or 4, the switching elements in memory block BK1 are turned off by the string select line signal SSL, and the switching elements in memory block BK1' are turned on by the string select line signal SSL'.

[0138] Correspondingly, when the input bit IBT1 has a logic value of 0 or 1, in response to the stored data bit SDT1 having logic values ​​of 0 to 4, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 0, 1, 4, 9 and 16, respectively.

[0139] When input bit IBT1 has a logic value of 2, in response to stored data bit SDT1 having logic values ​​from 0 to 4, the current level of current signal IT1 is equal to current level ISL1 multiplied by 0. In this case, input bit IBT1 can be considered to have a wildcard coded value.

[0140] When the input bit IBT1 has a logic value of 3 or 4, in response to the stored data bit SDT1 having logic values ​​of 0 to 4, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 16, 9, 4, 1 and 0 respectively.

[0141] In summary, in the various scenarios shown in Figures 5A to 5C, the larger the difference between the logic value of the input bit IBT1 and the logic value of the stored data bit SDT1, the higher the current level of the current signal IT1. Conversely, the smaller the difference between the logic value of the input bit IBT1 and the logic value of the stored data bit SDT1, the lower the current level of the current signal IT1. In this way, approximate Euclidean distance calculation can be achieved using the memory device 200.

[0142] For example, in the embodiment shown in Figure 5C, along line segment L51, the logic value of input bit IBT1 is equal to the logic value of stored data bit SDT1. In other words, the difference between the logic value of input bit IBT1 and the logic value of stored data bit SDT1 is equal to 0. Correspondingly, the current level of current signal IT1 is equal to the current level ISL1 multiplied by 0 or 1. Along lines L52 and L53, the difference between the logic value of input bit IBT1 and the logic value of stored data bit SDT1 is equal to 3. Correspondingly, the current level of current signal IT1 is equal to the current level ISL1 multiplied by 9 or 16.

[0143] In some implementations, memory devices use only two switching elements to store one data bit and two word line signals to carry one input bit, resulting in lower reliability and robustness, and more complex word line signal operation.

[0144] Compared to the above approach, in this embodiment of the disclosure, the memory device 200 stores the data bits DT1 in memory blocks and carries the input bits IBT1 through the string selection signals SSL and SSL', which makes the reliability and robustness higher and the operation of the string selection signals SSL and SSL' simpler.

[0145] Figure 6A is a schematic diagram of a memory system 600 according to some embodiments of the present invention. As shown in Figure 6A, the memory system 600 includes a memory device 610 and an output device 620. In some embodiments, the memory device 610 is used to perform a search operation to generate a corresponding bit line signal. The output device 620 is used to output the matching result of the search operation of the memory device 610.

[0146] As shown in Figure 6A, memory device 610 includes multiple memory planes, such as memory planes PLN0 to PLN4. Each memory plane includes multiple memory blocks, page registers, and cache registers. For example, memory plane PLN0 includes memory blocks BK0 to BK255, BK0' to BK255', page register 611, and cache register 612. However, the embodiments disclosed herein are not limited thereto. In various embodiments, memory device 610 may include various numbers of memory blocks; that is, 255 may be replaced with other positive integers.

[0147] In some embodiments, page register 611 can be implemented by a sense amplifier and used to sense the search results corresponding to the bit line signals. The cache register 612 can perform processing on the bit line signals including AND logic, OR logic, and counting logic processing, or a combination of the above three logics. Referring to Figures 1A to 6A, the cache register 612 can receive sensing results from memory devices 100, 200 and / or memory blocks BK0~BK255, BK0'~BK255', and control the sorting (which can be serial or parallel) and combining the sensing results to generate an overall search result as the pairing result output by the output device 620.

[0148] In some embodiments, cache 612 may work in conjunction with a priority encoder (not shown). The priority encoder may perform priority encoding on the search results corresponding to the bit line signals. For example, cache 612 and priority encoder may process the search results corresponding to the bit line signals in a unified manner and prioritize the address of the bit line signal corresponding to the best search result (i.e., the input value of the input data and the stored value of the stored data are closest to each other).

[0149] As shown in Figure 6A, memory blocks BK0~BK255 and BK0'~BK255' are used to receive string select line signals SSL0~SSL255 and SSL0'~SSL255', respectively. Referring to Figures 2A to 6A, the configuration of string select line signals SSL0~SSL255 and SSL0'~SSL255' is similar to that of string select line signals SSL and SSL'. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0150] Figure 6B is a schematic diagram illustrating further details of a memory device 610 according to some embodiments of the present invention. As shown in Figure 6B, the memory device 610 includes global bit lines GBL1 to GBL128K, where K equals one thousand. Global bit lines GBL1 to GBL128K are used to transmit bit line signals BL1 to BL128K to page registers 611, respectively. However, the embodiments disclosed herein are not limited thereto. In various embodiments, the memory device 610 may include various numbers of global bit lines; that is, 128K may be replaced with other positive integers.

[0151] As shown in Figure 6B, the memory device 610 further includes memory blocks BK0_1~BK255_1 and BK0_1'~BK255_1' coupled to the global bit line GBL1. Memory blocks BK0_1 and BK0_1' are used to generate the current signal IT0_1. Memory blocks BK1_1 and BK1_1' are used to generate the current signal IT1_1, and so on. Memory blocks BK255_1 and BK255_1' are used to generate the current signal IT255_1.

[0152] Please refer to Figures 2A to 6A. The configuration of memory blocks BK0_1~BK255_1, BK0_1'~BK255_1', and current signals IT0_1~IT255_1 is similar to the configuration of memory blocks BK1, BK1', and current signal IT1. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0153] In some embodiments, the memory device 610 is used to sum the current signals IT0_1 to IB255_1 on the global bit line GBL1 to generate a bit line signal BL1. In other words, the current level of the bit line signal BL1 is equal to the sum of the current levels of the current signals IT0_1 to IB255_1.

[0154] As shown in Figure 6A, the memory device 610 further includes memory blocks BK0_128K~BK255_128K and BK0_128K'~BK255_128K' coupled to the global bit line GBL128K. Memory blocks BK0_128K and BK0_128K' are used to generate the current signal IT0_128K. Memory blocks BK1_128K and BK1_128K' are used to generate the current signal IT1_128K, and so on. Memory blocks BK255_128K and BK255_128K' are used to generate the current signal IT255_128K.

[0155] Please refer to Figures 2A to 6A. The configuration of memory blocks BK0_128K ~ BK255_128K, BK0_128K' ~ BK255_128K', and current signals IT0_128K ~ IT255_128K is similar to the configuration of memory blocks BK1, BK1', and current signal IT1. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0156] In some embodiments, the memory device 610 is used to sum the current signals IT0_128K to IB255_128K on the global bit line GBL128K to generate a bit line signal BL128K. In other words, the current level of the bit line signal BL128K is equal to the sum of the current levels of the current signals IT0_128K to IB255_128K.

[0157] Furthermore, the memory device 610 includes multiple memory blocks coupled to other global bit lines. These memory blocks generate corresponding current signals and sum the current signals to generate corresponding bit line signals.

[0158] In some embodiments, memory blocks BK0_1 and BK0_1' are used to store data bits SDT0_1. Memory blocks BK1_1 and BK1_1' are used to store data bits SDT1_1, and so on. Memory blocks BK255_1 and BK255_1' are used to store data bits SDT255_1.

[0159] Similarly, memory blocks BK0_128K and BK0_128K' are used to store data bits SDT0_128K. Memory blocks BK1_128K and BK1_128K' are used to store data bits SDT1_128K, and so on. Memory blocks BK255_128K and BK255_128K' are used to store data bits SDT255_128K.

[0160] On the other hand, the string select lines SSL0 and SSL0' are used to carry the input bit IBT0. The string select lines SSL1 and SSL1' are used to carry the input bit IBT1, and so on. The string select lines SSL255 and SSL255' are used to carry the input bit IBT255.

[0161] During the search operation, memory blocks BK0_1 and BK0_1 compare the stored data bit SDT0_1 and the input bit IBT0 to generate the current signal IT0_1. Memory blocks BK1_1 and BK1_1 compare the stored data bit SDT1_1 and the input bit IBT1 to generate the current signal IT1_1, and so on. Memory blocks BK255_1 and BK255_1 compare the stored data bit SDT255_1 and the input bit IBT255 to generate the current signal IT255_1.

[0162] Similarly, memory blocks BK0_128K and BK0_128K are used to compare the stored data bits SDT0_128K and the input bit IBT0 to generate the current signal IT0_128K. Memory blocks BK1_128K and BK1_128K are used to compare the stored data bits SDT1_128K and the input bit IBT1 to generate the current signal IT1_128K, and so on. Memory blocks BK255_128K and BK255_128K are used to compare the stored data bits SDT255_128K and the input bit IBT255 to generate the current signal IT255_128K.

[0163] Correspondingly, the current level of bit line signal BL1 is proportional to the approximate Euclidean distance between the input bits IBT0~IBT255 and the stored data bits SDT0_1~SDT255_1. The current level of bit line signal BL128K is proportional to the approximate Euclidean distance between the input bits IBT0~IBT255 and the stored data bits SDT0_128K~SDT255_128K.

[0164] As shown in Figure 6B, memory block BK0_1 contains sub-blocks SBK0_1_1 to SBK0_9_1. Sub-blocks SBK0_1_1 to SBK0_9_1 each contain memory strings MS0_1_1 to MS0_9_1. Memory block BK0_1' contains sub-blocks SBK0_1_1' to SBK0_9_1'. Sub-blocks SBK0_1_1' to SBK0_9_1' each contain memory strings MS0_1_1' to MS0_9_1'.

[0165] Similarly, memory block BK0_128K contains sub-blocks SBK0_1_128K ~ SBK0_9_128K. Sub-blocks SBK0_1_128K ~ SBK0_9_128K each contain memory strings MS0_1_128K ~ MS0_9_128K. Memory block BK0_128K' contains sub-blocks SBK0_1_128K' ~ SBK0_9_128K'. Sub-blocks SBK0_1_128K' ~ SBK0_9_128K' each contain memory strings MS0_1_128K' ~ MS0_9_128K'.

[0166] Similarly, memory block BK255_1 contains sub-blocks SBK255_1_1 to SBK255_9_1. Sub-blocks SBK255_1_1 to SBK255_9_1 each contain memory strings MS255_1_1 to MS255_9_1. Memory block BK255_1' contains sub-blocks SBK255_1_1' to SBK255_9_1'. Sub-blocks SBK255_1_1' to SBK255_9_1' each contain memory strings MS255_1_1' to MS255_9_1'.

[0167] Similarly, memory block BK255_128K contains sub-blocks SBK255_1_128K ~ SBK255_9_128K. Sub-blocks SBK255_1_128K ~ SBK255_9_128K each contain memory strings MS255_1_128K ~ MS255_9_128K. Memory block BK255_128K' contains sub-blocks SBK255_1_128K' ~ SBK255_9_128K'. Sub-blocks SBK255_1_128K' ~ SBK255_9_128K' each contain memory strings MS255_1_128K' ~ MS255_9_128K'.

[0168] Figure 6C is a schematic diagram illustrating further details of memory blocks BK0_1 and BK0_1' according to some embodiments of the present invention. As shown in Figure 6C, memory string MS0_1_1 includes switching elements T0_1_1_0 to T0_1_1_95 and TS0_1_1 connected in series with each other. Memory string MS0_2_1 includes switching elements T0_2_1_0 to T0_2_1_95 and TS0_2_1 connected in series with each other, and so on. Memory string MS0_9_1 includes switching elements T0_9_1_0 to T0_9_1_95 and TS0_9_1 connected in series with each other.

[0169] Similarly, the memory string MS0_1_1' contains switching elements T0_1_1_0' to T0_1_1_95' and TS0_1_1' connected in series with each other. The memory string MS0_2_1' contains switching elements T0_2_1_0' to T0_2_1_95' and TS0_2_1' connected in series with each other, and so on. The memory string MS0_9_1' contains switching elements T0_9_1_0' to T0_9_1_95' and TS0_9_1' connected in series with each other. However, the embodiments disclosed herein are not limited thereto. In various embodiments, the memory string may contain various numbers of switching elements, that is, 95 may be replaced with other positive integers. For example, 95 may be replaced with 191.

[0170] In some embodiments, each of the control terminals of switching elements T0_1_1_0~T0_9_1_0 and T0_1_1_0'~T0_9_1_0' is used to receive the character line signal WL0. Each of the control terminals of switching elements T0_1_1_1~T0_9_1_1 and T0_1_1_1'~T0_9_1_1' is used to receive the character line signal WL1, and so on. Each of the control terminals of switching elements T0_1_1_93~T0_9_1_93 and T0_1_1_93'~T0_9_1_93' is used to receive the character line signal WL93. Each of the control terminals of switching elements T0_1_1_94~T0_9_1_94 and T0_1_1_94'~T0_9_1_94' is used to receive the character line signal WL94. Each of the control terminals of switching elements T0_1_1_95~T0_9_1_95 and T0_1_1_95'~T0_9_1_95' is used to receive the character line signal WL95. Each of the control terminals of switching elements TS0_1_1~TS0_9_1 is used to receive the character string selection line signal SSL0. Each of the control terminals of switching elements TS0_1_1'~TS0_9_1' is used to receive the character string selection line signal SSL0'.

[0171] In the embodiment shown in Figure 6C, switching elements T0_1_1_95~T0_9_1_95 and T0_1_1_95'~T0_9_1_95' are used to store the storage data bit SDT0_1. The storage data bit SDT0_1 has a logic value of 3, such that each of the switching elements T0_1_1_95~T0_9_1_95 has a critical voltage level LVT, and each of the switching elements T0_1_1_95'~T0_9_1_95' has a critical voltage level HVT. On the other hand, the input bit IBT0 has a logic value of 0 or 1, such that the string select line signals SSL0 and SSL0' have voltage levels HVSSL and LVSSL, respectively.

[0172] During the search operation, the character line signal WL95 has a read voltage level VREAD, and each of the character line signals WL0~WL94 has a pass voltage level VPASS. Correspondingly, memory block BK0_1 generates nine word string current signals with current levels ISL1, such that the current level of current signal IT0_1 is equal to nine times the current level ISL1.

[0173] The scenario of memory blocks BK0_1 and BK0_1' shown in Figure 6C is similar to that of memory blocks BK1 and BK1' shown in Figure 4D. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0174] Figure 6D is a schematic diagram illustrating further details of memory blocks BK255_1 and BK255_1' according to some embodiments of this invention. As shown in Figure 6D, memory string MS255_1_1 includes switching elements T255_1_1_0 to T255_1_1_95 and TS255_1_1 connected in series with each other. Memory string MS255_2_1 includes switching elements T255_2_1_0 to T255_2_1_95 and TS255_2_1 connected in series with each other, and so on. Memory string MS255_9_1 includes switching elements T255_9_1_0 to T255_9_1_95 and TS255_9_1 connected in series with each other.

[0175] Similarly, the memory string MS255_1_1' contains switching elements T255_1_1_0' to T255_1_1_95' and TS255_1_1' coupled in series with each other. The memory string MS255_2_1' contains switching elements T255_2_1_0' to T255_2_1_95' and TS255_2_1' coupled in series with each other, and so on. The memory string MS255_9_1' contains switching elements T255_9_1_0' to T255_9_1_95' and TS255_9_1' coupled in series with each other.

[0176] In some embodiments, each of the control terminals of switching elements T255_1_1_0 to T255_9_1_0 and T255_1_1_0' to T255_9_1_0' is used to receive the character line signal WL0. Each of the control terminals of switching elements T255_1_1_1 to T255_9_1_1 and T255_1_1_1' to T255_9_1_1' is used to receive the character line signal WL1, and so on. Each of the control terminals of switching elements T255_1_1_93 to T255_9_1_93 and T255_1_1_93' to T255_9_1_93' is used to receive the character line signal WL93. Each of the control terminals of switching elements T255_1_1_94~T255_9_1_94 and T255_1_1_94'~T255_9_1_94' is used to receive the character line signal WL94. Each of the control terminals of switching elements T255_1_1_95~T255_9_1_95 and T255_1_1_95'~T255_9_1_95' is used to receive the character line signal WL95. Each of the control terminals of switching elements TS255_1_1~TS255_9_1 is used to receive the string select line signal SSL255. Each of the control terminals of switching elements TS255_1_1'~TS255_9_1' is used to receive the string select line signal SSL255'.

[0177] In the embodiment shown in Figure 6D, switching elements T255_1_1_95~T255_9_1_95 and T255_1_1_95'~T255_9_1_95' are used to store the storage data bit SDT255_1. The storage data bit SDT255_1 has a logic value of 1, such that each of the switching elements T255_1_1_95 and T255_1_1_95'~T255_4_1_95' has a critical voltage level LVT, and each of the switching elements T255_2_1_95~T255_9_1_95 and T255_5_1_95'~T255_9_1_95' has a critical voltage level HVT. On the other hand, the input bit IBT255 has a logic value of 2 or 3, which causes the string select line signals SSL255 and SSL255' to have voltage levels LVSSL and HVSSL, respectively.

[0178] During the search operation, the character line signal WL95 has a read voltage level VREAD, and each of the character line signals WL0~WL94 has a pass voltage level VPASS. Correspondingly, memory block BK255_1' generates four word string current signals with current levels ISL1, such that the current level of current signal IT255_1 is equal to four times the current level ISL1.

[0179] The scenarios of memory blocks BK255_1 and BK255_1' shown in Figure 6D are similar to those of memory blocks BK1 and BK1' shown in Figure 4F. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0180] Figure 6E is a schematic diagram illustrating further details of memory blocks BK0_128K and BK0_128K' according to some embodiments of this invention. As shown in Figure 6E, the memory string MS0_1_128K includes switching elements T0_1_128K_0 to T0_1_128K_95 and TS0_1_128K connected in series with each other. The memory string MS0_2_128K includes switching elements T0_2_128K_0 to T0_2_128K_95 and TS0_2_128K connected in series with each other, and so on. The memory string MS0_9_128K includes switching elements T0_9_128K_0 to T0_9_128K_95 and TS0_9_128K connected in series with each other.

[0181] Similarly, the memory string MS0_1_128K' contains switching elements T0_1_128K_0' to T0_1_128K_95' and TS0_1_128K' connected in series. The memory string MS0_2_128K' contains switching elements T0_2_128K_0' to T0_2_128K_95' and TS0_2_128K' connected in series, and so on. The memory string MS0_9_128K contains switching elements T0_9_128K_0' to T0_9_128K_95' and TS0_9_128K' connected in series.

[0182] In some embodiments, each of the control terminals of switching elements T0_1_128K_0~T0_9_128K_0 and T0_1_128K_0'~T0_9_128K_0' is used to receive the character line signal WL0. Each of the control terminals of switching elements T0_1_128K_1~T0_9_128K_1 and T0_1_128K_1'~T0_9_128K_1' is used to receive the character line signal WL1, and so on. Each of the control terminals of switching elements T0_1_128K_93~T0_9_128K_93 and T0_1_128K_93'~T0_9_128K_93' is used to receive the character line signal WL93. Each of the control terminals of switching elements T0_1_128K_94~T0_9_128K_94 and T0_1_128K_94'~T0_9_128K_94' is used to receive the character line signal WL94. Each of the control terminals of switching elements T0_1_128K_95~T0_9_128K_95 and T0_1_128K_95'~T0_9_128K_95' is used to receive the character line signal WL95. Each of the control terminals of switching elements TS0_1_128K~TS0_9_128K is used to receive the string selection line signal SSL0. Each of the control terminals of switching elements TS0_1_128K'~TS0_9_128K' is used to receive the string selection line signal SSL0'.

[0183] In the embodiment shown in Figure 6E, switching elements T0_1_128K_95~T0_9_128K_95 and T0_1_128K_95'~T0_9_128K_95' are used to store the storage data bit SDT0_128K. The storage data bit SDT0_128K has a logic value of 0, such that each of the switching elements T0_1_128K_95~T0_9_128K_95 has a critical voltage level HVT, and each of the switching elements T0_1_128K_95'~T0_9_128K_95' has a critical voltage level LVT. On the other hand, the input bit IBT0 has a logic value of 0 or 1, such that the string select line signals SSL0 and SSL0' have voltage levels HVSSL and LVSSL, respectively.

[0184] During the search operation, the character line signal WL95 has a read voltage level VREAD, and each of the character line signals WL0~WL94 has a pass voltage level VPASS. Correspondingly, memory blocks BK0_128K and BK0_128K' generate 0 word string current signals with a current level ISL1, such that the current level of the current signal IT0_128K is equal to 0 times the current level ISL1.

[0185] The scenarios of memory blocks BK0_128K and BK0_128K' shown in Figure 6E are similar to those of memory blocks BK1 and BK1' shown in Figure 4A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0186] Figure 6F is a schematic diagram illustrating further details of memory blocks BK255_128K and BK255_128K' according to some embodiments of this invention. As shown in Figure 6F, the memory string MS255_1_128K includes switching elements T255_1_128K_0 to T255_1_128K_95 and TS255_1_128K connected in series with each other. The memory string MS255_2_128K includes switching elements T255_2_128K_0 to T255_2_128K_95 and TS255_2_128K connected in series with each other, and so on. The memory string MS255_9_128K contains switching elements T255_9_128K_0~T255_9_128K_95 and TS255_9_128K that are connected in series with each other.

[0187] Similarly, the memory string MS255_1_128K' contains switching elements T255_1_128K_0' to T255_1_128K_95' and TS255_1_128K' connected in series. The memory string MS255_2_128K' contains switching elements T255_2_128K_0' to T255_2_128K_95' and TS255_2_128K' connected in series, and so on. The memory string MS255_9_128K' contains switching elements T255_9_128K_0' to T255_9_128K_95' and TS255_9_128K' connected in series.

[0188] In some embodiments, each of the control terminals of switching elements T255_1_128K_0 to T255_9_128K_0 and T255_1_128K_0' to T255_9_128K_0' is used to receive the character line signal WL0. Each of the control terminals of switching elements T255_1_128K_1 to T255_9_128K_1 and T255_1_128K_1' to T255_9_128K_1' is used to receive the character line signal WL1, and so on. Each of the control terminals of switching elements T255_1_128K_93 to T255_9_128K_93 and T255_1_128K_93' to T255_9_128K_93' is used to receive the character line signal WL93. Each of the control terminals of switching elements T255_1_128K_94~T255_9_128K_94 and T255_1_128K_94'~T255_9_128K_94' is used to receive the character line signal WL94. Each of the control terminals of switching elements T255_1_128K_95~T255_9_128K_95 and T255_1_128K_95'~T255_9_128K_95' is used to receive the character line signal WL95. Each of the control terminals of switching elements TS255_1_128K~TS255_9_128K is used to receive the string select line signal SSL255. Each of the control terminals of the switching elements TS255_1_128K' to TS255_9_128K' is used to receive the string select line signal SSL255'.

[0189] In the embodiment shown in Figure 6F, switching elements T255_1_128K_95~T255_9_128K_95 and T255_1_128K_95'~T255_9_128K_95' are used to store the storage data bit SDT255_128K. The storage data bit SDT255_128K has a logic value of 3, such that each of the switching elements T255_1_128K_95~T255_9_128K_95 has a critical voltage level LVT, and each of the switching elements T255_1_128K_95~T255_9_128K_95' has a critical voltage level HVT. On the other hand, the input bit IBT0 has a logic value of 2 or 3, such that the string select line signals SSL255 and SSL255' have voltage levels LVSSL and HVSSL, respectively.

[0190] During the search operation, the character line signal WL95 has a read voltage level VREAD, and each of the character line signals WL0~WL94 has a pass voltage level VPASS. Correspondingly, memory blocks BK255_128K and BK255_128K' generate 0 word string current signals with a current level ISL1, such that the current level of the current signal IT255_128K is equal to 0 times the current level ISL1.

[0191] The scenario of memory blocks BK255_128K and BK255_128K' shown in Figure 6F is similar to that of memory blocks BK1 and BK1' shown in Figure 4H. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0192] In some embodiments, the search operations shown in Figures 6C to 6F can be performed simultaneously. In other words, the memory device 610 can simultaneously compare input bits IBT0 and stored data bits SDT0_1 to SDT0_128K, and simultaneously compare input bits IBT255 and stored data bits SDT255_1 to SDT255_128K.

[0193] In some embodiments, the lower the current level of the bit line signal, the higher the similarity between the corresponding stored data bit and the input bits IBT0~IBT255, that is, the smaller the corresponding approximate Euclidean distance.

[0194] For example, in the embodiments shown in Figures 6C to 6F, the current level of bit line signal BL128K is lower than the current level of bit line signal BL1. Correspondingly, the similarity between stored data bits SDT0_128K~SDT255_128K and input bits IBT0~IBT255 is higher than the similarity between stored data bits SDT0_1~SDT255_1 and input bits IBT0~IBT255.

[0195] In some embodiments, the memory cell in this disclosure is referred to as an in-memory searching (IMS) cell. In various embodiments, the IMS cell may be implemented using floating gate memory, split-gate memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, floating dot memory, dynamic random-access memory (DRAM), and / or ferroelectric field-effect transistor (FeFET).

[0196] In various embodiments, the memory device 510 may be implemented by various structures, such as a two-dimensional NAND cache structure, a three-dimensional NAND cache structure, a two-dimensional NOR cache structure, or a three-dimensional NOR cache structure.

[0197] Although the present disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of the present disclosure. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0198] 100, 200: Memory devices MS1, MS1_1~MS1_9, MS1_1'~MS1_9', MS0_1_1~MS0_9_1, MS0_1_1'~MS0_9_1', MS0_1_128K ~MS0_9_128K, MS0_1_128K'~MS0_9_128K', MS255_1_1~MS255_9_1, MS255_1_1'~MS255_9_1', MS255_1_128K ~MS255_9_128K, MS255_1_128K'~MS255_9_128K': Memory string IS1, IS1_1~IS1_9, IS1_1'~IS1_9': String current signal TS, T0~T95, T0_1_1_0~T255_9_128K_95, T0_1_1_0'~T255_9_128K_95', TS0_1_1~TS255_9_128K, TS0_1_1'~TS255_9_128K': Switching elements WL0~WL95: Character line signals SSL, SSL', SSL0, SSL0', SSL255, SSL255': String select line signals HVT, LVT: Critical Voltage Level HVSSL, LVSSL: Voltage Level ISL1: Current Level VREAD: Read voltage level VPASS: Through voltage level RSTR1: String resistor R, r: Resistance values BKP1: Memory Block Pairs BK1, BK1', BK0~BK255, BK0'~BK255', BK0_1~BK255_1, BK0_1'~BK255_1', BK0_128K ~BK255_128K, BK0_128K'~BK255_128K': Memory blocks SBK1_1~SBK1_9, SBK1_1'~SBK1_9', SBK0_1_1~SBK0_9_1, SBK0_1_1'~SBK0_9_1', SBK0_1_128K ~SBK0_9_128, SBK0_1_128K'~SBK0_9_128K', SBK255_1_1~SBK255_9_1, SBK255_1_1'~SBK255_9_1', SBK255_1_128K ~SBK255_9_128K, SBK255_1_128K'~SBK255_9_128K': Sub-blocks T1_1_0~T1_9_95, TS1_1~TS1_9, T1_1_0'~T1_9_95', TS1_1'~TS1_9': Switching elements 300: Schematic diagram IBT1: Input bits IB1, IB1', IT1, IT0_1, IT255_1, IT0_128K, IT255_128K: Current signals 500A, 500B, 500C: Tables 600: Memory System 610: Memory device 620: Output device PLN0~PLN4: Memory plane 611: Page Register 612: Cache register GBL1~GBL128K: Global Bit Line BL1~BL128K: Bit line signals

Claims

1. A memory device comprising a first memory block pair for storing a first stored data bit and for comparing the first stored data bit with a first input bit to generate a first current signal, the first memory block pair comprising: a first memory block for generating a plurality of first string current signals based on a first string select line signal; and a second memory block for generating a plurality of second string current signals based on a second string select line signal, wherein the first string select line signal and the second string select line signal are used to carry the first input bit, the first memory block pair is further used to add the first string current signals and the second string current signals to generate the first current signal, and the current level of the first current signal is proportional to the square of the difference between the encoded value of the first input bit and the logic value of the first stored data bit.

2. The memory device as claimed in claim 1, wherein the first memory block is further configured to add the first string current signals to generate a second current signal, the second memory block is further configured to add the second string current signals to generate a third current signal, and each of the second current signal and the third current signal has a first current level when the first stored data bit has a first logic value and the first input bit has the first logic value or a second logic value.

3. The memory device as claimed in claim 2, wherein when the first stored data bit has the second logic value and the first input bit has the first logic value or the second logic value, the second current signal and the third current signal have a second current level and the first current level, respectively, and the second current level is greater than the first current level.

4. The memory device as claimed in claim 3, wherein when the first stored data bit has a third logic value and the first input bit has the first logic value or the second logic value, the second current signal and the third current signal have a third current level and the first current level, respectively, and the third current level is greater than the second current level.

5. The memory device as claimed in claim 4, wherein when the first stored data bit has a fourth logic value and the first input bit has the first logic value or the second logic value, the second current signal and the third current signal have a fourth current level and the first current level, respectively, and the fourth current level is greater than the third current level.

6. The memory device as claimed in claim 4, wherein when the first stored data bit has the second logic value and the first input bit has the third logic value or a fourth logic value, the second current signal and the third current signal have the first current level and the third current level, respectively.

7. The memory device as claimed in claim 1, wherein when the first input bit has a first logic value or a second logic value, the first string select line signal and the second string select line signal each have a first voltage level and a second voltage level, respectively; and when the first input bit has a third logic value or a fourth logic value, the first string select line signal and the second string select line signal each have the second voltage level and the first voltage level, respectively.

8. The memory device as claimed in claim 7, wherein the first memory block includes a first memory string and a second memory string, each of the first memory string and the second memory string having a first resistance value when the first storage data bit has the first logic value, and the first memory string and the second memory string having a second resistance value and the first resistance value, respectively, when the first storage data bit has the second logic value.

9. The memory device as claimed in claim 8, wherein each of the first memory string and the second memory string has the second resistance value when the first stored data bit has the third logic value.

10. The memory device as claimed in claim 9, wherein the first memory block further includes a third memory string, wherein the third memory string has the first resistance value when the first storage data bit has the third logic value, and each of the first memory string, the second memory string and the third memory string has the second resistance value when the first storage data bit has the fourth logic value.

11. A memory device comprising: a first memory block for generating a plurality of first string current signals based on a first string select line signal and summing the first string current signals to generate a first current signal; and a second memory block for generating a plurality of second string current signals based on a second string select line signal and summing the second string current signals to generate a second current signal, wherein the first string select line signal and the second string select line signal are used to carry a first input bit, the first memory block and the second memory block are further used to store a first storage data bit, wherein when the logic value of the first input bit is equal to the logic value of the first storage data bit, the current level of the first current signal is equal to the current level of the second current signal, and the sum of the current levels of the first current signal and the second current signal is proportional to the square of the difference between the encoded value of the first input bit and the logic value of the first storage data bit.

12. The memory device as claimed in claim 11, wherein when the logic value of the first input bit is different from the logic value of the first stored data bit, the current level of the first current signal is different from the current level of the second current signal.

13. The memory device as claimed in claim 11, wherein the first memory block and the second memory block each include a first switching element and a second switching element, wherein when the first stored data bit has a first logic value, the first switching element and the second switching element each have a first threshold voltage level and a second threshold voltage level, and when the first stored data bit has a second logic value, each of the first switching element and the second switching element has the second threshold voltage level.

14. The memory device as claimed in claim 13, wherein when the first stored data bit has a third logic value, the first switching element and the second switching element respectively have the second critical voltage level and the first critical voltage level.

15. The memory device as claimed in claim 13, wherein the first memory block and the second memory block further include a third switching element and a fourth switching element, wherein when the first stored data bit has the first logic value, the third switching element and the fourth switching element have the first threshold voltage level and the second threshold voltage level, respectively, and when the first stored data bit has the second logic value, the third switching element and the fourth switching element have the first threshold voltage level and the second threshold voltage level, respectively.

16. The memory device as claimed in claim 15, wherein each of the first and third switching elements has the second threshold voltage level when the first stored data bit has a third logic value, and each of the second and fourth switching elements has the first threshold voltage level.

17. The memory device as claimed in claim 13, wherein the first memory block and the second memory block further include a third switching element and a fourth switching element, the third switching element and the fourth switching element being respectively configured to receive the first string select line signal and the second string select line signal, wherein when the first input bit has the first logic value or the second logic value, the first string select line signal and the second string select line signal have a first voltage level and a second voltage level, respectively, and when the first input bit has a third logic value or a fourth logic value, the first string select line signal and the second string select line signal have the second voltage level and the first voltage level, respectively, wherein the first logic value, the second logic value, the third logic value and the fourth logic value are different from each other.

18. A memory system comprising: a plurality of first memory blocks for storing a plurality of first stored data bits and for comparing the first stored data bits with a plurality of input bits to generate a first bit line signal; and a plurality of second memory blocks for storing a plurality of second stored data bits and for comparing the second stored data bits with the input bits to generate a second bit line signal, wherein the first memory blocks and the second memory blocks are further configured to receive a plurality of string select line signals, the string select line signals carrying the input bits, the first memory blocks for storing a third stored data bit among the first stored data bits and for comparing a first input bit with the third stored data bit among the input bits to generate a first current signal, and the current level of the first current signal being proportional to the square of the difference between the encoded value of the first input bit and the logic value of the first stored data bit.

19. The memory system of claim 18, wherein the first memory blocks include a third memory block and a fourth memory block for receiving a first string select line signal and a second string select line signal, respectively, the third memory block and the fourth memory block for storing the third stored data bit, in response to the first input bit having a first logic value or a second logic value, the first string select line signal and the second string select line signal having a first voltage level and a second voltage level, respectively, and the first voltage level being greater than the second voltage level.

20. The memory system of claim 19, wherein the second memory blocks include a fifth memory block and a sixth memory block for receiving the first string select line signal and the second string select line signal, respectively; the fifth memory block and the sixth memory block for storing a fourth storage data bit among the second storage data bits; in response to the third storage data bit having a third logic value; the third memory block and the fourth memory block for generating the first current signal having a first current level; in response to the fourth storage data bit having the first logic value; the fifth memory block and the sixth memory block for generating a second current signal having a second current level, wherein the first current level is greater than the second current level.

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