Masked transmission methods, devices, electronic equipment, storage media, and software products

Abstract

This disclosure relates to the field of image rendering, proposing a mask transmission method, apparatus, electronic device, storage medium, and program product. The method is applied to the rendering pipeline of a graphics processor and includes: performing rasterization on M primitives to determine M first masks; performing depth testing and / or stencil testing on the M first masks to determine M second masks; performing hidden face removal testing on the M first masks based on the M second masks to determine a third mask; splitting the third masks to obtain M fourth masks, where the first and fourth masks corresponding to the same primitive are identical; and inputting the M fourth masks into a pixel shader. This method ensures that the pixel shader can correctly receive the rasterized masks and avoids the defect in a single rendering pipeline where depth / stencil testing and hidden face removal testing cannot be enabled before the masks enter the pixel shader, resulting in a graphics processor with lower design complexity and higher performance.

Description

[Technical Field]

[0001] This disclosure relates to the field of image rendering, and more particularly to a mask transmission method, apparatus, electronic device, storage medium, and program product. [Previous Technology]

[0002] In the graphics processing unit (GPU) rendering pipeline, after primitives undergo vertex processing, clipping, viewport transformation and other operations, they enter the rasterization stage. Rasterization calculates the positions of the pixels (or sampling points) covered by the primitives, and then outputs a mask indicating the information of the pixels (or sampling points) covered by the primitives and the starting coordinates of the pixels to the pixel shader.

[0003] In some application scenarios, in order to improve image rendering quality, the rasterized mask will undergo a depth / stencil test and a hidden surface removal (HSR) test. Enabling the depth / stencil test and the hidden surface removal test may change the rasterized mask and output a new mask. Only then will the mask output by the hidden surface removal test enter the pixel shader.

[0004] With the upgrade of the operating system, an Application Programming Interface (API) emerged that supports pixel shaders to process data using rasterized masks. Since enabling depth / stencil testing and hidden face removal testing may change the rasterized mask, to accommodate the functionality of this API, two rendering pipelines are needed to transmit the rasterized mask and the mask after the hidden face removal test respectively, which greatly increases the design complexity of the graphics processor.

[0005] Existing technologies propose disabling depth / stencil testing and hidden face removal testing before the mask enters the pixel shader, in order to achieve one-way transmission of the rasterized mask to the pixel shader through the rendering pipeline, reducing the design complexity of the graphics processor, at the cost of a decrease in graphics processor performance. Therefore, how to ensure that the rasterized mask is correctly transmitted to the pixel shader while the graphics processor has low design complexity and high performance has become an urgent technical problem to be solved. [Summary of the Invention]

[0006] In view of the above, this disclosure proposes a mask transmission method, apparatus, electronic device, storage medium, and program product. The mask transmission method according to the embodiments of this disclosure improves the hidden face removal test mechanism, which not only ensures that the pixel shader can correctly receive the rasterized mask, but also avoids the defect that the depth / stencil test and hidden face removal test cannot be opened before the mask enters the pixel shader in one rendering pipeline, so that the graphics processor has lower design complexity and higher performance.

[0007] According to one aspect of this disclosure, a mask transmission method is provided, the method being applied to a rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, the method comprising: performing rasterization processing on M primitives respectively to determine M first masks corresponding to the M primitives respectively, where M is an integer greater than 1; performing depth testing and / or stencil testing on the M first masks respectively to determine M second masks corresponding to the M primitives respectively; performing hidden face removal testing on the M first masks based on the M second masks to determine a third mask corresponding to all M primitives; splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively, wherein the first mask and the fourth mask corresponding to the same primitive are the same; and inputting the M fourth masks into the pixel shader in response to a first instruction.

[0008] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. Each first mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits; each second mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits; the third mask comprises N sets of masks corresponding to the N pixels respectively, each set of masks comprising K masks, each mask comprising K bits; and each fourth mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits.

[0009] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The step of performing a hidden surface removal test on the M first masks based on the M second masks to determine the third mask corresponding to all M primitives includes: processing the M first masks based on the M second masks to obtain M fifth masks, each fifth mask comprising N sets of masks corresponding to the N pixels respectively, each set of masks comprising K masks, each mask comprising K bits; performing a hidden surface removal test on the M fifth masks to determine the third mask.

[0010] In one possible implementation, the step of processing the M first masks according to the M second masks to obtain the M fifth masks includes: when the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of masks of the i-th fifth mask, 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, 0 < t ≤ K and are integers; when the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of K second values ​​is used as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0011] In one possible implementation, the step of performing a hidden surface removal test on the M fifth masks to determine the third mask includes: according to the stacking order of the M primitives, using the fifth mask corresponding to the primitive stacked later to cover the fifth mask corresponding to the primitive stacked earlier, thereby obtaining the third mask.

[0012] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: when the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer; when the i-th primitive does not correspond to any of the masks of the j-th set of the third mask, the K second-value masks are used as the j-th mask of the i-th fourth mask.

[0013] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: the t-th bit of the j-th set of the third mask corresponding to the i-th primitive. When using a mask, the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask; the OR operation result of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0014] In one possible implementation, the method further includes: performing a hidden face removal test on the M second masks to determine a sixth mask that corresponds to all M primitives; splitting the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and inputting the M eighth masks into the pixel shader in response to a second instruction.

[0015] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0016] In one possible implementation, the rendering pipeline corresponds to a cache, which is used when performing hidden surface removal tests on the M first masks. The third mask includes N sets of masks corresponding to N pixels respectively. Each set of masks includes K masks, and each mask includes K bits. N and K are integers greater than 1. The cache includes N storage locations. The j-th storage location stores the j-th set of masks of the third mask, where 0 < j ≤ N and is an integer.

[0017] According to another aspect of this disclosure, a mask transmission apparatus is provided, the apparatus being applied to a rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, the apparatus comprising: a rasterization module for rasterizing M primitives respectively, determining M first masks corresponding to the M primitives respectively, where M is an integer greater than 1; a first test module for performing depth testing and / or stencil testing on the M first masks respectively, determining M second masks corresponding to the M primitives respectively; a second test module for performing hidden face removal testing on the M first masks based on the M second masks, determining third masks corresponding to all M primitives; splitting the third masks to obtain M fourth masks corresponding to the M primitives respectively; and inputting the M fourth masks into the pixel shader in response to a first instruction.

[0018] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. Each first mask comprises N masks corresponding to the N pixels, each mask comprising K bits; each second mask comprises N masks corresponding to the N pixels, each mask comprising K bits; the third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, each mask comprising K bits; and each fourth mask comprises N masks corresponding to the N pixels, each mask comprising K bits.

[0019] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The step of performing a hidden surface removal test on the M first masks according to the M second masks to determine the third mask corresponding to all M primitives includes: processing the M first masks according to the M second masks to obtain M fifth masks, each fifth mask including N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, each mask including K bits; performing a hidden surface removal test on the M fifth masks to determine the third mask.

[0020] In one possible implementation, the step of processing the M first masks according to the M second masks to obtain the M fifth masks includes: when the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of masks of the i-th fifth mask, 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, 0 < t ≤ K and are integers; when the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of K second values ​​is used as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0021] In one possible implementation, the step of performing a hidden surface removal test on the M fifth masks to determine the third mask includes: according to the stacking order of the M primitives, using the fifth mask corresponding to the later stacked primitive to cover the fifth mask corresponding to the earlier stacked primitive, thereby obtaining the third mask.

[0022] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: when the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer; when the i-th primitive does not correspond to any of the masks of the j-th set of the third mask, the K second-value masks are used as the j-th mask of the i-th fourth mask.

[0023] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: the t-th bit of the j-th set of the third mask corresponding to the i-th primitive. When using a mask, the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask; the OR operation result of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0024] In one possible implementation, the second test module is further configured to: perform hidden face removal tests on the M second masks to determine a sixth mask that corresponds to all M primitives; split the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and input the M eighth masks into the pixel shader in response to a second instruction.

[0025] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0026] In one possible implementation, the rendering pipeline corresponds to a cache, which is used when performing hidden surface removal tests on the M first masks.

[0027] The third mask includes N sets of masks corresponding to N pixels respectively. Each set of masks includes K masks, and each mask includes K bits. N and K are integers greater than 1.

[0028] The cache includes N storage locations, where the j-th storage location stores the j-th group of the third mask, 0 < j ≤ N and is an integer.

[0029] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0030] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0031] According to another aspect of this disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0032] According to the mask transmission method of this disclosure, by performing rasterization processing on M primitives respectively, M first masks corresponding to the M primitives are determined, where M is an integer greater than 1, and the rasterization of the primitives can be completed to obtain the rasterized first mask; by performing depth testing and / or stencil testing on the M first masks respectively, M second masks corresponding to the M primitives can be determined, so that the graphics processor has the function of implementing depth testing and / or stencil testing; based on the M second masks, hidden face removal testing is performed on the M first masks to determine the third mask corresponding to all M primitives, and the third mask is split to obtain M fourth masks corresponding to the M primitives, so that the graphics processor has the function of implementing hidden face removal testing; the first mask and the fourth mask corresponding to the same primitive are the same, and in response to the first instruction, the M fourth masks are input into the pixel shader, ensuring that the pixel shader can correctly receive the rasterized mask. The mask transmission method of this disclosure is executed by a single rendering pipeline. It eliminates the need to disable early depth / stencil testing, reducing the amount of data entering the pixel shader and lowering the data processing pressure on the graphics processor. It also eliminates the need to enable late depth / stencil testing, reducing the rendering cycle time. Furthermore, it eliminates the need to disable hidden face removal testing, improving graphics processor performance. In summary, the mask transmission method of this disclosure improves the hidden face removal testing mechanism, ensuring that the pixel shader can correctly receive the rasterized mask while avoiding the drawback of depth / stencil testing and hidden face removal testing not being enabled before the mask enters the pixel shader in a single rendering pipeline. This results in a graphics processor with lower design complexity and higher performance.

[0033] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Implementation Method

[0035] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0036] The term “exemplary” as used herein means “serving as an example, embodiment or illustration”. Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0037] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art should understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0038] The principle of mask generation and transmission is introduced below.

[0039] In the graphics processing unit (GPU) rendering pipeline, after primitives undergo vertex processing, clipping, viewport transformation, and other operations, they enter the rasterization stage. Rasterization calculates the positions of the pixels (or sampling points) covered by the primitives, and then outputs a mask indicating the pixel (or sampling point) information covered by the primitives, along with the starting coordinates of the pixels, to the pixel shader for shading. The mask indicates the coverage of pixels (or sampling points) by the primitives.

[0040] Figure 1 shows an example of a rasterized mask.

[0041] As shown in Figure 1, the pixel block includes 4 pixels P3-P0. Assuming that each pixel corresponds to a sampling point and is the center of the pixel during rasterization, the triangular primitive covers the sampling points of pixels P2-P0 but does not cover the sampling point of pixel P3. One sampling point corresponds to one bit of binary mask. The mask of the covered sampling point can be 1, and the mask of the uncovered sampling point can be 0. Therefore, the mask corresponding to this pixel block can be 0111 (in the order of pixels P3-P0).

[0042] The mask output from the rasterization stage can be called the raw mask. Since the starting coordinates of the pixels are known, it is easy to calculate whether each pixel is covered by combining the mask and the starting coordinates. Of course, in a graphics processor, a pixel block may contain more than 4 pixels; it may be a pixel block with a size of 32x32 or 8x8. For these pixel blocks containing a large number of pixels, it is more convenient to pass information about whether a pixel (or sampling point) has a value in the rendering pipeline by using a mask and starting coordinates.

[0043] If multisample antialiasing (MSAA) is used during rasterization, more sampling points will be rasterized per pixel, and the number of mask bits will also increase. Figure 2 shows another example of a rasterized mask. For ease of understanding, the following description uses 4 sampling points per pixel (i.e., MSAA 4x) as an example. It should be understood that this disclosure is not limited to this, and for example, it also applies to cases with 2 to 16 sampling points per pixel (e.g., MSAA 2x, MSAA 8x, MSAA 16x).

[0044] As shown in Figure 2, the pixel block includes 4 pixels P3-P0. Each pixel includes 4 sampling points, and the pixel block includes a total of 16 sampling points. One sampling point corresponds to one bit of binary mask, so each pixel has a 4-bit mask, and the pixel block mask has 16 bits. The sampling points of pixel P3 are not covered, so the mask of pixel P3 is 0000. The sampling points of pixel P2 are all covered, so the mask of pixel P2 is 1111. The first and third sampling points of pixel P1 (in the order from bottom to top, which is the same order in the following text) are not covered, while the second and fourth sampling points are covered, so the mask of pixel P1 is 0101. The sampling points of pixel P0 are all covered, so the mask of pixel P0 is 1111. Therefore, the mask of the pixel block is 0000 1111 0101 1111 (in the order of pixels P3-P0).

[0045] In some application scenarios, to improve image rendering quality, the rasterized mask undergoes a depth / stencil test. This test determines whether the coverage of pixels (or sampling points) by the primitives determined by rasterization is valid, and some originally valid coverages may be deemed invalid. The mask output by the depth / stencil test indicates the sampling point information covered by the primitives after the depth / stencil test. Only then does the mask output by the depth / stencil test enter the pixel shader. This depth / stencil test performed before the mask enters the pixel shader is also called an early depth / stencil test. Figure 3 shows an example of a mask after the early depth / stencil test.

[0046] As shown in Figure 3, the original mask of the rasterized pixel block is 0000 1111 0101 1111. The depth / stencil test may determine that the primitive does not cover the 4th sampling point of pixel P0 and the 1st and 3rd sampling points of pixel P2. Based on this determination, the mask 0000 0101 0101 1110 can be output. The mask output by the depth / stencil test can be called the active mask. If all 4 bits of the mask corresponding to a pixel are 0, the pixel shader does not need to determine the color of the pixel when it is covered by the triangular primitive. Therefore, the depth / stencil test can greatly reduce the data processing cost of the pixel shader.

[0047] For rendering pipelines employing a tile-based deferred rendering (TBDR) architecture, the mask after the depth / stencil test must also undergo a hidden surface removal (HSR) test. This test determines whether the primitive's coverage of pixels (or sampling points) determined after the depth / stencil test is valid. Some coverages that were originally valid may be deemed invalid because they are covered by pixels or sampling points of other primitives. The mask output by the hidden surface removal test indicates the sampling point information covered by the primitive after the hidden surface removal test. Only then will the mask output by the hidden surface removal test enter the pixel shader.

[0048] Figure 4 shows an example of a mask after a hidden face removal test. For clarity, only one pixel is shown in Figure 4.

[0049] As shown in Figure 4, assume there are 4 sampling points during pixel rasterization. The mask after rasterization of primitive A can be 1111, and the mask output by the depth / stencil test can be 1110. In this case, primitive A covers the 1st to 3rd sampling points (in bottom-to-top order). The mask after rasterization of primitive B can be 1101, and the mask output by the depth / stencil test can be 1101. In this case, primitive B covers the 1st, 2nd, and 4th sampling points (in bottom-to-top order). Assuming primitive B covers primitive A, the 1st, 2nd, and 4th sampling points of the pixel (in bottom-to-top order) will display the color of primitive B, and the 3rd sampling point will display the color of primitive A. Whether the 1st, 2nd, and 4th bits of the mask corresponding to primitive A input to the pixel shader have values ​​does not affect the shading. To save shading costs, the 1st, 2nd, and 4th bits of the mask can be 0, that is, the mask output by primitive A after the hidden face removal test is 0010. Primitive B is not covered by other primitives, so the mask of primitive B output by the hidden face removal test is still 1101. In this case, the mask of primitive A input to the pixel shader and the mask of primitive A after rasterization differ.

[0050] With operating system upgrades, application programming interfaces (APIs) such as DirectX 11 emerged that support pixel shaders using rasterized masks for data processing. These APIs support using rasterized masks as input attributes for data calculations or centroid interpolation. Since enabling depth / stencil testing and hidden face removal testing may alter the rasterized mask, two rendering pipelines are needed to transmit the rasterized mask and the mask after hidden face removal testing, respectively, to accommodate the functionality of this API. Due to limitations in mask cache size, this operation significantly increases the design complexity of the graphics processor.

[0051] Existing technical solutions employ a simplified approach: from the rasterization stage to the pixel shader, the mask is still transmitted through a single rendering pipeline. If it is known in advance that the pixel shader uses the rasterized mask, the early depth / stencil test is directly disabled, and the hidden face removal test is also disabled, thus ensuring that the mask obtained by the pixel shader is consistent with the rasterized mask. The depth / stencil test is then initiated after the pixel processor completes shading. This depth / stencil test, performed after the mask enters the pixel shader, is also known as the late depth / stencil test.

[0052] While the existing technical solution achieves the transmission of the rasterized mask to the pixel shader through a single rendering pipeline, reducing the design complexity of the graphics processor, it comes at the cost of reduced graphics processor performance. The inventors have found that this performance reduction manifests in the following ways: 1. Forcibly disabling early depth / stencil testing may lead to a surge in the number of pixels entering the pixel shader. For example, in scenes involving overdraw, other pixels may be drawn again at the location of an existing pixel. Previously, early depth / stencil testing could remove most pixels in advance, but now the masks of these pixels must enter the pixel shader, increasing the data processing pressure on the graphics processor. 2. Forcibly enabling late depth / stencil testing will correspondingly extend the entire rendering cycle. 3. Hidden face removal testing is a key technology for improving performance in tile-based deferred rendering architectures. Forcibly disabling this function will undoubtedly lead to a further decrease in graphics processor performance. Therefore, how to ensure the correct transmission of the rasterized mask to the pixel shader while maintaining low design complexity and high performance for the graphics processor has become an urgent technical problem to be solved.

[0053] In view of this, the present disclosure proposes a mask transmission method, apparatus, electronic device, storage medium, and program product. The mask transmission method according to the embodiments of the present disclosure improves the hidden face removal test mechanism, which not only ensures that the pixel shader can correctly receive the rasterized mask, but also avoids the defect that the depth / stencil test and hidden face removal test cannot be opened before the mask enters the pixel shader in one rendering pipeline, so that the graphics processor has lower design complexity and higher performance.

[0054] Figures 5a and 5b illustrate exemplary application scenarios of the mask transmission method according to embodiments of the present disclosure.

[0055] In the application scenarios shown in Figures 5a and 5b, the graphics processor includes a rendering pipeline that supports tile-based deferred rendering and can be used to render an image comprising N pixels (N is an integer greater than 1). This rendering pipeline may include a rasterization module (for rasterization processing), a first test module (for depth / stencil testing), a second test module (for hidden face removal testing), and pixel shaders. The first test module may perform only depth testing, only stencil testing, or both depth and stencil testing; this disclosure does not limit this.

[0056] In the application scenario shown in Figure 5a, in the rendering pipeline, multiple primitives are input into the rasterization module after vertex processing, clipping, and viewport transformation. After rasterization is completed, one mask (i.e., the first mask mentioned below) is output to the first test module. After the first test module completes the depth / stencil test, two masks (i.e., the first mask and the second mask mentioned below) are output to the second test module. After the second test module completes the hidden face removal test (and splitting), one mask (i.e., the fourth mask mentioned below) can be output to the pixel shader. This mask and the rasterized mask (i.e., the first mask mentioned below) can be the same.

[0057] In the application scenario shown in Figure 5b, in the rendering pipeline, multiple primitives are input into the rasterization module after vertex processing, clipping, and viewport transformation. After rasterization is completed, one mask (i.e., the first mask mentioned below) is output to the first test module. After the first test module completes the depth / stencil test, two masks (i.e., the first mask and the second mask mentioned below) are output to the second test module. After the second test module completes the hidden face removal test (and splitting), two masks can be output to the pixel shader. The first mask (i.e., the fourth mask mentioned below) and the rasterized mask (i.e., the first mask mentioned below) can be the same. The second mask (i.e., the eighth mask mentioned below) and the mask obtained after rasterization, depth / stencil test, and hidden face removal test according to the prior art can be the same.

[0058] The functions of each module included in the rendering pipeline shown in Figures 5a and 5b can be found in the following description of the mask transmission method flow.

[0059] Figure 6 shows a schematic diagram of the flow of the mask transmission method according to an embodiment of the present disclosure.

[0060] As shown in Figure 6, in one possible implementation, this disclosure proposes a mask transmission method. The method is applied to the rendering pipeline of a graphics processor, which includes a pixel shader. The method includes: Step S61, performing rasterization on M primitives to determine M first masks corresponding to the M primitives, where M is an integer greater than 1; Step S62, performing depth testing and / or stencil testing on the M first masks to determine M second masks corresponding to the M primitives; Step S63, performing hidden face removal testing on the M first masks based on the M second masks to determine third masks corresponding to all M primitives; Step S64, splitting the third masks to obtain M fourth masks corresponding to the M primitives, where the first and fourth masks corresponding to the same primitive are the same; Step S65, in response to a first instruction, inputting the M fourth masks into the pixel shader.

[0061] For example, the structure of the rendering pipeline can be seen in the examples of Figures 5a and 5b.

[0062] Step S61 can be completed by the rasterization module. The M primitives (primitive 1 - primitive M) received by the rasterization module can be primitives after vertex processing, clipping, and viewport transformation. M can be an integer greater than 1. The rasterization module performs rasterization processing on the M primitives respectively, and can determine the M first masks (mask G1 - mask GM) corresponding to the M primitives. Among them, primitive 1 corresponds to mask G1, ..., primitive M corresponds to mask GM.

[0063] The rendering pipeline is used to render M primitives to generate an image containing N pixels (N is an integer greater than 1). Therefore, when performing rasterization processing on any primitive in step S61, it can determine which pixels out of the N pixels the primitive covers, and specifically which sampling points of the pixels it covers. The first mask corresponding to the primitive, determined by the rasterization processing, can indicate the sampling point information covered by the primitive after rasterization processing. An example of the first mask can be found in the relevant description in Figure 7 below.

[0064] Rasterization can be implemented based on existing technologies, and the specific implementation method of rasterization will not be elaborated here.

[0065] The rasterization module can output M first masks (mask G1-mask GM) and the starting address of the pixel (not shown) to the first test module. Step S62 can be completed by the first test module.

[0066] The first test module executes step S62, performing depth testing and / or template testing on the M first masks (mask G1-mask GM) respectively, to determine the M second masks (mask S1-mask SM) corresponding to the M primitives. The mask determined by depth testing and / or template testing of mask G1 can be mask S1, and the mask determined by depth testing and / or template testing of mask GM can be mask SM. Primitive 1 corresponds to mask G1, ..., primitive M corresponds to mask GM; therefore, primitive 1 corresponds to mask S1, ..., primitive M corresponds to mask SM. An example of the second mask can be found in the relevant description in Figure 7 below.

[0067] When performing step S62 to perform depth testing and / or stencil testing on the first mask corresponding to any primitive, it may be necessary to determine whether the coverage of the primitive indicated by the first mask on each sampling point is still valid. If the rasterization process determines that the primitive covers the sampling point, and the depth testing and / or stencil testing determines that the primitive no longer covers the sampling point, then the coverage of the primitive indicated by the first mask on the sampling point may be invalid. Conversely, if the rasterization process determines that the primitive covers the sampling point, and the depth testing and / or stencil testing determines that the primitive still covers the sampling point, then the coverage of the primitive indicated by the first mask on the sampling point may be valid.

[0068] The first test module can determine the second mask corresponding to the graphic element based on the first mask corresponding to the graphic element and the effective coverage of the graphic element to each sampling point after the depth test and / or template test, so that the second mask indicates the sampling point information covered by the graphic element after the depth test and / or template test.

[0069] Deep testing and template testing can be implemented based on existing technologies, and the specific implementation methods of deep testing and template testing will not be elaborated here.

[0070] The first test module can output M first masks (mask G1-mask GM) and M second masks (mask S1-mask SM) to the second test module via two separate paths. The starting address of the pixel can be output via either path. Steps S63-S65 can be completed by the second test module.

[0071] The second test module first executes step S63, performing a hidden surface removal test on the M first masks based on the M second masks, and determining a third mask D3 corresponding to all M primitives. That is, the number of first masks and second masks are M, and the number of third masks is 1. The implementation method of the hidden surface removal test used in step S63 can be different from the hidden surface removal test in the prior art. For example, when performing the hidden surface removal test in step S63, the pixel-level mask in each first mask can be extended to the sampling point level to obtain the corresponding fifth mask (the extension method is determined by the second mask corresponding to each first mask). Then, the fifth masks corresponding to multiple primitives are layered according to the coverage order of the primitives, and the coverage result of the final M fifth masks is the third mask D3. Therefore, the third mask D3 corresponds to all M primitives. At this time, the third mask D3 can indicate which sampling points each primitive serves as the top primitive, and indicate the coverage of each sampling point in the pixel where the primitive is located when it serves as the top primitive of the sampling point. (When the fifth mask is completed, if the fifth mask corresponding to a certain sampling point covered by a certain primitive is still valid, that primitive is the top-level primitive of that sampling point). Examples of the extension method and the fifth and third masks can be found in the relevant descriptions in Figure 7.

[0072] The second test module then executes step S64 to split the third mask D3. The purpose of splitting is to separate the parts of the third mask D3 that are related to each primitive, and obtain M fourth masks (mask Y1-mask YM) that are the same as the M first masks. Among them, primitive 1 corresponds to mask Y1, ..., primitive M corresponds to mask YM.

[0073] The user can provide instructions on which mask to use for data processing in the pixel shader. For example, a first instruction can be given when the pixel shader uses a rasterized mask for data processing. The second test module then executes step S65, and in response to the first instruction, can input M fourth masks, identical to the M first masks, into the pixel shader. Simultaneously, the starting address of the pixel (not shown) can also be output to the pixel shader. When the pixel shader uses the fourth masks for data processing, the effect is the same as using the rasterized mask (first mask); that is, the pixel shader can output color data for N pixels based on the mask Y1-mask YM and the starting address of the pixel. Subsequently, an image to be rendered to the screen can be generated based on this color data.

[0074] If it can be determined in advance that the pixel shader uses a rasterized mask for data processing, the first indication can also be stored in a specific location, such as memory, and after the graphics processor's rendering pipeline is started, the processor reads the first indication from memory and outputs it to the rendering pipeline. This disclosure does not limit the source of the first indication.

[0075] In this case, the graphics processor can make the mask of the input pixel shader consistent with the rasterized mask while using one rendering pipeline and retaining the early depth / stencil test and hidden face removal test, thereby conforming to the capabilities of specific application programming interfaces such as DirectX 11.

[0076] According to the mask transmission method of this disclosure, by performing rasterization processing on M primitives respectively, M first masks corresponding to the M primitives are determined, where M is an integer greater than 1, and the rasterization of the primitives can be completed to obtain the rasterized first mask; by performing depth testing and / or stencil testing on the M first masks respectively, M second masks corresponding to the M primitives can be determined, so that the graphics processor has the function of implementing depth testing and / or stencil testing; based on the M second masks, hidden face removal testing is performed on the M first masks to determine the third mask corresponding to all M primitives, and the third mask is split to obtain M fourth masks corresponding to the M primitives, so that the graphics processor has the function of implementing hidden face removal testing; the first mask and the fourth mask corresponding to the same primitive are the same, and in response to the first instruction, the M fourth masks are input into the pixel shader, ensuring that the pixel shader can correctly receive the rasterized mask. The mask transmission method of this disclosure is executed by a single rendering pipeline. It eliminates the need to disable early depth / stencil testing, reducing the amount of data entering the pixel shader and lowering the data processing pressure on the graphics processor. It also eliminates the need to enable late depth / stencil testing, reducing the rendering cycle time. Furthermore, it eliminates the need to disable hidden face removal testing, improving graphics processor performance. In summary, the mask transmission method of this disclosure improves the hidden face removal testing mechanism, ensuring that the pixel shader can correctly receive the rasterized mask while avoiding the drawback of depth / stencil testing and hidden face removal testing not being enabled before the mask enters the pixel shader in a single rendering pipeline. This results in a graphics processor with lower design complexity and higher performance.

[0077] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0078] Because the rendering pipeline retains the hidden face removal test functionality, it can support tile-based deferred rendering. It is understood that the rendering pipeline can also support other rendering methods that require hidden face removal testing, as implemented in existing technologies. This disclosure does not limit the specific type of rendering supported by the rendering pipeline.

[0079] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. Each first mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits; each second mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits; each third mask comprises N sets of masks corresponding to the N pixels respectively, each set of masks comprising K masks, each mask comprising K bits; and each fourth mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits.

[0080] For example, the rendering pipeline can be used to render M primitives to generate an image comprising N pixels, each pixel including K sampling points. K can be an integer greater than 1, such as equal to 2, 4, 6, 8, 16, etc. The specific value of K is not limited in the embodiments of this disclosure.

[0081] M primitives correspond to M first masks, therefore the first masks are primitive-level masks. Each primitive includes N pixels, so each first mask includes N masks corresponding to N pixels, and each mask included in the first mask is a pixel-level mask. Each pixel includes K sampling points. During rasterization processing in step S61, one sampling point corresponds to one bit of binary mask; therefore, each mask included in the first mask may include K bits.

[0082] M primitives correspond to M second masks, therefore the second masks are primitive-level masks. Each primitive includes N pixels, so each second mask includes N masks corresponding to N pixels, and each mask in the second mask is a pixel-level mask. Each pixel includes K sampling points. When performing depth testing and / or template testing in step S62, one sampling point corresponds to one bit of binary mask, therefore each mask in the second mask can include K bits.

[0083] The third mask corresponds to all M primitives, therefore the third mask is an image-level mask. Each primitive includes N pixels, which allows the third mask to include N sets of masks corresponding to each of the N pixels. Each pixel includes K sampling points. When performing the hidden surface removal test in step S63, each set of masks in the third mask can include K masks corresponding to the K sampling points. That is, each mask in each set corresponds to a sampling point, therefore each set of masks is a sampling point-level mask. Each mask in each set can include K bits.

[0084] M primitives correspond to M fourth masks, therefore the fourth mask is a primitive-level mask. Each primitive includes N pixels, so each fourth mask includes N masks corresponding to N pixels, and each mask included in the fourth mask is a pixel-level mask. Each pixel includes K sampling points. During the splitting process in step S64, one sampling point corresponds to one bit of binary mask, therefore each mask included in the fourth mask can include K bits.

[0085] Figure 7 shows an example of the mask determined in each step of the mask transmission method according to an embodiment of the present disclosure and the indicated sampling point coverage.

[0086] Assuming M=2, N=4, and K=4, the mask transmission method of this embodiment is applied to a scene where two primitives (primitive 1 and primitive 2) are rendered. The rendered image includes four pixels, and each pixel includes four sampling points. For clarity, Figure 7 only shows the coverage of the four sampling points of the first pixel by primitive 1 and primitive 2.

[0087] After the rasterization process in step S61, primitive 1 can obtain mask G1 (first mask). Mask G1 may include masks G11-G14, where mask G11 corresponds to the first pixel. Referring to Figure 7, mask G11 may include 4 bits. After rasterization, primitive 1 can cover the first to fourth sampling points of the first pixel (in order from bottom to top), so mask G11 can be 1111.

[0088] After rasterization in step S61, primitive 2 can obtain mask G2 (first mask). Mask G2 may include masks G21-G24, where mask G21 corresponds to the first pixel. Referring to Figure 7, mask G21 may include 4 bits. After rasterization, primitive 2 can cover the 1st, 2nd, and 4th sampling points of the first pixel (in bottom-to-top order), so mask G21 can be 1101.

[0089] After the depth test and / or stencil test in step S62, mask G1 (first mask) can be obtained as mask S1 (second mask). Mask S1 corresponds to primitive 1. Mask S1 may include masks S11-S14, where mask S11 corresponds to the first pixel. Referring to Figure 7, mask S11 may include 4 bits. After the depth test and / or stencil test, the coverage of primitive 1 on the second sampling point of the first pixel becomes invalid, while the coverage of primitive 1 on the first, third, and fourth sampling points of the first pixel remains valid (in bottom-to-top order). Therefore, mask S11 can be 1011.

[0090] Mask G2 (first mask) can be obtained after the depth test and / or stencil test in step S62 to obtain mask S2 (second mask). Mask S2 corresponds to primitive 2. Mask S2 may include masks S21-S24, where mask S21 corresponds to the first pixel. Referring to Figure 7, mask S21 may include 4 bits. After the depth test and / or stencil test, the coverage of primitive 2 on the 1st, 2nd, and 4th sampling points of the first pixel is still valid (in the order from bottom to top), so mask S21 can be 1101.

[0091] After the hidden surface removal test in step S63, masks G1 and G2 (first masks) yield mask D3 (third mask). Mask D3 corresponds to primitive 1 and primitive 2. Mask D3 may include a first group of masks D31 to a fourth group of masks D34, where the first group of masks D31 corresponds to the first pixel. Referring to Figure 7, the first group of masks D31 may include masks D311 to D314, where mask D311 corresponds to the first sampling point s0 of the first pixel, mask D312 corresponds to the second sampling point s1 of the first pixel, mask D313 corresponds to the third sampling point s2 of the first pixel, and mask D314 corresponds to the fourth sampling point s3 of the first pixel. Masks D311-D314 may include 4 bits. In the example of Figure 7, mask D311 can be 1101, mask D312 can be 1101, mask D313 can be 1111, and mask D314 can be 1101. Mask D3 can be 1101 1101 1111 1101. An exemplary method for determining the values ​​of masks D311-D314 can be found in the further description of step S63 below.

[0092] After the splitting process in step S64, mask D3 (third mask) yields mask Y1 and mask Y2 (fourth mask). Mask Y1 corresponds to primitive 1, and mask Y2 corresponds to primitive 2. Mask Y1 may include masks Y11-Y14, where mask Y11 corresponds to the first pixel. Mask Y11 may include 4 bits; in the example of Figure 7, mask Y11 may be 1111. Mask Y2 may include masks Y21-Y24, where mask Y21 corresponds to the first pixel. Mask Y21 may include 4 bits; in the example of Figure 7, mask Y21 may be 1101. An exemplary method for determining the values ​​of masks Y11 and Y21 can be found in the further description of step S63 below.

[0093] The following describes an exemplary implementation of the hidden face removal test in step S63.

[0094] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. Step S63 includes: processing the M first masks according to the M second masks to obtain M fifth masks, each fifth mask including N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, each mask including K bits; performing a hidden surface removal test on the M fifth masks to determine the third mask.

[0095] For example, in step S63, M first masks can be processed based on M second masks to obtain M fifth masks. Therefore, the fifth masks are primitive-level masks. When processing the M first masks to obtain M fifth masks, the pixel-level mask in each first mask can be extended to the sampling point level to obtain the fifth mask corresponding to that first mask. Each first mask includes N masks corresponding to N pixels, and each fifth mask includes N groups of masks corresponding to N pixels. That is, one mask (pixel level) in the first mask is extended into one group of masks (sampling point level) in the fifth mask. Each mask in the first mask includes K bits. The number of masks included in each extended group of masks can be equal to the number of sampling points of each pixel. That is, each group of masks can include K masks, and each mask can include K bits.

[0096] Still using Figure 7 as an example, step S63 can process mask G1 (first mask) according to mask S1 (second mask) to obtain mask G_1 (fifth mask). Mask G_1 may include the first group of masks G_11 to the fourth group of masks G_14, where the first group of masks G_11 corresponds to the first pixel. Referring to Figure 7, the first group of masks G_11 may include masks G_111 to G_114, where mask G_111 corresponds to the first sampling point s0 of the first pixel, mask G_112 corresponds to the second sampling point s1 of the first pixel, mask G_113 corresponds to the third sampling point s2 of the first pixel, and mask G_114 corresponds to the fourth sampling point s3 of the first pixel. Masks G_111-G_114 may include 4 bits. In the example of Figure 7, mask G_111 can be 1111, mask G_112 can be 0000, mask G_113 can be 1111, and mask G_114 can be 1111. Mask G_11 can be 1111 0000 1111 1111. An exemplary method for determining the values ​​of masks G_111-G_114 can be found in the further description of step S63 below.

[0097] Step S63 can process mask G2 (first mask) according to mask S2 (second mask) to obtain mask G_2 (fifth mask). Mask G_2 may include the first group of masks G_21 to the fourth group of masks G_24, where the first group of masks G_21 corresponds to the first pixel. Referring to Figure 7, the first group of masks G_21 may include masks G_211 to G_214, where mask G_211 corresponds to the first sampling point s0 of the first pixel, mask G_212 corresponds to the second sampling point s1 of the first pixel, mask G_213 corresponds to the third sampling point s2 of the first pixel, and mask G_214 corresponds to the fourth sampling point s3 of the first pixel. Masks G_211-G_214 may include 4 bits. In the example of Figure 7, mask G_211 can be 1101, mask G_212 can be 1101, mask G_213 can be 0000, and mask G_214 can be 1101. Mask G_21 can be 1101 1101 0000 1101. An exemplary method for determining the values ​​of masks G_211-G_214 can be found in the further description of step S63 below.

[0098] After the expansion is completed, the fifth mask corresponding to the M primitives is used as the object of the hidden surface removal test, and the third mask is obtained by processing it according to the implementation method of the hidden surface removal test in the prior art. The hidden surface removal test does not change the number of bits in the mask, so the data structure of the fifth mask and the third mask can be the same, both including N sets of masks, each set of masks including K masks, and each mask including K bits. In this case, each mask in each set of masks in the third mask corresponds to a sampling point, so each set of masks in the third mask is also a mask at the sampling point level.

[0099] For example, masks G_1 and G_2 can be used as objects for hidden surface removal testing, ultimately resulting in a third mask D3. The third mask D3 can include a first group of masks D31 to a fourth group of masks D34, where the first group of masks D31 corresponds to the first pixel. Referring to Figure 7, the first group of masks D31 can include masks D311 to D314, where mask D311 corresponds to the first sampling point s0 of the first pixel, mask D312 corresponds to the second sampling point s1 of the first pixel, mask D313 corresponds to the third sampling point s2 of the first pixel, and mask D314 corresponds to the fourth sampling point s3 of the first pixel. Masks D311-D314 can each include 4 bits. Mask D311 can be 1101, mask D312 can be 1101, mask D313 can be 1111, and mask D314 can be 1101. The mask D31 can be 1101 1101 1111 1101. An exemplary method for determining the values ​​of masks D311-D314 can be found in the further description of step S63 below.

[0100] The following describes an exemplary method, with reference to Figure 7, for extending a mask corresponding to a pixel in the first mask to a set of masks corresponding to the pixel in the fifth mask.

[0101] In one possible implementation, in step S63, the M first masks are processed according to the M second masks to obtain the M fifth masks, including: when the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of masks of the i-th fifth mask, 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, 0 < t ≤ K and is an integer; when the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of K second values ​​is used as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0102] For example, the i-th primitive (0 < i ≤ M and is an integer) corresponds to the i-th second mask, the i-th first mask, and the i-th fifth mask. For example, the first primitive (primitive 1) corresponds to the first second mask (S1), the first first mask (G1), and the first fifth mask (G_1). The second primitive (primitive 2) corresponds to the second second mask (S2), the second first mask (G2), and the second fifth mask (G_2).

[0103] The first value may, for example, represent a value indicating that the sampling point is covered, and in this embodiment, it may be 1. The second value may, for example, represent a value indicating that the sampling point is not covered, and in this embodiment, it may be 0. It is understood that the first value and the second value may also be set to other values, as long as the first value indicates that the sampling point is covered and the second value indicates that the sampling point is not covered, this disclosure does not impose any restrictions on this.

[0104] The example in Figure 7 shows the first pixel, taking j=1 as an example. When the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of the i-th fifth mask. Alternatively, when the t-th bit of the first mask (mask S11) of the first second mask (S1) is equal to the first value (1), the first mask (G11) of the first first mask (G1) is used as the t-th mask of the first group of the first fifth mask (G_1) G_11. For example, when t=1, the first bit of mask S11 is equal to the first value (1), and mask G11 (1111) is used as the first mask G_111 of the first group of the first mask G_11. Therefore, mask G_111 can be 1111. Similarly, at t=3, the third bit of mask S11 equals the first value (1), and mask G11 is used as the third mask G_113 of the first group of masks G_11. Therefore, mask G_113 can be 1111. At t=4, the fourth bit of mask S11 equals the first value (1), and mask G11 is used as the fourth mask G_114 of the first group of masks G_11. Therefore, mask G_114 can be 1111.

[0105] When the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of K second values ​​is used as the t-th mask of the j-th group of the i-th fifth mask. Alternatively, when the t-th bit is equal to the second value (0), the mask of 4 (K=4) second values ​​(0) is used as the t-th mask of the first group of the first fifth mask (G_1) G_11. For example, when t=2, the second bit of the mask S11 is equal to the second value (0), and the 4 zeros are used as the second mask G_112 of the first group of the mask G_11. Therefore, the mask G_112 can be 0000.

[0106] In this case, the first group mask G_11 of the first fifth mask (G_1) can be 1111 0000 1111 1111.

[0107] Similarly, when the t-th bit of the first mask (mask S21) of the second second mask (S2) is equal to the first value (1), the first mask (G21) of the second first mask (G2) is used as the t-th mask of the first group mask G_21 of the second fifth mask (G_2). When the t-th bit is equal to the second value (0), the mask of the four second values ​​(0) is used as the t-th mask of the first group mask G_21 of the second fifth mask (G_2). Referring to Figure 7, the mask G21 is 1101. The first bit of the mask S21 (1101) is 1, the second bit is 1, the third bit is 0, and the fourth bit is 1. The first group of masks G_21 includes masks G_211-mask G_214. Therefore, mask G_211 can be 1101, mask G_212 can be 1101, mask G_213 can be 0000, and mask G_214 can be 1101.

[0108] In this case, the first group mask G_21 of the second fifth mask (G_2) can be 1101 1101 0000 1101.

[0109] By analogy, each first mask corresponding to each primitive can be expanded into a fifth mask. The expansion method of each first mask will not be elaborated here.

[0110] In this way, the pixel-level mask can be extended to the sampling point-level mask.

[0111] The following describes an exemplary method for performing hidden surface removal tests on M fifth masks in accordance with the prior art.

[0112] In one possible implementation, a hidden surface removal test is performed on the M fifth masks to determine the third mask, including: according to the stacking order of the M primitives, the fifth mask corresponding to the primitive stacked later is used to cover the fifth mask corresponding to the primitive stacked earlier to obtain the third mask.

[0113] For example, to determine the third mask by performing a hidden face removal test on M fifth masks, the third mask can be obtained by using the fifth mask corresponding to the later-added primitive to cover the fifth mask corresponding to the earlier-added primitive, based on the stacking order of the M primitives. When two fifth masks overlap, the two sets of masks corresponding to the same pixel overlap; when two sets of masks overlap, the masks corresponding to the same sampling point overlap. During the overlap, the later-added mask corresponding to the same sampling point covers the earlier-added mask, i.e., a copying method is used, writing the later-added mask to the corresponding storage location of the earlier-added mask. The mask presented after the overlap is the third mask. It should be noted that when masks corresponding to the same sampling point overlap, the overlap operation is only effective if at least one bit of the later-added mask is not 0, and it can completely cover the earlier-added mask. For example, if the later-added mask is 1011 and the earlier-added mask is 0111, the overlapped mask is 1011. If every bit of the mask superimposed later is 0, then the overlay operation of the mask later is invalid, and the superimposed mask still has the same effect as the mask superimposed earlier. For example, if the mask superimposed later is 0000 and the mask superimposed earlier is 0111, the mask superimposed later will be 0111.

[0114] Assume that primitive 2 is a primitive superimposed later, and primitive 1 is a primitive superimposed earlier. The fifth mask (G_2) corresponding to primitive 2 can be used to cover the fifth mask (G_1) corresponding to primitive 1. Among them, the first group of masks G_2, G_21, covers the first group of masks G_1, G_11 (corresponding to the first pixel). Referring to Figure 7, the first mask of mask G_21 (G_211=1101) covers the first mask of mask G_11 (G_111=1111) to obtain mask D311=1101. This mask D311 is used as the first mask of the first group of masks D31 of the third mask D3 (corresponding to the first sampling point). The second mask of mask G_21 (G_212=1101) overwrites the second mask of mask G_11 (G_112=0000), resulting in mask D312=1101. This mask D312 serves as the second mask of the first group of masks D31 in the third mask D3 (corresponding to the second sampling point). The third mask of mask G_21 (G_213=0000) overwrites the third mask of mask G_11 (G_113=1111). Since every bit of the subsequently superimposed mask G_21 is 0, mask G_21 is invalid. The superimposed mask is still consistent with the previously superimposed mask G_11, resulting in mask D313=1111. This mask D313 serves as the third mask of the first group of masks D31 in the third mask D3 (corresponding to the third sampling point). The fourth mask of mask G_21 (G_214=1101) covers the fourth mask of mask G_11 (G_114=1111) to obtain mask D314=1101. This mask D314 is used as the fourth mask of the first group of masks D31 of the third mask D3 (corresponding to the fourth sampling point).

[0115] In this case, the first group of masks D31 of the third mask D3 can be 1101 1101 1111 1101.

[0116] Similarly, by overlapping the M sets of masks corresponding to the same pixel in the M fifth masks, a set of masks corresponding to that pixel in the third mask can be obtained. The third mask can be obtained by combining the N sets of masks obtained through the overlapping. The overlapping method of each pair of masks corresponding to other pixels will not be described in detail here.

[0117] It can be seen that the third mask includes the same mask as the first mask. In the example above, this is represented as D311=D312=D314=G21 and D313=G11. In this way, the information of the first mask can be retained in the third mask, which makes it easier to obtain the fourth mask that is the same as the first mask by splitting the third mask later.

[0118] Those skilled in the art should understand that there can be many other ways to perform the hidden face removal test in step S63, as long as the third mask can include the information of the first mask and the third mask is a mask obtained by depth / template testing and hidden face removal testing. The specific method of the hidden face removal test in step S63 is not limited in the embodiments of this disclosure.

[0119] In one possible implementation, the rendering pipeline corresponds to a cache, which is used when performing hidden surface removal tests on M first masks. The third mask includes N sets of masks corresponding to N pixels respectively. Each set of masks includes K masks, and each mask includes K bits. N and K are integers greater than 1. The cache includes N storage locations. The j-th storage location stores the j-th set of masks of the third mask, where 0 < j ≤ N and is an integer.

[0120] For example, the rendering pipeline may correspond to a cache, such as a cache located in the second test module. The cache is used when performing hidden surface removal tests on M first masks, and specifically for implementing the overlay of the fifth mask. Figure 8 shows a schematic diagram of a cache according to an embodiment of this disclosure.

[0121] As shown in Figure 8, this cache can have N storage locations, each corresponding to one pixel. Each storage location can store a mask corresponding to one pixel. Each storage location can include K rows (or K columns). In the example of Figure 8, the storage location corresponding to each pixel can include 4 rows. Each row corresponds to one sampling point, that is, each row is used to store one mask from a set of masks corresponding to that sampling point. In the example of Figure 8, the first row can correspond to the first sampling point s0, the second row can correspond to the second sampling point s1, the third row can correspond to the third sampling point s2, and the fourth row can correspond to the fourth sampling point s3. Each row can store a 4-bit mask.

[0122] After the stacking order of the M primitives is determined, the N sets of masks included in the fifth mask corresponding to the first stacked primitive are sequentially written to the N storage locations in the cache. The N sets of masks included in the fifth mask corresponding to the second stacked primitive overwrite the existing masks in the N storage locations one by one. At this point, the fifth mask corresponding to the second stacked primitive is completely covered. This process continues until the fifth mask corresponding to the Mth stacked primitive is completely covered. The N sets of masks stored in the N storage locations are the third mask determined by the hidden surface removal test of the M fifth masks.

[0123] In this case, only K bits are needed to complete the hidden surface removal test in step S63 for each sampling point. The required cache is also relatively small, and the cost is still much smaller than that of two rendering pipelines. Therefore, the function of the hidden surface removal test can be guaranteed to be executed normally at a relatively low cost.

[0124] Since the mask overlay is performed using a copy method, the K masks stored in the storage location corresponding to a pixel may come from different primitives. Therefore, in order to obtain the M fourth masks corresponding to M primitives, the third mask can be split, separating the parts belonging to the same primitive.

[0125] The following describes an exemplary method for splitting the third mask in step S64.

[0126] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits; Step S64 includes: When the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer; When the i-th primitive does not correspond to any of the masks of the j-th set of the third mask, the mask of K second values ​​is used as the j-th mask of the i-th fourth mask.

[0127] The correspondence between the t-th mask of the j-th group of the third mask and the primitive can be determined according to existing technology, and will not be elaborated here.

[0128] For example, as shown in Figure 7, the effective mask corresponding to a sampling point in the fifth mask (i.e., the mask where K bits are not all 0, such as G_111) and the mask corresponding to the pixel to which the sampling point belongs in the first mask corresponding to the fifth mask (such as G11) are actually the same. The mask corresponding to the sampling point in the third mask is derived from the mask corresponding to the sampling point in the fifth mask. Therefore, if the i-th primitive corresponds to the t-th mask of the j-th group of masks in the third mask, it can be considered that the i-th primitive is the top primitive of the t-th sampling point of the j-th pixel. The corresponding mask of the t-th mask of the j-th group of masks in the fifth mask is an effective mask. Therefore, the t-th mask of the j-th group of masks in the third mask can be used as the j-th mask of the i-th fourth mask.

[0129] Taking Figure 7 as an example, the first group of masks D31 of the third mask D3 is 1101 1101 1111 1101, where the first, second, and fourth masks (1101) correspond to the second primitive (primitive 2), and the third mask (1111) corresponds to the first primitive (primitive 1). Therefore, 1101 can be used as the first mask of the second fourth mask (corresponding to primitive 2). 1111 can be used as the first mask of the first fourth mask (corresponding to primitive 1).

[0130] If the i-th primitive does not correspond to each mask of the j-th group of the third mask, it can be considered that the i-th primitive is not the top primitive of the t-th sampling point of the j-th pixel. The corresponding mask of the t-th mask of the j-th group of the third mask in the fifth mask is an invalid mask (all K bits are 0). Therefore, the mask of K second values ​​(e.g., 0000) can be used as the j-th mask of the i-th fourth mask.

[0131] In this way, a fourth mask that is the same as the first mask can be obtained. This method reduces the cost required by the graphics processor.

[0132] The following describes another exemplary method for splitting the third mask in step S64.

[0133] In one possible implementation, the rendering pipeline is used to render M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits; Step S64 includes: When the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the t-th mask of the j-th set of the i-th seventh mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; When the i-th primitive does not correspond to the t-th mask of the j-th set of the third mask, the mask of K second values ​​is used as the t-th mask of the j-th set of the i-th seventh mask; The OR operation result of the j-th set of the j-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0134] For example, another way to split the third mask is by using an OR operation. Using this method, the third mask is first split to obtain M seventh masks. Each seventh mask includes N groups of masks, each group of masks includes K masks, and each mask includes K bits. Each group of masks corresponds to one pixel, and each mask in each group of masks corresponds to one sampling point. Figure 9 shows a schematic diagram of the seventh mask according to an embodiment of this disclosure.

[0135] Assuming M=2, N=4, and K=4, the mask transmission method of this embodiment is applied to a scene where two primitives (primitive 1 and primitive 2) are rendered. The rendered image includes four pixels, and each pixel includes four sampling points. For clarity, Figure 9 only shows the coverage of the four sampling points of the first pixel by primitive 1 and primitive 2.

[0136] As shown in Figure 9, the first group of masks D31 of the third mask D3 corresponds to the first pixel, which can be 1101 1101 1111 1101, where the first, second and fourth masks (1101) correspond to the second primitive (primitive 2), and the third mask (1111) corresponds to the first primitive (primitive 1). Therefore, 1101 can be used as the first mask P211, the second mask P212, and the fourth mask P214 of the first group of masks P21 (corresponding to the first pixel) of the second seventh mask P2 (corresponding to primitive 2). The third mask P213 of the first group of masks P21 of the second seventh mask can be 0000. 1111 can be used as the third mask P113 of the first group of masks P11 (corresponding to the first pixel) of the first seventh mask P1 (corresponding to primitive 1). The first mask P111, the second mask P112, and the fourth mask P114 of the first group of masks of the first seventh mask can all be 0000.

[0137] In this case, the first group mask P11 of the first seventh mask can be 0000 0000 1111 0000, and the first group mask P21 of the second seventh mask can be 1101 1101 0000 1101.

[0138] Then, an OR operation is performed on the K masks in the j-th group of the i-th seventh mask, and the result of the OR operation is used as the j-th mask of the fourth mask corresponding to the i-th primitive. In the example of Figure 9, the OR operation result of the first mask P111=0000, the second mask P112=0000, the third mask P113=1111, and the fourth mask P114=0000 of the first group of the first seventh mask can be 1111. Therefore, 1111 can be used as the first mask Y11 of the fourth mask Y1 corresponding to primitive 1 (corresponding to the first pixel). The OR operation of the first mask P211=1101, the second mask P212=1101, the third mask P213=0000, and the fourth mask P214=1101 of the first group of the second seventh mask can result in 1101. Therefore, 1101 can be used as the first mask Y21 of the fourth mask Y2 corresponding to primitive 2 (corresponding to the first pixel).

[0139] In this way, the flexibility of the splitting method of the third mask can be improved.

[0140] Those skilled in the art should understand that there can be many other ways to split the third mask, as long as M fourth masks can be obtained from the third mask, and the M fourth masks are the same as the M first masks respectively. The embodiments of this disclosure do not limit the specific way of splitting the third mask.

[0141] FIG10 shows a schematic diagram of an exemplary flow of a mask transmission method according to an embodiment of the present disclosure.

[0142] As shown in Figure 10, in one possible implementation, the method further includes: Step S71, performing a hidden face removal test on the M second masks to determine the sixth mask corresponding to all M primitives; Step S72, splitting the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; Step S73, in response to the second instruction, inputting the M eighth masks into the pixel shader.

[0143] For example, referring to the application scenario in Figure 5b, the second test module can have two branches. The first branch can perform the functions described in steps S63-S65 above, outputting the fourth mask, which is the same as the first mask, to the pixel shader. The second branch can perform the functions described in steps S71-S73, outputting the mask (i.e., the eighth mask) after performing rasterization, depth stencil testing, and hidden face removal testing on the primitives according to the existing technology method. The workflow of the first branch can be referred to the relevant description in Figure 6, and will not be repeated here. The workflow of the second branch is described below.

[0144] For example, in step S71, the second branch of the second test module can perform hidden surface removal testing on the M second masks (masks S1-SM) in the manner of existing technology to determine the sixth mask D6 corresponding to all M primitives. When performing the hidden surface removal test in step S71, the second masks corresponding to multiple primitives can be directly covered layer by layer according to the coverage order of the primitives. The final coverage result of the M second masks is the sixth mask D6. Therefore, the sixth mask D6 corresponds to all M primitives. The sixth mask includes N masks corresponding to N pixels respectively, and each mask includes K bits. At this time, the sixth mask D6 can indicate which sampling points each primitive is the top primitive of (after the inter-primary coverage is completed, if the second mask corresponding to a sampling point covered by a primitive is still valid, the primitive is the top primitive of that sampling point).

[0145] For example, after the hidden face removal test in step 71, masks S1 and S2 (second masks) can be used to obtain mask D6 (sixth mask). Mask D6 corresponds to primitive 1 and primitive 2. Mask D6 may include masks D61-D64, where mask D61 corresponds to the first pixel. In the example of FIG7, mask D61 can be 1111, where the first, second, and fourth bits come from mask S2 and therefore correspond to primitive 2, and the third bit comes from mask S1 and therefore corresponds to primitive 1.

[0146] The second branch of the second test module then executes step S72 to split the sixth mask D6. The purpose of the split is to separate the parts of the sixth mask D6 related to each primitive. Under the premise of performing depth testing and / or stencil testing, as well as hidden face removal testing, M eighth masks (mask Y_1-mask Y_M) are obtained. Primitive 1 corresponds to mask Y_1, ..., primitive M corresponds to mask Y_M. The eighth mask can include N masks, each mask corresponds to one pixel, and each mask includes K bits. Taking the mask D61 corresponding to the first pixel in the split mask D6 in Figure 7 or Figure 9 as an example, after the mask D61 is split, we can obtain the first mask Y_11 in the eighth mask Y_1 corresponding to primitive 1 and the first mask Y_21 in the eighth mask Y_2 corresponding to primitive 2. Since the first, second and fourth bits of the mask D61 correspond to primitive 2 and the third bit corresponds to primitive 1, the mask Y_11 can be 0010 and the mask Y_21 can be 1101.

[0147] The method of obtaining the masks corresponding to other pixels by splitting the sixth mask is similar to that of obtaining the mask Y_11 by splitting, and will not be repeated here.

[0148] The first mask and the eighth mask corresponding to each primitive may be the same or different. If the second mask and the first mask corresponding to a primitive are the same, and the primitive is the top primitive covering all sampling points after the primitive has undergone depth / template testing, then the eighth mask and the first mask corresponding to the primitive are also the same; if the second mask and the first mask corresponding to a primitive are different, then the eighth mask and the first mask corresponding to the primitive are also different; if the second mask and the first mask corresponding to a primitive are the same, but the primitive is not the top primitive covering all sampling points after the primitive has undergone depth / template testing, then the eighth mask and the first mask corresponding to the primitive are different.

[0149] The user can provide a second instruction when the pixel shader processes data using the mask after performing a hidden face removal test according to existing technology. The second branch of the second test module then executes step S73, and in response to the second instruction, M eighth masks can be input into the pixel shader. At the same time, the starting address of the pixel can also be output to the pixel shader. The pixel shader processes data using the eighth masks and the starting address of the pixel, and outputs color data for N pixels. An image to be rendered to the screen can be generated based on this color data.

[0150] If it can be determined in advance that the pixel shader will use a mask after performing a hidden face removal test according to the prior art for data processing, the second instruction can also be pre-stored in a specific location, such as memory, and after the graphics processor's rendering pipeline is started, the processor reads the second instruction from memory and outputs it to the rendering pipeline. This disclosure does not limit the source of the second instruction.

[0151] In this case, the graphics processor can output both a mask consistent with the rasterized mask to the pixel shader and another mask consistent with the mask after the hidden face removal test in the prior art, while using one rendering pipeline and retaining the early depth / stencil test and hidden face removal test, so that the pixel shader has more choices of data to use when performing shading.

[0152] This disclosure also provides a mask transmission device. FIG11 shows a schematic diagram of the structure of the mask transmission device according to an embodiment of this disclosure.

[0153] As shown in Figure 11, the device is applied to the rendering pipeline of a graphics processor. The rendering pipeline includes a pixel shader. The device includes: a rasterization module 10, used to rasterize M primitives respectively, and determine M first masks corresponding to the M primitives respectively, where M is an integer greater than 1; a first test module 20, used to perform depth testing and / or stencil testing on the M first masks respectively, and determine M second masks corresponding to the M primitives respectively; a second test module 30, used to perform hidden face removal testing on the M first masks according to the M second masks, and determine a third mask corresponding to all M primitives; split the third mask to obtain M fourth masks corresponding to the M primitives respectively; and input the M fourth masks into the pixel shader in response to a first instruction.

[0154] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. Each first mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits; each second mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits; the third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits; each fourth mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits.

[0155] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The step of performing a hidden surface removal test on the M first masks according to the M second masks to determine the third mask corresponding to all M primitives includes: processing the M first masks according to the M second masks to obtain M fifth masks, each fifth mask including N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, each mask including K bits; performing a hidden surface removal test on the M fifth masks to determine the third mask.

[0156] In one possible implementation, the step of processing the M first masks according to the M second masks to obtain the M fifth masks includes: when the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of masks of the i-th fifth mask, 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, 0 < t ≤ K and are integers; when the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of K second values ​​is used as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0157] In one possible implementation, the step of performing a hidden surface removal test on the M fifth masks to determine the third mask includes: according to the stacking order of the M primitives, using the fifth mask corresponding to the later stacked primitive to cover the fifth mask corresponding to the earlier stacked primitive, thereby obtaining the third mask.

[0158] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N sets of masks corresponding to the N pixels respectively, each set of masks including K masks, and each mask including K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: when the i-th primitive corresponds to the t-th mask of the j-th set of the third mask, the t-th mask of the j-th set of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer; when the i-th primitive does not correspond to any of the masks of the j-th set of the third mask, the mask of K second values ​​is used as the j-th mask of the i-th fourth mask.

[0159] In one possible implementation, the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1. The third mask comprises N sets of masks corresponding to the N pixels, each set of masks comprising K masks, and each mask comprising K bits. The step of splitting the third mask to obtain M fourth masks corresponding to the M primitives includes: the t-th bit of the j-th set of the third mask corresponding to the i-th primitive. When using a mask, the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, where 0 < i ≤ M and are integers, 0 < j ≤ N and are integers, and 0 < t ≤ K and are integers; when the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask; the OR operation result of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

[0160] In one possible implementation, the second test module is further configured to: perform hidden face removal tests on the M second masks to determine a sixth mask that corresponds to all M primitives; split the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and input the M eighth masks into the pixel shader in response to a second instruction.

[0161] In one possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0162] In one possible implementation, the rendering pipeline corresponds to a cache, which is used when performing hidden surface removal tests on the M first masks. The third mask includes N sets of masks corresponding to N pixels respectively. Each set of masks includes K masks, and each mask includes K bits. N and K are integers greater than 1. The cache includes N storage locations. The j-th storage location stores the j-th set of masks of the third mask, where 0 < j ≤ N and is an integer.

[0163] In some embodiments, the functions of the apparatus provided in this disclosure or the modules included therein can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0164] This disclosure also provides a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the above-described method. The computer-readable storage medium may be volatile or non-volatile.

[0165] This disclosure also provides an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0166] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0167] FIG12 shows a block diagram of an apparatus 1900 according to an embodiment of the present disclosure. For example, apparatus 1900 may be provided as an electronic device. Referring to FIG12, apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions executable by processing component 1922, such as applications. The applications stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, processing component 1922 is configured to execute instructions to perform the methods described above.

[0168] The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 can operate on an operating system stored in memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0169] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by a processing component 1922 of the device 1900 to perform the above method.

[0170] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0171] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage medium as used herein is not to be construed as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0172] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to computer-readable storage media stored in the respective computing / processing device.

[0173] The computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable arrays (PLAs), is personalized by utilizing state information from computer-readable programmable instructions. This electronic circuitry can execute computer-readable programmable instructions to implement various aspects of this disclosure.

[0174] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0175] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, thereby comprising an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0176] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0177] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0178] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. [Simplified Explanation of the Diagram]

[0034] The accompanying drawings, which are included in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure. Figure 1 shows an example of a rasterized mask. Figure 2 shows another example of a rasterized mask. Figure 3 shows an example of a mask after an early depth / stencil test. Figure 4 shows an example of a mask after a hidden face removal test. Figure 5a shows an exemplary application scenario of a mask transmission method according to an embodiment of this disclosure. Figure 5b shows an exemplary application scenario of a mask transmission method according to an embodiment of this disclosure. Figure 6 shows a schematic flowchart of a mask transmission method according to an embodiment of this disclosure. Figure 7 shows an example of a mask determined in each step of a mask transmission method according to an embodiment of this disclosure and an example of indicated sampling point coverage. Figure 8 shows a schematic diagram of a cache according to an embodiment of this disclosure. Figure 9 shows a schematic diagram of a seventh mask according to an embodiment of this disclosure. Figure 10 shows a schematic flowchart of an exemplary mask transmission method according to an embodiment of this disclosure. Figure 11 shows a schematic diagram of the structure of a mask transmission apparatus according to an embodiment of this disclosure. Figure 12 shows a block diagram of an apparatus 1900 according to an embodiment of this disclosure.

Claims

1. A mask transmission method, characterized in that the method is applied to the rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, the method comprising: Rasterization is performed on each of the M primitives to determine the M first masks corresponding to each of the M primitives, where M is an integer greater than 1; Depth testing and / or stencil testing are performed on the M first masks to determine M second masks corresponding to the M primitives; based on the M second masks, hidden face removal testing is performed on the M first masks to determine third masks corresponding to all M primitives; the third masks are split to obtain M fourth masks corresponding to the M primitives, with the first and fourth masks corresponding to the same primitive being the same; in response to a first instruction, the M fourth masks are input into the pixel shader.

2. The method as described in claim 1, characterized in that the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1; each first mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits; each second mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits; the third mask comprises N sets of masks corresponding to the N pixels respectively, each set of masks comprising K masks, each mask comprising K bits; and each fourth mask comprises N masks corresponding to the N pixels respectively, each mask comprising K bits.

3. The method as described in claim 1, characterized in that the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1; and based on the M second masks, a hidden surface removal test is performed on the M first masks to determine a third mask corresponding to all M primitives, including: Based on the M second masks, the M first masks are processed to obtain M fifth masks. Each fifth mask includes N sets of masks corresponding to the N pixels. Each set of masks includes K masks, and each mask includes K bits. A hidden surface removal test is performed on the M fifth masks to determine the third mask.

4. The method as described in claim 3, characterized in that, based on the M second masks, the M first masks are processed to obtain M fifth masks, including: When the t-th bit of the j-th mask of the i-th second mask is equal to the first value, the j-th mask of the i-th first mask is used as the t-th mask of the j-th group of the i-th fifth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer; When the t-th bit of the j-th mask of the i-th second mask is equal to the second value, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th fifth mask.

5. The method as described in claim 3, characterized in that, the step of performing a hidden surface removal test on the M fifth masks to determine the third mask includes: Based on the stacking order of the M primitives, the fifth mask corresponding to the primitives stacked later is used to cover the fifth mask corresponding to the primitives stacked earlier, thus obtaining the third mask.

6. The method as described in claim 1, characterized in that the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1; the third mask comprises N sets of masks corresponding to the N pixels respectively, each set of masks comprising K masks, each mask comprising K bits; the step of splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively comprises: When the i-th primitive corresponds to the t-th mask of the j-th group of the third mask, the t-th mask of the j-th group of the third mask is used as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer. When the i-th primitive does not correspond to any of the masks in the j-th group of the third mask, the mask of the K second values ​​is used as the j-th mask of the i-th fourth mask.

7. The method as described in claim 1, characterized in that the rendering pipeline is used to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, where N and K are integers greater than 1; the third mask comprises N sets of masks corresponding to the N pixels respectively, each set of masks comprising K masks, each mask comprising K bits; the step of splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively comprises: When the i-th primitive corresponds to the t-th mask of the j-th group of the third mask, the t-th mask of the j-th group of the third mask is used as the t-th mask of the j-th group of the i-th seventh mask, where 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer. When the i-th primitive does not correspond to the t-th mask of the j-th group of the third mask, the mask of the K second values ​​is used as the t-th mask of the j-th group of the i-th seventh mask; the OR operation result of the j-th group of the i-th seventh mask is used as the j-th mask of the i-th fourth mask.

8. The method as described in claim 1, characterized in that the method further comprises: Perform a hidden surface removal test on the M second masks to determine the sixth mask that corresponds to all M primitives; The sixth mask is split to obtain M eighth masks corresponding to the M primitives respectively; in response to the second instruction, the M eighth masks are input into the pixel shader.

9. The method as described in claim 1, wherein the rendering pipeline supports tile-based deferred rendering.

10. The method as described in claim 9, characterized in that the rendering pipeline corresponds to a cache, the cache is used when performing hidden surface removal tests on the M first masks, the third mask includes N sets of masks corresponding to N pixels respectively, each set of masks includes K masks, each mask includes K bits, N and K are integers greater than 1; the cache includes N storage locations, the j-th storage location stores the j-th set of masks of the third mask, 0 < j ≤ N and is an integer.

11. A mask transmission device, characterized in that the device is applied to the rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, the device comprising: A rasterization module is used to rasterize M primitives respectively, and determine M first masks corresponding to the M primitives, where M is an integer greater than 1; a first test module is used to perform depth testing and / or stencil testing on the M first masks respectively, and determine M second masks corresponding to the M primitives; a second test module is used to perform hidden face removal testing on the M first masks based on the M second masks, and determine a third mask corresponding to all M primitives; the third mask is split to obtain M fourth masks corresponding to the M primitives; and in response to a first instruction, the M fourth masks are input into the pixel shader.

12. An electronic device, characterized in that it comprises: processor; Memory for storing processor-executable instructions; wherein the processor is configured to implement the method described in any one of requests 1 to 10 when executing the instructions stored in the memory.

13. A non-volatile computer-readable storage medium having stored thereon computer program instructions, characterized in that, when the computer program instructions are executed by a processor, they implement the method described in any one of requests 1 to 10.

14. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, characterized in that, when the computer-readable code is executed in a processor of an electronic device, the processor in the electronic device performs the method described in any one of requests 1 to 10.

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