3-transistor footprint stacked SRAM

Abstract

The embodiments disclosed herein pertain to a processing method and resulting structure for providing a 3T footprint stacked SRAM. In a non-limiting embodiment, an SRAM bit cell includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first pull-up transistor (PU) vertically stacked above a first pull-down transistor (PD). The SRAM bit cell includes a second inverter positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU vertically stacked above a second PD. A first channel gate (PG) is positioned at a first acute angle of the parallelogram, and a second PG is positioned at a second acute angle of the parallelogram.

Description

Technical Field

[0001] This disclosure is generally about semiconductor technology, and more specifically about a semiconductor structure comprising a stacked field-effect transistor (FET) with a three-transistor (3T) footprint having a static random access memory (SRAM) design. Prior Technology

[0002] SRAM is a type of random access memory (RAM) that uses a latching circuit system (flip-flops) to store bits. A typical SRAM cell consists of six FETs. The bits in a conventional SRAM are stored on four of the transistors that form two cross-coupled inverters. This memory cell has two stable states, 0 and 1. Two additional access transistors are used to control access to the memory cell during read and write operations. Besides this six-transistor (6T) SRAM architecture, other types of SRAM chips use four, eight, ten (4T, 8T, 10T SRAM) or more transistors per bit.

[0003] Monolithic and sequential stacking of transistors presents an attractive architecture for future scaling of complementary metal-oxide-semiconductor (CMOS) and latently for ultimate scaling technologies. Significant area scaling can be achieved by directly stacking one type of FET (e.g., n-type FET) on top of another type (e.g., p-type FET). For example, in a stacked SRAM architecture, pull-up (PU) transistors can be stacked vertically on top of pull-down (PD) transistors of a cross-coupled inverter pair, or vice versa. This vertical configuration allows for a smaller footprint (4T) in stacked SRAM cells compared to a conventional 6T SRAM cell, which actually requires an eight-transistor footprint due to the presence of two half-dummy PFET regions at the channel gate (PG) (i.e., a footprint that can include two transistors but only one transistor). Summary of the Invention

[0004] The embodiments disclosed herein pertain to a method for forming a static random access memory (SRAM) bit cell. One non-limiting example of the method includes forming a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first pull-up transistor (PU) vertically stacked above a first pull-down transistor (PD). The method includes forming a second inverter positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU vertically stacked above a second PD. The method includes forming a first channel gate (PG) positioned at a first acute angle of the parallelogram and forming a second PG positioned at a second acute angle of the parallelogram.

[0005] The embodiments disclosed herein pertain to a 3T (3-T) footprint stacked SRAM bit cell. One non-limiting example of this bit cell includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first PU vertically stacked above a first PD. The SRAM bit cell includes a second inverter positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU vertically stacked above a second PD. A first PG is positioned at a first acute angle of the parallelogram, and a second PG is positioned at a second acute angle of the parallelogram.

[0006] The embodiments disclosed herein pertain to a method for forming a semiconductor device. One non-limiting example of the method includes forming a first SRAM bit cell having a first bit cell type. The first bit cell type includes a first pair of channel gates (PGs) located in the top layer of the first SRAM bit cell. The method includes forming a second SRAM bit cell having a second bit cell type. The second bit cell type includes a second pair of PGs located in the bottom layer of the second SRAM bit cell. The first SRAM bit cell and the second SRAM bit cell are adjacent bit cells. The channel gates of the first SRAM bit cell and the second SRAM bit cell are vertically stacked in the same channel gate region, such that the first SRAM bit cell and the second SRAM bit cell partially overlap in a 3T footprint.

[0007] The embodiments disclosed herein are directed to a semiconductor device. One non-limiting example of the semiconductor device includes a first SRAM bit cell having a first bit cell type. The first bit cell type includes a first pair of channel gates (PGs) located in the top layer of the first SRAM bit cell. The semiconductor device includes a second SRAM bit cell having a second bit cell type. The second bit cell type includes a second pair of PGs located in the bottom layer of the second SRAM bit cell. The first SRAM bit cell and the second SRAM bit cell are adjacent bit cells. The channel gates of the first SRAM bit cell and the second SRAM bit cell are vertically stacked in the same channel gate region, such that the first SRAM bit cell and the second SRAM bit cell partially overlap in a 3T footprint.

[0008] The embodiments disclosed herein pertain to a 3T footprint stacked SRAM bit cell. One non-limiting example of this bit cell includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first PD vertically stacked above a first PU. The SRAM bit cell includes a second inverter positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PD vertically stacked above a second PU. A first PG is positioned at a first acute angle of the parallelogram, and a second PG is positioned at a second acute angle of the parallelogram.

[0009] Additional technical features and benefits are achieved through the techniques disclosed herein. Embodiments and styles of this disclosure are described in detail herein and are considered part of the claimed subject matter. For a better understanding, refer to the embodiments and drawings. Simple Explanation of the Diagram

[0010] The details of the proprietary rights described herein are specifically pointed out and clearly claimed in the claims at the end of this specification. The foregoing and other features and advantages of the disclosed embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a top view of a parallelogram stacked SRAM bit cell design according to one or more embodiments;

[0012] Figure 2 is a top view of a circuit design layout for a parallelogram stacked SRAM bit cell design according to one or more embodiments;

[0013] Figure 3 is an alternative top view of the circuit design layout of Figure 2 according to one or more embodiments;

[0014] Figure 4 is an alternative top view of the circuit design layout of Figure 2 according to one or more embodiments;

[0015] Figure 5 is an alternative top view of the circuit design layout of Figure 2 according to one or more embodiments;

[0016] Figure 6 shows the circuit design layout of Figure 2 according to one or more embodiments along the line. [, A-A Cross-sectional view of , ];

[0017] Figure 7 shows the circuit design layout of Figure 2 according to one or more embodiments along the line. [, A-A Alternative cross-sectional view of , ];

[0018] Figure 8 depicts a flowchart illustrating a method according to one or more embodiments; and

[0019] Figure 9 depicts a flowchart illustrating a method according to one or more embodiments.

[0020] The diagrams described herein are illustrative. Many variations may exist in the diagrams or operations described without departing from the spirit of this disclosure. For example, actions may be performed in different orders, or actions may be added, deleted, or modified.

[0021] In the following detailed description of the embodiments described in the accompanying drawings and this disclosure, the various elements illustrated in the figures have two or three digit element symbols. With a few exceptions, one or more of the leftmost digits of each element symbol correspond to the diagram in which the element is first drawn. Implementation

[0022] According to one aspect of this disclosure, a method for providing static random access memory (SRAM) bit cells is provided. A non-limiting example of the method includes forming a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first pull-up transistor (PU) vertically stacked above a first pull-down transistor (PD). The method includes forming a second inverter positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU vertically stacked above a second PD. The method includes forming a first channel gate (PG) positioned at a first acute angle of the parallelogram and forming a second PG positioned at a second acute angle of the parallelogram. Advantageously, forming SRAM bit cells in this manner allows overlap with adjacent bit cells, thereby providing a aggregated 3T footprint.

[0023] In some embodiments, the method includes forming a supply voltage (VDD) line located on the front side of the SRAM bit cell and forming a source supply voltage (VSS) line located on the back side of the SRAM bit cell. This serves as a physical feature of the manufacturing method described herein.

[0024] In some embodiments, the first PU and the second PU are located at the top level of the SRAM bit cell, and the first PD and the second PD are located at the bottom level below the top level. This allows a pair of SRAM bit cells to partially overlap within the aggregated 3T footprint (at the shared PG region).

[0025] In some embodiments, the method includes forming a word line (WL) and forming a bit line (BL). In some embodiments, a first PG and a second PG are located on a top level, and the WL and BL are positioned on the front side of the SRAM bit cell. In some embodiments, the first PG and the second PG are located on a bottom level, and the WL and BL are positioned on the back side of the SRAM bit cell. In these configurations, the bit cell is compatible with PGs of different polarities.

[0026] The embodiments disclosed herein pertain to a 3T (3-T) footprint stacked SRAM bit cell. A non-limiting example of the bit cell includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first PU stacked vertically above a first PD. The SRAM bit cell includes a second inverter positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU stacked vertically above a second PD. A first PG is positioned at a first acute angle of the parallelogram, and a second PG is positioned at a second acute angle of the parallelogram.

[0027] In some embodiments, the supply voltage (VDD) line is located on the front side of the SRAM bit cell, and the source supply voltage (VSS) line is located on the back side of the SRAM bit cell. The VDD and VSS lines can be used to change the state of the SRAM bit cell (e.g., from 0 to 1).

[0028] In some embodiments, the first PU and the second PU are located on the top level of the SRAM bit cell, and the first PD and the second PD are located on the bottom level below the top level. This allows the SRAM bit cell to partially overlap with other bit cells (at the PG region).

[0029] In some embodiments, the SRAM bit cell includes WL and BL. In some embodiments, the first PG and the second PG are located on the top layer, and WL and BL are positioned on the front side of the SRAM bit cell. In some embodiments, the first PG and the second PG are located on the bottom layer, and WL and BL are positioned on the back side of the SRAM bit cell. In these configurations, the bit cell is compatible with PGs of different polarities.

[0030] The embodiments disclosed herein pertain to a method for forming a semiconductor device. A non-limiting example of the method includes forming a first SRAM bit cell having a first bit cell type. The first bit cell type includes a first pair of channel gates (PGs) located in the top layer of the first SRAM bit cell. The method includes forming a second SRAM bit cell having a second bit cell type. The second bit cell type includes a second pair of PGs located in the bottom layer of the second SRAM bit cell. The first SRAM bit cell and the second SRAM bit cell are adjacent bit cells. The channel gates of the first SRAM bit cell and the channel gates of the second SRAM bit cell are vertically stacked in the same channel gate region, such that the first SRAM bit cell and the second SRAM bit cell partially overlap in a 3T footprint.

[0031] In some embodiments, each of the first and second SRAM bit cells includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first PU stacked vertically above the first PD. A second inverter is positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU stacked vertically above the second PD. A first PG is positioned at a first acute angle of the parallelogram, and a second PG is positioned at a second acute angle of the parallelogram. This configuration allows the first and second PGs to partially overlap with PGs from adjacent bit cells.

[0032] In some embodiments, a first pair of PGs located in the top layer of a first SRAM bit cell has a first polarity, and a second pair of PGs located in the bottom layer of a second SRAM bit cell has a second polarity opposite to the first polarity. This configuration implements a split polarity architecture.

[0033] In some embodiments, a first SRAM bit cell includes a first WL and a first BL located on the front side of the first SRAM bit cell, and a second SRAM bit cell includes a second WL and a second BL located on the back side of the second SRAM bit cell. In these configurations, the bit cell is compatible with PGs having different polarities.

[0034] In some embodiments, the first pair of PGs located in the top layer of the first SRAM bit cell and the second pair of PGs located in the bottom layer of the second SRAM bit cell have the same polarity. In some embodiments, the WL is located on the front side of the semiconductor device, the first BL is located on the front side of the semiconductor device, and the second BL is located on the back side of the semiconductor device. This configuration is compatible with unipolar architectures.

[0035] The embodiments disclosed herein are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a first SRAM bit cell having a first bit cell type. The first bit cell type includes a first pair of channel gates (PGs) located in the top layer of the first SRAM bit cell. The semiconductor device includes a second SRAM bit cell having a second bit cell type. The second bit cell type includes a second pair of PGs located in the bottom layer of the second SRAM bit cell. The first SRAM bit cell and the second SRAM bit cell are adjacent bit cells. The channel gates of the first SRAM bit cell and the channel gates of the second SRAM bit cell are vertically stacked in the same channel gate region, such that the first SRAM bit cell and the second SRAM bit cell partially overlap in a 3T footprint.

[0036] In some embodiments, each of the first and second SRAM bit cells includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first PU stacked vertically above the first PD. A second inverter is positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU stacked vertically above the second PD. A first PG is positioned at a first acute angle of the parallelogram, and a second PG is positioned at a second acute angle of the parallelogram. This configuration allows the first and second PGs to partially overlap with PGs from adjacent bit cells.

[0037] In some embodiments, a first pair of PGs located in the top layer of a first SRAM bit cell has a first polarity, and a second pair of PGs located in the bottom layer of a second SRAM bit cell has a second polarity opposite to the first polarity. This configuration implements a split polarity architecture.

[0038] In some embodiments, a first SRAM bit cell includes a first WL and a first BL located on the front side of the first SRAM bit cell, and a second SRAM bit cell includes a second WL and a second BL located on the back side of the second SRAM bit cell. In these configurations, the bit cell is compatible with PGs having different polarities.

[0039] In some embodiments, the first pair of PGs located in the top layer of the first SRAM bit cell and the second pair of PGs located in the bottom layer of the second SRAM bit cell have the same polarity. In some embodiments, the WL is located on the front side of the semiconductor device, the first BL is located on the front side of the semiconductor device, and the second BL is located on the back side of the semiconductor device. This configuration is compatible with unipolar architectures.

[0040] The disclosed embodiment pertains to a 3T footprint stacked SRAM bit cell. A non-limiting example of the bit cell includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first PD vertically stacked above a first PU. The SRAM bit cell includes a second inverter positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PD vertically stacked above a second PU. A first PG is positioned at a first acute angle of the parallelogram, and a second PG is positioned at a second acute angle of the parallelogram.

[0041] In some embodiments, the VDD line is positioned on the front side of the SRAM bit cell, and the VSS line is positioned on the back side of the SRAM bit cell. The VDD and VSS lines can be used to change the state of the SRAM bit cell (e.g., from 0 to 1).

[0042] In some embodiments, the first PD and the second PD are located on the top level of the SRAM bit cell, and the first PU and the second PU are located on the bottom level below the top level. This allows the SRAM bit cell to partially overlap with other bit cells (at the PG region).

[0043] In some embodiments, the SRAM bit cell includes WL and BL. In some embodiments, the first PG and the second PG are located on the top layer, and WL and BL are positioned on the front side of the SRAM bit cell. In some embodiments, the first PG and the second PG are located on the bottom layer, and WL and BL are positioned on the back side of the SRAM bit cell. In these configurations, the bit cell is compatible with PGs of different polarities.

[0044] It should be understood in advance that although the exemplary embodiments of this disclosure are described in conjunction with specific transistor architectures, the embodiments of this disclosure are not limited to the specific transistor architectures or materials described in this specification. In fact, the embodiments of this disclosure can be implemented in conjunction with any other type of transistor architecture or material now known or to be developed later.

[0045] For the sake of brevity, known techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and procedural steps described herein may be incorporated into more comprehensive processes or procedures with additional steps or functionalities not described in detail herein. Specifically, the various steps involved in manufacturing semiconductor devices and semiconductor-based ICs are well-known, and therefore, for the sake of brevity, many known steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0046] Turning now to a more specific overview of the technologies relevant to the present disclosure, ICs are manufactured in a series of stages, including the front-end process (FEOL), mid-end process (MOL), and back-end process (BEOL). The process flow used to manufacture modern ICs is often identified based on whether the process flow belongs to the FEOL, MOL, or BEOL stage. Generally, the FEOL stage is the stage where device components (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate / wafer. FEOL stage processes include wafer fabrication, isolation, gate patterning, and the formation of wells, source / drain (S / D) regions, extended junctions, silicate regions, and pads. The MOL stage typically includes process flows for forming contacts (e.g., CAs) and other structures that are communicatively coupled to the active regions (e.g., gates, sources, and drains) of the device components. For example, siliconization of the source / drain regions and deposition of metal contacts can occur during the MOL stage to connect the components patterned during the FEOL stage. During the BEOL stage, interconnect layers (e.g., metallization layers) are formed over these logic and functional layers to complete the IC. Most ICs require more than one wire layer to form all the necessary connections, and up to 5 to 12 layers are added during the BEOL process. The various BEOL layers are interconnected by vias that couple from one layer to another. Layers throughout the IC use insulating dielectric materials to perform multiple functions, including stabilizing the IC structure and providing electrical isolation for IC components. For example, metal interconnect wires in the BEOL region of the IC are isolated by dielectric layers to prevent short circuits between the wires and other metal layers.

[0047] Static Random Access Memory (SRAM) area scaling has been a significant challenge using non-stacked transistor technology. As previously discussed, a typical 6-transistor SRAM has a footprint of approximately 8 transistors (8T), including two pull-up transistors (2 PUs), two pull-down transistors (2 PDs), two channel gate transistors (2 PGs), and two semi-dummy PFET regions electrically isolated above the PGs via gate-cut. Stacking transistors in a so-called stacked SRAM architecture can provide a smaller footprint than a conventional 6T SRAM cell with an 8T footprint. This can be achieved, for example, by moving the PU transistors on top of the PD transistors in a two-layer configuration. The result is a footprint reduction to 4 transistors, often referred to as "4T" stacked SRAM. In other words, current stacked SRAM architectures offer approximately a 50% footprint reduction (e.g., from 8T to 4T).

[0048] In the current dual-layer 4T stacked SRAM layout, SRAM bit cells (each comprising 4T stacked SRAM) are positioned end-to-end in one or more rows, and the PG transistors of each bit cell are positioned along the bottom layer. The space above the two PG transistors of each bit cell (i.e., the semi-dummy PFET region) is used for MOL (Modular Oscillator), since those regions were originally unused. Further improvements to region scaling have been limited.

[0049] This disclosure describes a 3T footprint stacked SRAM architecture and its fabrication method. A parallelogram stacked SRAM bit cell design is proposed to reuse semi-dummy PFET regions, allowing these regions to include another transistor, rather than using the semi-dummy PFET region above the PG for a less critical MOL. In some embodiments, the PG of each bit cell is positioned near the acute angle of the parallelogram, and the inverter (vertically integrated PU / PD) is placed on the obtuse angle. Advantageously, in this configuration, adjacent bit cells in a row utilize the same PG region. Specifically, a bit cell uses a PG FET in the bottom layer, and one or more adjacent bit cells use PG FETs in the top layer. In other words, this disclosure provides an SRAM architecture that utilizes wasted PG space to achieve an efficient 3T footprint bit cell design. As used herein, "efficient 3T footprint" refers to the fact that although individual bit cells still include a 4T footprint, the PG region is shared by adjacent bit cells, thus providing an efficient 3T footprint overall. To reiterate, "effective 3T footprint" refers to the 4T footprint of the overlapping PG regions between adjacent bit cells.

[0050] Turning now to a more detailed description of the manufacturing operations and resulting structures according to the present disclosure, Figure 1 depicts a top view of a parallelogram-stacked SRAM bit cell design 100 according to one or more embodiments of the present disclosure. The parallelogram-stacked SRAM bit cell design 100 includes a set of transistor channels 102, configured and arranged as shown. Transistor channels 102 represent the locations of the intersections between the gate and active regions in the parallelogram-stacked SRAM bit cell design 100.

[0051] In some embodiments, the transistor channels 102 are arranged in an array pattern including a first group 104 and a second group 106. In some embodiments, the first group 104 includes two rows of transistor channels 102, and the second group 106 includes two rows of transistor channels 102 offset from the rows of the first group 104. In some embodiments, adjacent transistor channels 102 are spaced by the same distance between them. [, P Separation, ] Although not intended to be subject to specific restrictions, the spacing [, P The range can be approximately 10 nanometers to 100 nanometers or larger, for example, 20 nanometers to 60 nanometers. In some embodiments, the second row group 106 is offset from the first row group 104 by an offset distance. [, O In some embodiments, offset distance [, O , ] represents the spacing [, P Half of , ] (as shown), but other spacing and offset configurations are within the scope of this disclosure.

[0052] In some embodiments, the parallelogram-stacked SRAM bit cell design 100 includes a first bit cell type 108 and a second bit cell type 110. In some embodiments, the first bit cell type 108 and the second bit cell type 110 are SRAM bit cells, each having two PMOS PUs and two NMOS PDs (vertically stacked to define one of the previously described pairs of inverters "INV") and two PGs. In some embodiments, the first bit cell type 108 and the second bit cell type 110 alternate within the parallelogram-stacked SRAM bit cell design 100. Although shown as having four bit cells (two first bit cell types 108 and two second bit cell types 110), this is only for convenience and ease of illustration. It should be understood that the parallelogram-stacked SRAM bit cell design 100 may include any number of transistor channels 102 configured along any number of rows (where each row is offset relative to adjacent rows), and all such configurations are within the scope of this disclosure.

[0053] In some embodiments, adjacent pairs of the first bit cell type 108 and the second bit cell type 110 partially overlap. In some embodiments, this overlap occurs when each individual bit cell includes a channel gate. In other words, the overlap occurs when the transistor channel 102 represents a channel gate PG. In some embodiments, both the top FET and the bottom FET in the transistor channel 102 at the intersection of the first bit cell type 108 and the second bit cell type 110 are channel gates. In some embodiments, the first bit cell type 108 uses one of these channel gates (e.g., the top PG), and the second bit cell type 110 uses the other channel gate (e.g., the bottom PG). This configuration differs from previous stacked SRAM bit cells, which typically include a single PG in each transistor channel (where the remaining slot, typically at the top, is for MOL elements). In some embodiments, the first bit cell type 108 uses the top FET as a channel gate, while the second bit cell type 110 uses the bottom FET as a channel gate, but this is merely a matter of convention. Advantageously, this design produces an efficient 3T footprint, where each bit cell includes two non-shared inverters (each a vertical PU / PD stack), a PG shared with the upper bit cell, and a PG shared with the lower bit cell (as shown). The shared PG element is effectively 0.5T, resulting in a converged 3T bit cell layout. This represents a 62.5% footprint reduction compared to a planar 8T SRAM layout and a 25% footprint reduction compared to the previous stacked 4T SRAM layout.

[0054] Figure 2 depicts a top view of a circuit design layout 200 for a parallelogram-stacked SRAM bit cell design (e.g., the parallelogram-stacked SRAM bit cell design 100 of Figure 1) according to one or more embodiments of this disclosure. Specifically, Figure 2 illustrates a circuit design layout 200 above the front-side MOL elements of the SRAM architecture. As shown in Figure 2, the circuit design layout 200 includes multiple SRAM bit cells, specifically, alternating between first bit cell type 108 and second bit cell type 110 (see Figure 1). Each bit cell includes a first inverter INV1, a second inverter INV2, a first channel gate PG1, and a second channel gate PG2. It should be noted that the circuit design layout 200 shown in Figure 2 is used for an inverter stack and a PG stack (see below) both positioned such that pFETs are on the top layer and nFETs are on the bottom layer. Alternatively, the circuit layout 200 can be configured such that the pFET is on the bottom layer and the nFET is on the top layer, but for clarity, this separate configuration is omitted. Both configurations are within the scope of this disclosure.

[0055] The circuit design layout 200 (SRAM cell) is implemented using a cross-coupled inverter pair comprising a first inverter INV1 and a second inverter INV2. In some embodiments, each inverter INV1, INV2 is connected to the output of the other inverter. Therefore, the cross-coupled inverter pair INV1, INV2 forms a bistable latch (with two stable states) capable of storing a single data bit and acting as a storage element in each SRAM cell. The two stable states of the cross-coupled inverter pair represent two binary values ​​(0 and 1) that can be stored in each SRAM cell. When one inverter output is high (logic 1), the other inverter output is low (logic 0), and vice versa. Therefore, the two outputs of the cross-coupled inverters can be referred to as storage nodes.

[0056] The first inverter INV1 and the second inverter INV2 each include a PMOS "PU" transistor and an NMOS "PD" transistor, wherein their gates are connected to the output of the other inverter via a pair of cross-coupled contacts "XC". In some embodiments, the PU transistor may be stacked vertically on top of the PD transistor, or vice versa. The term "pull-up transistor" in SRAM cells refers to a PMOS (P-channel MOSFET) transistor, which is responsible for pulling the storage node up to a logic high level (VDD or supply voltage) when the cell stores logic "1". In some embodiments, the source terminal of the PU transistor is connected to the supply voltage (VDD), and the drain terminal is connected to one of the individual storage nodes (another storage node besides the one connected to the PD transistor). When the storage node needs to be charged to represent logic "1", the PU transistor can be turned on by applying an appropriate gate voltage to the individual channel gate (PG1 or PG2). This allows current to flow from the VDD supply through the PU transistor, thereby effectively "pulling up" the voltage level of the storage node to VDD. Conversely, the term "pull-down transistor" in SRAM cells refers to an NMOS (N-channel MOSFET) transistor, which is responsible for pulling the storage node down to a low logic level (VSS or source supply voltage, also known as GND or ground) when the cell stores logic "0". In some embodiments, the source terminal of the PD transistor is connected to ground (or more specifically, local ground VSS), and the drain terminal is connected to one of the individual storage nodes (another storage node besides the one connected to the PU transistor). When the storage node needs to discharge to represent logic "0", the PD transistor can be turned on by applying an appropriate gate voltage to the individual channel gate (PG2 or PG1). This allows current to flow from the storage node through the PD transistor to VSS, thereby effectively "pulling down" the voltage level of the storage node to GND.

[0057] The first channel gate PG1 and the second channel gate PG2 are access transistors that control access to the storage nodes via a pair of complementary bit lines (BL and BLC). In some embodiments, one of PG1 and PG2 is connected to the storage nodes of each cross-coupled inverter pair. The gates of access transistors PG1 and PG2 are connected to the word line (WL) signal. During a read or write operation, PG1 and PG2 are controlled by the WL to allow access to the storage nodes of the inverter pair via bit lines BL and BLC (also referred to as complementary BL (BL bars)). Specifically, during a read operation, the differential voltage between the two storage nodes is transmitted to the bit lines via the access transistors, allowing a downstream sense amplifier (not shown separately) to detect the stored data. During a write operation, the desired data value is driven to the bit lines and the cross-coupled inverter pair is forced into the corresponding state (0 or 1) by access transistors PG1 and PG2, thereby updating the voltage level of the storage node.

[0058] To complete the SRAM circuit system, the circuit design layout 200 further includes a plurality of active regions 202 (source / drain regions) arranged in parallel columns and a plurality of gates 204 arranged in parallel rows, as shown in the configuration and arrangement. A plurality of single diffusion breaks (SDBs) 206 are located at the intersection between the active regions 202 and the gates 204. A plurality of front contacts 208, 210 ensure electrical continuity between the FEOL devices (e.g., INV1, INV2, PG1, PG2, WL) and the front MOL elements (e.g., BL, BLC and the front contacts 208, 210 themselves).

[0059] Figure 3 depicts an alternative top view of the circuit design layout 200 of Figure 2 according to one or more embodiments of this disclosure. Specifically, Figure 3 illustrates the circuit design layout 200 above the front-side MOL elements and front-side BEOL elements of the SRAM architecture. As shown in Figure 3, the circuit design layout 200 further includes a plurality of front-side BEOL elements 302, commonly referred to as front-side interconnects and / or a first front-side metallization layer (or front V0 / M1, which individually refer to the first via and the first metallization layer of the interconnects on the front side of the circuit design layout 200, respectively).

[0060] Figure 4 depicts an alternative top view of the circuit design layout 200 of Figure 2 according to one or more embodiments of this disclosure. Specifically, Figure 4 illustrates the circuit design layout 200 above the back-side MOL elements of an SRAM architecture. As shown in Figure 4, the circuit design layout 200 further includes a plurality of back-side contacts 402, 404 to ensure electrical continuity between the FEOL devices (e.g., INV1, INV2, PG1, PG2, WL) and the back-side MOL elements (e.g., BL, BLC and the back-side contacts 402, 404 themselves).

[0061] Figure 5 depicts an alternative top view of the circuit design layout 200 of Figure 2 according to one or more embodiments of this disclosure. Specifically, Figure 5 illustrates the circuit design layout 200 above the back-side MOL elements and back-side BEOL elements of an SRAM architecture. As shown in Figure 5, the circuit design layout 200 further includes a plurality of back-side BEOL elements 502, commonly referred to as back-side interconnects and / or a first back-side metallization layer (or back V0 / M1, which individually refer to the first via and the first metallization layer of the interconnects on the back side of the circuit design layout 200, respectively).

[0062] The circuit layout 200 of the parallelogram stacked SRAM bit cell design 100 provides several observable features (entity signatures). First, the first bit cell type 108 and the second bit cell type 110 are configured as alternating parallelograms, wherein the positions of the obtuse angles (corners) and acute angles (corners) in the first bit cell type 108 are opposite to the positions of the respective obtuse angles and acute angles in the second bit cell type 110 (i.e., the alternating parallelograms are mirror images). Channel gates PG1 and PG2 are positioned closest to the acute angles, and inverters INV1 and INV2 are positioned closest to the obtuse angles. Furthermore, adjacent bit cells in a row of the circuit layout 200 utilize the same PG region, as previously discussed. In short, one of the bit cells uses a PG FET at the bottom, and the other uses a PG FET at the top.

[0063] As observed in Figures 2 through 5, in circuit design layout 200, VDD and VSS are located on different sides of FETs INV1, INV2, PG1, and PG2 (e.g., comparing the VDD placement in Figure 3 with the VSS placement in Figure 5). In some embodiments, the bit cells of the bottom PG are constructed such that each WL and BL / BLC extends on the back side of the FET. Conversely, the bit cells of the top PG are constructed such that each WL and BL / BLC extends on the front side of the FET (e.g., comparing the front side shown in Figures 2 and 3 with the back side shown in Figures 4 and 5). In this configuration, the top PG (one of PG1 and PG2) and the bottom PG (one of PG2 and PG1) have different polarities (as shown). In some embodiments, the top PG and the bottom PG have the same polarity. In this configuration, WL extends on one side of the device, while BL / BLC extends on both sides (not shown separately).

[0064] Figure 6 depicts the circuit design layout of Figure 2 according to one or more embodiments of this disclosure along the line. [, A-A Cross-sectional view 600 of [ ]. As shown in Figure 6, the first bit cell type 108 and the second bit cell type 110 of the parallelogram stacked SRAM bit cell design 100 (and circuit design layout 200) partially overlap. Specifically, the first bit cell type 108 and the second bit cell type 110 share a common PG area 602.

[0065] As can be easily seen from the cross-sectional view provided in Figure 6, the total footprint of the first bit cell type 108 and the second bit cell type 110 is reduced due to the overlapping PG region 602. In fact, the first bit cell type 108 and the second bit cell type 110 each only require half of the shared PG region 602. Although not individually indicated, the same configuration is possible for upstream / downstream bit cells. The overall result is that each bit cell in the circuit design layout 200 (alternating between the first bit cell type 108 and the second bit cell type 110) requires only 3T of footprint, with INV1 requiring 1T, INV2 requiring 1T, and each of their two shared PG regions 602 requiring 0.5T (2 × 0.5T).

[0066] As further shown in Figure 6, in some embodiments, the circuit design layout 200 includes one or more sidewall strips 604 positioned between the individual components (i.e., inverters) in the PU / PD pair. The sidewall strips 604 may be made of a conductive material to short the NMOS drain of the individual PD to the PMOS drain of the individual PU.

[0067] Figure 7 depicts the circuit design layout of Figure 2 according to one or more embodiments of this disclosure 200 along the line. [, A-A The alternative cross-sectional view 700 is shown in Figure 7. As illustrated in Figure 7, the first cell type 108 and the second cell type 110 of the parallelogram stacked SRAM cell design 100 (and circuit layout 200) partially overlap in a manner similar to that discussed in Figure 6. However, in view 700, the shared PG area 602 is not perfectly aligned. In other words, there is a degree of misalignment between PG1 of the first cell type 108 and PG1 of the second cell type 110.

[0068] In other words, Figure 7 illustrates an embodiment in which the top FET and bottom FET, which serve as the top PG and bottom PG of the respective first bit cell type 108 and second bit cell type 110, are not perfectly aligned. In some embodiments, the top PG and bottom PG may be shifted by a certain displacement due to lithography and / or other patterning processes. [, S (e.g., measured as the centerline-to-centerline distance between individual PGs). The practical result of this misalignment is that, for the parallelogram-stacked SRAM bit cell design 100 described herein, the full 25% reduction in SRAM footprint is not achieved. The achieved footprint reduction percentage increases with shift distance. [, S The footprint decreases as the offset increases. In some embodiments, the shift distance S is between zero (no shift) and a complete offset of approximately half the width of the PG region. At the complete offset (i.e., when the top PG and bottom PG are minimally vertically aligned), the footprint reduction decreases to approximately 15%. Therefore, the percentage reduction in footprint achieved by the parallelogram stacked SRAM bit cell design can range from approximately 15% to a full 25%, depending on the degree of alignment (offset distance) between the top PG and bottom PG. [, S , ]) and so on.

[0069] Figure 8 depicts a flowchart illustrating a method 800 for forming a 3T transistor (3T) footprint stacked SRAM architecture according to one or more embodiments. Method 800 is described with reference to Figures 1 through 7 and may include additional blocks not depicted in Figure 8. Although depicted in a specific order, the blocks depicted in Figure 8 may be reconfigured, subdivided, and / or combined.

[0070] As shown in block 802, the method includes forming a first inverter positioned at a first obtuse angle of a parallelogram. In some embodiments, the first inverter includes a first PU stacked vertically above the first PD.

[0071] As shown in block 804, the method includes forming a second inverter positioned at a second obtuse angle of a parallelogram. In some embodiments, the second inverter includes a second PU stacked vertically above the second PD.

[0072] As shown in block 806, the method includes forming a first PG located at the first acute angle of the parallelogram.

[0073] As shown in block 808, the method includes forming a second PG located at the second acute angle of the parallelogram.

[0074] In some embodiments, the method includes forming a VDD line located on the front side of an SRAM bit cell and forming a VSS line located on the back side of an SRAM bit cell.

[0075] In some embodiments, the first PU and the second PU are located at the top level of the SRAM bit cell, and the first PD and the second PD are located at the bottom level below the top level.

[0076] In some embodiments, the method includes forming a WL and a BL. In some embodiments, a first PG and a second PG are located on the top level, and the WL and BL are positioned on the front side of the SRAM bit cell.

[0077] In some embodiments, the method includes forming a WL and a BL. In some embodiments, a first PG and a second PG are located on a bottom layer, and the WL and BL are located on the back side of an SRAM bit cell.

[0078] In some embodiments, the method includes first forming a bottom layer (bottom layer) of SRAM bit cells on the surface of a wafer (not shown separately); then forming a top layer (top layer), followed by MOL and front BEOL elements. In some embodiments, the bottom wafer is bonded to another wafer and flipped. In some embodiments, the original wafer (substrate) is removed and the back MOL and BEOL are formed.

[0079] Figure 9 depicts a flowchart illustrating a method 900 for forming a semiconductor device according to one or more embodiments. Method 900 is described with reference to Figures 1 through 7 and may include additional blocks not depicted in Figure 9. Although depicted in a specific order, the blocks depicted in Figure 9 may be reconfigured, subdivided, and / or combined.

[0080] As shown at block 902, the method includes forming a first SRAM bit cell having a first bit cell type. In some embodiments, the first bit cell type includes a first pair of PGs located in the top level of the first SRAM bit cell.

[0081] As shown at block 902, the method includes forming a second SRAM bit cell having a second bit cell type. In some embodiments, the second bit cell type includes a second pair of PGs located in the bottom layer of the second SRAM bit cell.

[0082] In some embodiments, the first SRAM bit cell and the second SRAM bit cell are adjacent bit cells. In some embodiments, the channel gates of the first SRAM bit cell and the channel gates of the second SRAM bit cell are vertically stacked in the same channel gate region, such that the first SRAM bit cell and the second SRAM bit cell partially overlap in the 3T footprint.

[0083] In some embodiments, each of the first SRAM bit cell and the second SRAM bit cell includes a first inverter positioned at a first obtuse angle of a parallelogram. The first inverter includes a first PU stacked vertically above the first PD. The second inverter is positioned at a second obtuse angle of the parallelogram. The second inverter includes a second PU stacked vertically above the second PD. The first PG is positioned at a first acute angle of the parallelogram, and the second PG is positioned at a second acute angle of the parallelogram.

[0084] In some embodiments, a first pair of PGs located in the top layer of a first SRAM bit cell has a first polarity, and a second pair of PGs located in the bottom layer of a second SRAM bit cell has a second polarity opposite to the first polarity. In some embodiments, when the first pair of PGs and the second pair of PGs have opposite polarities in this manner, the first pair of PGs located in the top layer (top PGs) and the second pair of PGs located in the bottom layer (bottom PGs) have electrically isolated gates.

[0085] In some embodiments, the first SRAM bit cell includes a first WL and a first BL located on the front side of the first SRAM bit cell, and the second SRAM bit cell includes a second WL and a second BL located on the back side of the second SRAM bit cell.

[0086] In some embodiments, a first pair of PGs located in the top layer of a first SRAM bit cell and a second pair of PGs located in the bottom layer of a second SRAM bit cell have the same polarity. In some embodiments, the method includes forming a WL located on the front side of the semiconductor device, forming a first BL located on the front side of the semiconductor device, and forming a second BL located on the back side of the semiconductor device. In some embodiments, when the first pair of PGs and the second pair of PGs have the same polarity in this manner, the top PG and the bottom PG have electrically connected gates, and the WL is electrically connected to the top PG and the bottom PG.

[0087] The methods and structures described herein can be used to manufacture IC chips. The resulting IC chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in a monochip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multichip package (such as a ceramic carrier with either or both surface-mount or embedded interconnects). In any case, the chips are subsequently integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product including the IC chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0088] Various embodiments of this disclosure are described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of this disclosure. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) are depicted between elements in the following description and in the drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent while maintaining the described functionality even if the orientation is changed. Unless otherwise specified, such connections and / or positional relationships may be direct or indirect, and this disclosure is not intended to be limiting in this regard. Similarly, the term "coupled" and its variations describe the presence of a communication path between two elements and do not imply a direct connection between the elements or the absence of an inserting element / connection between the two elements. All such variations are considered part of this specification. Accordingly, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, referring to the current description of a layer "A" formed above layer "B" including one or more intermediate layers (e.g., layer "C") located between layer "A" and layer "B", as long as the relevant characteristics and functions of layer "A" and layer "B" are not substantially changed by one or more intermediate layers.

[0089] The following definitions and abbreviations are used to explain the scope of the patent application and this specification. As used herein, the terms "comprises / comprising," "includes / including," "has / having," "contains or containing," or any other variations thereof are intended to cover non-exclusive inclusions. For example, a composition, mixture, procedure, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, procedure, method, article, or apparatus.

[0090] Furthermore, the term "illustrative" as used herein means "serving as an example, example, or illustration." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as superior or advantageous to other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plural" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0091] The embodiments described in this specification using references to "one embodiment," "an embodiment," "an example embodiment," etc., may include specific features, structures, or characteristics, but each embodiment may or may not include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, it should be argued that, whether explicitly described or not, implementing that feature, structure, or characteristic in combination with other embodiments is within the understanding of those skilled in the art.

[0092] For the purposes of the description herein, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall be oriented as shown in the accompanying drawings and relating to the described structure and method. The terms “overlapping,” “on top,” “on top of,” “positioned on,” or “positioned on top” mean that a first element, such as a first structure, exists on a second element, such as a second structure, wherein an intervening element, such as an interface structure, may exist between the first and second elements. The term “direct contact” means that the first element, such as a first structure, and the second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0093] For ease of description, spatially relative terms, such as "below," "under," "lower," "above," "upper," and similar terms, are used herein to describe the relationship between one element or feature and another element(s) as illustrated in the figures. It should be understood that spatially relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as "below" or "under" other elements or features will subsequently be oriented "above other elements or features." Therefore, the term "below" can cover both orientations above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0094] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include a degree of error associated with a measurement based on a specific quantity of equipment available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0095] The phrase "selective towards" means that the first element is selective towards the second element, such as "the first element is selective towards the second element". This means that the first element can be etched and the second element can act as the etch stop (i.e., the second element remains).

[0096] The term "conformal" (e.g., conformal layer or conformal deposition) means that the thickness of a layer is substantially the same on all surfaces, or the thickness variation is less than 15% of the nominal thickness of the layer.

[0097] The terms "epitaxy growth and / or deposition" and "epitaxy formation and / or growth" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), wherein the growing semiconductor material (crystalline overlay) has substantially the same crystallization characteristics as the semiconductor material (seed material) deposited on the surface. In the epitaxial deposition process, the chemical reactants provided by the source gas can be controlled, and system parameters can be set so that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move back and forth on the surface, causing the deposited atoms themselves to orient themselves towards the crystal configuration of the atoms on the deposition surface. The epitaxially grown semiconductor material can have substantially the same crystallization characteristics as the deposition surface formed by the epitaxially grown material. For example, deposited on... <100> Epitaxial growth of semiconductor materials on directional crystallized surfaces can be achieved using... <100> Orientation. In some embodiments disclosed herein, epitaxial growth and / or deposition processes may be selective for forming materials, such as silicon dioxide or silicon nitride surfaces, on semiconductor surfaces and may or may not be deposited on other exposed surfaces.

[0098] As used herein, "p-type" refers to the addition of impurities to a pure semiconductor that creates defects that produce valence electrons. Examples of p-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium.

[0099] As used herein, "n-type" refers to the addition of impurities that contribute free electrons to a pure semiconductor. Examples of n-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus.

[0100] As previously noted herein, for the sake of brevity, prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, with the aid of the background, a more general description of semiconductor device manufacturing processes that can be used to implement one or more embodiments of this disclosure is now provided. Although specific manufacturing operations for implementing one or more embodiments of this disclosure may be individually known, the described combinations of operations and / or resulting structures are unique. Therefore, the unique combinations of operations described in the manufacture of semiconductor devices according to this disclosure utilize various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0101] Generally, the various processes used to form microchips to be packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), and similar processes. For example, reactive ion etching (RIE) is a type of dry etching that uses chemically reactive plasma to remove material, such as masked patterns of semiconductor materials, by exposing the material to ion bombardment, causing portions of the material to be removed from the exposed surface. The plasma is typically generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping modifies electrical properties, primarily through diffusion and / or ion implantation, by doping, for example, the source and drain electrodes of a transistor. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Films of both conductors (e.g., polycrystalline silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate the transistors and their components. Selective doping of various regions of a semiconductor substrate allows for alteration of the substrate's conductivity by applying voltage. By creating the structures of these various components, millions of transistors can be built and wired together to form the complex circuit systems of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional raised image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called photoresist. To build the complex structures of the transistors and the numerous wires connecting the millions of transistors in the circuitry, the lithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with a previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built in to form the final device.

[0102] The flowcharts and block diagrams in the figures illustrate possible implementations of manufacturing and / or operating methods according to various embodiments of this disclosure. Various functions / operations of the methods are represented by blocks in the flowcharts. In some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown in a sequential manner may actually be executed substantially simultaneously, or such blocks may sometimes be executed in reverse order.

[0103] Various embodiments of the invention have been described for illustrative purposes, but such descriptions are not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles, practical applications, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments described herein.

[0104] 100: Parallelogram Stacked SRAM Bit Cell Design 102: Transistor Channel 104: First row group 106: Second row group 108: First element type 110: Second bit unit type 200: Circuit Design Layout 202: Active Area 204: Gate 206:SDB 208: Front contact 210: Front contact 302: Front BEOL component 402: Backside contact 404: Backside contact 502: Backside BEOL component 600: Cross-sectional view 602: PG Zone 604: Sidewall band 700: Cross-sectional view 800: Method 802: Block 804: Block 806: Block 808: Block 900: Method 902: Block 904: Block AA: Line BL: Bitline BLC: Bitline INV: Inverter INV1: First Inverter INV2: Second inverter [, O Offset distance [, P ]:spacing PG: Channel gate PG1: First channel gate PG2: Second channel gate [, S ]: Distance of shift VDD: Supply voltage VSS: Source supply voltage WL: Character Line XC: Contact

Claims

1. A method for forming a static random access memory (SRAM) bit cell, the method comprising: forming a first inverter positioned at a first obtuse angle of a parallelogram, the first inverter comprising a first pull-up transistor (PU) vertically stacked above a first pull-down transistor (PD); forming a second inverter positioned at a second obtuse angle of the parallelogram, the second inverter comprising a second PU vertically stacked above a second PD; forming a first channel gate (PG) positioned at a first acute angle of the parallelogram; and forming a second PG positioned at a second acute angle of the parallelogram.

2. The method of claim 1, further comprising: forming a supply voltage (VDD) line located on the front side of one of the SRAM bit cells; and forming a source supply voltage (VSS) line located on the back side of one of the SRAM bit cells.

3. The method of claim 2, wherein the first PU and the second PU are located at a top level of one of the SRAM bit cells, and the first PD and the second PD are located at a bottom level below the top level.

4. The method of claim 3, further comprising: forming a word line (WL); and forming a bit line (BL); wherein the first PG and the second PG are located on the top level; and wherein the WL and the BL are located on the front side of the SRAM bit cell.

5. The method of claim 3, further comprising: forming a word line (WL); and forming a bit line (BL); wherein the first PG and the second PG are located on the bottom level; and wherein the WL and the BL are located on the back side of the SRAM bit cell.

6. A static random access memory (SRAM) bit cell comprising: a first inverter positioned at a first obtuse angle of a parallelogram, the first inverter comprising a first pull-up transistor (PU) vertically stacked above a first pull-down transistor (PD); a second inverter positioned at a second obtuse angle of the parallelogram, the second inverter comprising a second PU vertically stacked above a second PD; a first channel gate (PG) positioned at a first acute angle of the parallelogram; and a second PG positioned at a second acute angle of the parallelogram.

7. The SRAM bit cell of claim 6 further includes: a supply voltage (VDD) line located on the front side of one of the SRAM bit cells; and a source supply voltage (VSS) line located on the back side of one of the SRAM bit cells.

8. The SRAM bit cell of claim 7, wherein the first PU and the second PU are located at a top level of one of the SRAM bit cells, and the first PD and the second PD are located at a bottom level below the top level.

9. The SRAM bit cell of claim 8 further includes: a word line (WL); and a bit line (BL); wherein the first PG and the second PG are located on the top level; and wherein the WL and the BL are located on the front side of the SRAM bit cell.

10. The SRAM bit cell of claim 8 further includes: a word line (WL); and a bit line (BL); wherein the first PG and the second PG are located on the bottom level; and wherein the WL and the BL are located on the back side of the SRAM bit cell.

11. A method for forming a semiconductor device, the method comprising: forming a first static random access memory (SRAM) bit cell comprising one of a first bit cell types, the first bit cell type having a first pair of channel gates (PGs) located in a top layer of one of the first SRAM bit cells; and forming a second SRAM bit cell comprising one of a second bit cell types, the second bit cell type having a second pair of PGs located in a bottom layer of one of the second SRAM bit cells; wherein the first SRAM bit cell and the second SRAM bit cell are adjacent bit cells; and wherein the channel gates of the first SRAM bit cell and the channel gates of the second SRAM bit cell are vertically stacked in the same channel gate region, such that the first SRAM bit cell and the second SRAM bit cell partially overlap in a 3T transistor footprint.

12. The method of claim 11, wherein each of the first SRAM bit cell and the second SRAM bit cell comprises: a first inverter positioned at a first obtuse angle of a parallelogram, the first inverter comprising a first pull-up transistor (PU) vertically stacked above a first pull-down transistor (PD); a second inverter positioned at a second obtuse angle of the parallelogram, the second inverter comprising a second PU vertically stacked above a second PD; a first channel gate (PG) positioned at a first acute angle of the parallelogram; and a second PG positioned at a second acute angle of the parallelogram.

13. The method of claim 12, wherein the first pair of PGs located in the top layer of the first SRAM bit cell has a first polarity, and the second pair of PGs located in the bottom layer of the second SRAM bit cell has a second polarity opposite to the first polarity.

14. The method of claim 13, wherein the first SRAM bit cell includes a first word line (WL) and a first bit line (BL) located on the front side of one of the first SRAM bit cells, and wherein the second SRAM bit cell includes a second WL and a second BL located on the back side of one of the second SRAM bit cells.

15. The method of claim 12, wherein the first pair of PGs located in the top layer of the first SRAM bit cell and the second pair of PGs located in the bottom layer of the second SRAM bit cell have the same polarity, the method further comprising: forming a word line (WL) located on the front side of one of the semiconductor devices; forming a first bit line (BL) located on the front side of the semiconductor device; and forming a second BL located on the back side of one of the semiconductor devices.

16. A semiconductor device comprising: a first static random access memory (SRAM) bit cell including a first bit cell type having a first pair of channel gates (PGs) located in a top layer of one of the first SRAM bit cells; and a second SRAM bit cell including a second bit cell type having a second pair of PGs located in a bottom layer of one of the second SRAM bit cells; wherein the first SRAM bit cell and the second SRAM bit cell are adjacent bit cells; and wherein the channel gates of the first SRAM bit cell and the channel gates of the second SRAM bit cell are vertically stacked in the same channel gate region such that the first SRAM bit cell and the second SRAM bit cell partially overlap in a 3T transistor footprint.

17. The semiconductor device of claim 16, wherein each of the first SRAM bit cell and the second SRAM bit cell comprises: a first inverter positioned at a first obtuse angle of a parallelogram, the first inverter comprising a first pull-up transistor (PU) vertically stacked above a first pull-down transistor (PD); a second inverter positioned at a second obtuse angle of the parallelogram, the second inverter comprising a second PU vertically stacked above a second PD; a first channel gate (PG) positioned at a first acute angle of the parallelogram; and a second PG positioned at a second acute angle of the parallelogram.

18. The semiconductor device of claim 17, wherein the first pair of PGs located in the top layer of the first SRAM bit cell has a first polarity, and the second pair of PGs located in the bottom layer of the second SRAM bit cell has a second polarity opposite to the first polarity.

19. The semiconductor device of claim 18, wherein the first SRAM bit cell includes a first word line (WL) and a first bit line (BL) located on the front side of one of the first SRAM bit cells, and wherein the second SRAM bit cell includes a second WL and a second BL located on the back side of one of the second SRAM bit cells.

20. The semiconductor device of claim 17, wherein the first pair of PGs located in the top layer of the first SRAM bit cell and the second pair of PGs located in the bottom layer of the second SRAM bit cell have the same polarity, the semiconductor device further comprising: a word line (WL) located on a front side of the semiconductor device; a first bit line (BL) located on the front side of the semiconductor device; and a second BL located on a back side of the semiconductor device.

21. A static random access memory (SRAM) bit cell comprising: a first inverter positioned at a first obtuse angle of a parallelogram, the first inverter comprising a first pull-down crystal (PD) vertically stacked above a first pull-up crystal (PU); a second inverter positioned at a second obtuse angle of the parallelogram, the second inverter comprising a second PD vertically stacked above a second PU; a first channel gate (PG) positioned at a first acute angle of the parallelogram; and a second PG positioned at a second acute angle of the parallelogram.

22. The SRAM bit cell of claim 21 further includes: a supply voltage (VDD) line located on the front side of one of the SRAM bit cells; and a source supply voltage (VSS) line located on the back side of one of the SRAM bit cells.

23. The SRAM bit cell of claim 22, wherein the first PD and the second PD are located at a top level of one of the SRAM bit cells, and the first PU and the second PU are located at a bottom level below the top level.

24. The SRAM bit cell of claim 23 further includes: a word line (WL); and a bit line (BL); wherein the first PG and the second PG are located on the top level; and wherein the WL and the BL are located on the front side of the SRAM bit cell.

25. The SRAM bit cell of claim 23 further includes: a word line (WL); and a bit line (BL); wherein the first PG and the second PG are located on the bottom level; and wherein the WL and the BL are located on the back side of the SRAM bit cell.

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