Semiconductor device and electronic device

Abstract

A novel semiconductor device is provided. The semiconductor device includes a structure extending in a first direction, a first conductor, and a second conductor extending in a second direction. The structure includes a third conductor, a first insulator, a first semiconductor, and a second insulator. At a first intersection where the structure intersects with the first conductor, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are arranged concentrically. At a second intersection where the structure intersects with the second conductor, the first insulator, the first semiconductor, the second insulator, the fourth conductor, and the fourth insulator are arranged concentrically around the third conductor.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] One embodiment of the present invention is not limited to the above-described technical field. The technical field of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, explicitly, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. Prior Technology

[0003] In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), memory devices, and sensors have been used in various electronic devices such as personal computers, smartphones, and digital cameras, and these electronic components have been improved in various aspects such as miniaturization and low power consumption.

[0004] In particular, the amount of data used in the aforementioned electronic devices is increasing, thus creating a demand for memory devices with larger memory capacities. As a method to increase memory capacity, NAND memory elements with a three-dimensional structure using metal oxides as their channel forming regions are disclosed, for example, in Patent Documents 1 and 2.

[0005] [Patent Document 1] PCT International Application Publication No. 2019 / 3060 [Patent Document 2] Japanese Patent Application Publication No. 2018-207038 Summary of the Invention

[0006] One objective of one embodiment of the present invention is to provide a memory device with high reliability. Furthermore, one objective of one embodiment of the present invention is to provide a memory device with large memory capacity. Furthermore, one objective of one embodiment of the present invention is to provide a novel memory device. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with high reliability. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with large memory capacity. Furthermore, one objective of one embodiment of the present invention is to provide a novel semiconductor device.

[0007] Note that the purpose of one embodiment of the present invention is not limited to the above-described purposes. The above-described purposes do not preclude the existence of other purposes. Other purposes refer to those other than those described below, which will be described in the following description. Those skilled in the art can derive and appropriately concoct other purposes from the description in the specification or drawings, etc. One embodiment of the present invention achieves at least one of the above-described and other purposes. Furthermore, one embodiment of the present invention does not necessarily need to achieve all of the above-described and other purposes.

[0008] One embodiment of the present invention is a semiconductor device including an arithmetic processing unit and a memory device, the arithmetic processing unit and the memory device including overlapping regions, the memory device including a plurality of memory cells, each of the plurality of memory cells including an oxide semiconductor, and the memory device being of the NAND type and operating as RAM.

[0009] One embodiment of the present invention is a semiconductor device comprising a structure extending in a first direction, a first conductor and a second conductor extending in a second direction, the structure comprising a third conductor extending in the first direction, a first insulator adjacent to the third conductor, a first semiconductor adjacent to the first insulator, and a second insulator adjacent to the first semiconductor, at a first intersection where the structure intersects with the first conductor, a second semiconductor adjacent to the second insulator and a third insulator adjacent to the second semiconductor are included between the structure and the first conductor, at a second intersection where the structure intersects with the second conductor, the structure comprises a fourth conductor adjacent to the second insulator and a fourth insulator adjacent to the fourth conductor, at the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor and the third insulator are arranged concentrically around the third conductor, and at the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth conductor and the fourth insulator are arranged concentrically around the third conductor.

[0010] The first direction is orthogonal to the second direction. Furthermore, the first intersection is used as a data writing transistor, and the second intersection is used as a data reading transistor and capacitor.

[0011] The first crossover portion can be used as a transistor. Furthermore, the second crossover portion can be used as both a transistor and a capacitor. The aforementioned semiconductor device can, for example, be used as a NAND-type memory device.

[0012] At least one of the first semiconductor and the second semiconductor is preferably an oxide semiconductor. The oxide semiconductor preferably comprises at least one of indium and zinc.

[0013] Furthermore, another embodiment of the present invention is an electronic device that includes at least one of an operation switch, a battery, and a display unit, and the aforementioned semiconductor device.

[0014] According to one embodiment of the present invention, a memory device with high reliability can be provided. Furthermore, a memory device with large memory capacity can be provided. Furthermore, a novel memory device can be provided. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a semiconductor device with large memory capacity can be provided. Furthermore, a novel semiconductor device can be provided.

[0015] Note that the effects of one embodiment of the present invention are not limited to those described above. The above effects do not preclude the existence of other effects. Other effects refer to effects other than those described above, which will be described in the following description. Those skilled in the art can derive and appropriately conjure effects other than those described above from the description in the specification or drawings, etc. Furthermore, one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may sometimes lack the above-described effects, depending on the circumstances. Simple Explanation of the Diagram

[0016] In the diagram: [Figure 1A] is a three-dimensional view of the memory unit, and [Figure 1B] is a cross-sectional view of the memory unit; [Figure 2A] and [Figure 2B] are cross-sectional views of memory cells; [Figure 3A] and [Figure 3B] are cross-sectional views of memory cells; Figures 4A to 4C are the equivalent circuit diagrams of the memory cells; [Figure 5A] and [Figure 5B] are equivalent circuit diagrams of memory cells; [Figure 6] is a cross-sectional view of the memory string; [Figure 7] is the equivalent circuit diagram of the memory string; [Figure 8] is the equivalent circuit diagram of the memory string; [Figure 9] is the equivalent circuit diagram of the memory string; [Figure 10] is the equivalent circuit diagram of the memory string; [Figure 11A] and [Figure 11B] are top views of the memory string; [Figure 12A] and [Figure 12B] are cross-sectional views of memory cells; [Figure 13A] and [Figure 13B] are cross-sectional views of memory cells; [Figure 14] is a cross-sectional view of a memory unit; [Figure 15] is a cross-sectional view of a memory unit; [Figure 16A] and [Figure 16B] are cross-sectional views of memory cells; [Figure 17A] and [Figure 17B] are cross-sectional views of memory cells; [Figure 18A] is a three-dimensional view of the memory unit, and [Figure 18B] is a cross-sectional view of the memory unit; [Figure 19A] is a three-dimensional view of the memory unit, and [Figure 19B] is a cross-sectional view of the memory unit; [Figure 20A] and [Figure 20B] are cross-sectional views of memory cells; [Figure 21] is a cross-sectional view of a memory cell; [Figure 22A] and [Figure 22B] are cross-sectional views of memory cells; [Figure 23A] and [Figure 23B] are cross-sectional views of memory cells; [Figure 24A] and [Figure 24B] are cross-sectional views of memory cells; [Figure 25A] and [Figure 25B] are cross-sectional views of memory cells; [Figure 26] is a top view of the memory string; [Figure 27A] is a diagram illustrating the classification of crystal structures of oxide semiconductors; [Figure 27B] is a diagram illustrating the XRD pattern of a CAAC-IGZO film; [Figure 27C] is a diagram illustrating the nano-beam electron diffraction pattern of a CAAC-IGZO film. [Figure 28A] and [Figure 28B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 29A] and [Figure 29B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 30A] and [Figure 30B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 31A] and [Figure 31B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 32A] and [Figure 32B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 33A] and [Figure 33B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 34A] is a cross-sectional view illustrating the manufacturing method of the memory cell, and [Figure 34B] is a perspective view illustrating the manufacturing method of the memory cell; [Figure 35A] and [Figure 35B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 36A] and [Figure 36B] are cross-sectional views illustrating the manufacturing method of memory cells; [Figure 37] is a circuit diagram of a semiconductor device; [Figure 38A] and [Figure 38B] are timing diagrams illustrating an example of the operation of a semiconductor device; [Figure 39A] is a perspective view illustrating an example of the structure of a semiconductor device; [Figure 39B] is a top view illustrating an example of the structure of a semiconductor device; [Figure 39C] is a cross-sectional view illustrating an example of the structure of a semiconductor device. [Figure 40A] is a perspective view illustrating an example of the structure of a semiconductor device; [Figure 40B] is a top view illustrating an example of the structure of a semiconductor device; [Figure 40C] is a cross-sectional view illustrating an example of the structure of a semiconductor device. [Figure 41A] and [Figure 41B] are cross-sectional views illustrating a semiconductor device; [Figure 42A] and [Figure 42B] are cross-sectional views illustrating a semiconductor device; [Figure 43] is a block diagram illustrating an example of the structure of a semiconductor device. Figures 44A to 44G are diagrams illustrating examples of the circuit structure of a memory cell; Figures 45A and 45B are diagrams illustrating examples of the circuit structure of a memory cell; Figures 46A to 46C are perspective views illustrating examples of the structure of a semiconductor device; [Fig. 47A] is a perspective view showing an example of a semiconductor wafer, [Fig. 47B] is a perspective view showing an example of a semiconductor chip, and [Fig. 47C] and [Fig. 47D] are perspective views showing an example of an electronic component; [Figure 48] is a block diagram illustrating the CPU; [Figure 49A] and [Figure 49B] are perspective views of a semiconductor device; [Figure 50A] and [Figure 50B] are perspective views of a semiconductor device; [Figure 51A] and [Figure 51B] are perspective views of a semiconductor device; [Figure 52A] and [Figure 52B] are diagrams illustrating various classes of memory devices; [Figures 53A] to [Figures 53J] are perspective views or schematic diagrams illustrating an example of an electronic device; [Figures 54A] to [Figures 54E] are perspective views or schematic diagrams illustrating an example of an electronic device; Figures 55A to 55C are illustrations of an example of an electronic device; [Figure 56] is a diagram illustrating an example of the structure of a computer system; [Figure 57] is a diagram showing the hierarchical structure and requirements specifications of IoT networks; [Figure 58] is a schematic diagram of factory automation. Implementation

[0017] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips equipped with integrated circuits, and electronic components that house chips in packages. In addition, memory devices, display devices, light-emitting devices, lighting equipment, and electronic devices are themselves semiconductor devices, or sometimes include semiconductor devices.

[0018] Furthermore, in this specification, when it is stated as "X and Y are connected," it indicates that the following situations are disclosed in this specification: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the drawings or text; other connection relationships are also described within the scope of the drawings or text. X and Y are both objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0019] As an example of an electrical connection between X and Y, more than one component capable of electrically connecting X and Y (such as a switch, transistor, capacitor, inductor, resistor, diode, display device, light-emitting device, load, etc.) can be connected between X and Y. Furthermore, the switch has the function of controlling whether it is turned on or off. In other words, whether current flows is controlled by placing the switch in a conducting state (on state) or a non-conducting state (off state).

[0020] As an example of a functional connection between X and Y, one or more circuits that functionally connect X and Y can be connected between them (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-to-analog converters, analog-to-digital converters, gamma correction circuits, etc.), voltage level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifting circuits that change the voltage level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.). Note that, for example, even if there are other circuits between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.

[0021] Furthermore, when explicitly stated as "X and Y are electrically connected", it includes the following cases: X and Y are electrically connected (in other words, X and Y are connected in a way that includes other components or other circuits); and X and Y are directly connected (in other words, X and Y are connected in a way that does not include other components or other circuits).

[0022] For example, it can be represented as "X, Y, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and X, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to Y in sequence." Alternatively, it can be represented as "the source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to Y in sequence." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.), and Y are arranged in sequence." By specifying the connection order in the circuit structure using the same display method as this example, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished, thus determining the scope of the technology. Note that this display method is an example and is not limited to the display methods described above. Here, X and Y represent objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0023] Furthermore, even when components that are independent on a circuit diagram are electrically connected to each other, sometimes a single component can function as multiple components. For example, when a portion of a wiring is used as an electrode, a conductive film functions as both a wiring and an electrode. Therefore, the scope of "electrical connection" in this specification also includes such cases where a conductive film functions as multiple components.

[0024] In this specification, "resistive element" includes, for example, circuit elements and wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring with a resistance value, transistors through which current flows between the source and drain, diodes, coils, etc. Therefore, "resistive element" can also be called "resistor," "load," "area with a resistance value," etc., and conversely, "resistor," "load," and "area with a resistance value" can also be called "resistive element," etc. As for the resistance value, it is preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Furthermore, it can also be 1Ω or more and 1×10⁹Ω or less, for example.

[0025] In this specification, etc., "capacitor" includes, for example, circuit elements having an electrostatic capacitance value higher than 0F, wiring regions having an electrostatic capacitance value, parasitic capacitance, gate capacitance of a transistor, etc. Therefore, in this specification, "capacitor" includes not only circuit elements having a pair of electrodes and a dielectric between those electrodes, but also parasitic capacitance generated between wirings, gate capacitance generated between one of the source and drain electrodes of a transistor and the gate, etc. "Capacitor," "parasitic capacitance," "gate capacitance," etc., can also be called "capacitor," etc., and conversely, "capacitor" can also be called "capacitor," "parasitic capacitance," "gate capacitance," etc. Furthermore, the "pair of electrodes" of a "capacitor" can also be called "pair of conductors," "pair of conductive regions," "pair of regions," etc. The electrostatic capacitance value can, for example, be 0.05fF or more and 10pF or less. Furthermore, for example, it can also be 1pF or more and 10μF or less.

[0026] In this specification, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals, one of the two input and output terminals is used as the source and the other as the drain. Therefore, in this specification, the source and drain can be interchanged. In this specification, when describing the connection relationship of the transistor, the terms "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. Furthermore, depending on the structure of the transistor, sometimes a back gate is included in addition to the above three terminals. In this case, in this specification, sometimes one of the gate and back gate of the transistor is called the first gate, and the other of the gate and back gate is called the second gate. Moreover, in the same transistor, the "gate" and "back gate" can sometimes be interchanged. Furthermore, when a transistor includes three or more gates, each gate is sometimes referred to as the first gate, the second gate, the third gate, etc. in this specification and other documents.

[0027] Furthermore, in this specification and other materials, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, or impurity regions, depending on the circuit structure or device structure. Additionally, terminals and wiring may also be referred to as nodes.

[0028] Furthermore, in this instruction manual and other documents, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference between the reference potential and the reference potential; for example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Grounding potential does not necessarily mean 0V. Furthermore, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0029] Furthermore, in this specification and the like, "high potential (also called "H potential" or "H")" and "low potential (also called "L potential" or "L")" do not imply specific potentials. For example, if two wirings are both designated as "wirings used to supply high potentials," the high potentials supplied by the two wirings may be different. Similarly, if two wirings are both designated as "wirings used to supply low potentials," the low potentials supplied by the two wirings may be different.

[0030] "Current" refers to the phenomenon of charge movement (conductivity). For example, the description "conductivity occurs in a positively charged body" can be replaced with the description "conductivity occurs in a negatively charged body in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge movement (conductivity) when carriers move. Here, carriers can include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Furthermore, in wiring, etc., "direction of current" refers to the direction of positive carrier movement and is described as a positive current quantity. In other words, the direction of carrier movement is opposite to the current direction and is described as a negative current quantity. Therefore, in this specification, unless otherwise specified, regarding the positive or negative (or direction) of the current, descriptions such as "current flows from element A to element B" can be replaced with descriptions such as "current flows from element B to element A." Furthermore, descriptions such as "current is input to element A" can be replaced with descriptions such as "current is output from element A."

[0031] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the components. Therefore, these ordinal numbers do not limit the number of components. Furthermore, these ordinal numbers do not limit the order of the components. Moreover, for example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in other embodiments or claims. Furthermore, for example, a component referred to as "first" in one embodiment may be omitted in other embodiments or claims.

[0032] Furthermore, terms such as "above" or "below" are not limited to situations where the components are positioned "directly above" or "directly below" and in direct contact. For example, if the statement is "electrode B on insulating layer A," it is not necessarily required that electrode B is formed in direct contact on insulating layer A; it can also include situations where other components are included between insulating layer A and electrode B.

[0033] Furthermore, the positional relationships of the components are appropriately changed depending on the orientation of each component. Therefore, the wording is not limited to that described in the instruction manual, etc., and can be appropriately changed as needed. For example, in this instruction manual, etc., for convenience, terms such as "above" and "below" are sometimes used to indicate the arrangement to illustrate the positional relationships of the components with reference to the diagram. Therefore, in the description of "insulator located on the top surface of the conductor," by rotating the orientation of the diagram by 180 degrees, it can also be called "insulator located below the conductor." Furthermore, in the description of "insulator located on the top surface of the conductor," by rotating the orientation of the diagram by 90 degrees, it can also be called "insulator located on the left (or right) side of the conductor."

[0034] Similarly, in this specification and other documents, terms such as "overlapping" do not limit the state of the stacking order of components. For example, "electrode B overlapping with insulating layer A" is not limited to the state of "electrode B being formed on insulating layer A", but also includes the state of "electrode B being formed under insulating layer A" or "electrode B being formed on the right (or left) side of insulating layer A".

[0035] In this specification and other materials, terms such as "adjacent" or "near" do not limit the state of direct contact between components. For example, if the description is "electrode B adjacent to insulating layer A", it does not necessarily mean that insulating layer A and electrode B are in direct contact; it may also include situations where other components are included between insulating layer A and electrode B.

[0036] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged depending on the situation. For example, sometimes "conductive layer" may be replaced with "conductive film." Also, sometimes "insulating film" may be changed to "insulating layer." Furthermore, depending on the situation or state, other terms may be used to replace "film" and "layer." For example, sometimes "conductive layer" or "conductive film" may be changed to "conductor." Also, for example, sometimes "insulating layer" or "insulating film" may be changed to "insulator."

[0037] Note that in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit the components. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, "electrode" or "wiring" also includes cases where multiple "electrodes" or "wiring" are formed as one unit. Similarly, for example, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wiring," and "terminals" are formed as one unit. Therefore, for example, an "electrode" can be part of a "wiring" or a "terminal," and vice versa. Furthermore, terms such as "electrode," "wiring," and "terminal" are sometimes replaced with terms such as "area."

[0038] In this specification and other materials, the terms "wiring," "signal line," and "power line" may be interchanged depending on the situation or state. For example, sometimes "wiring" may be changed to "signal line." Similarly, sometimes "wiring" may be changed to "power line." Conversely, sometimes "signal line" or "power line" may be changed to "wiring." Sometimes "power line" may be changed to "signal line." Conversely, sometimes "signal line" may be changed to "power line." Furthermore, depending on the situation or state, the "potential" applied to the wiring may be interchanged with "signal." Conversely, sometimes "signal" may be changed to "potential."

[0039] In this specification, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor film. For example, elements with a concentration of less than 0.1 atomic% are considered impurities. When impurities are present, for example, the defect state density in the semiconductor may increase, carrier mobility may decrease, or crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that alter the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, especially, for example, hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that alter the semiconductor properties include, for example, oxygen, Group 1 elements (excluding hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements.

[0040] In this specification, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches the current path. As an example of a switch, an electrical switch or a mechanical switch can be used. In other words, a switch is not limited to a specific component as long as it can control current.

[0041] Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, metal-insulator-semiconductor (MIS) diodes, or diode-connected transistors), or logic circuits combining these components. When a transistor is used as a switch, the "on state" of a transistor refers to the state where the source and drain electrodes of the transistor are electrically short-circuited. Conversely, the "off state" of a transistor refers to the state where the source and drain electrodes of the transistor are electrically disconnected. When a transistor is used solely as a switch, there are no particular restrictions on the transistor's polarity (conductivity type).

[0042] As an example of a mechanical switch, a switch utilizing MEMS (Micro-Electro-Mechanical Systems) technology can be cited. This switch has mechanically movable electrodes, and operates by controlling the on / off state by moving these electrodes.

[0043] Furthermore, in this specification and other materials, "on-state current" sometimes refers to the current flowing between the source and drain when the transistor is in the on-state. Additionally, "off-state current" sometimes refers to the current flowing between the source and drain when the transistor is in the off-state.

[0044] In this specification, "parallel" means that the angle formed by two straight lines is greater than or equal to -10° and less than 10°. Therefore, it also includes angles greater than or equal to -5° and less than 5°. "Approximately parallel" means that the angle formed by two straight lines is greater than or equal to -30° and less than 30°. Furthermore, "perpendicular" means that the angle formed by two straight lines is greater than or equal to 80° and less than 100°. Therefore, it also includes angles greater than or equal to 85° and less than 95°. "Approximately perpendicular" means that the angle formed by two straight lines is greater than or equal to 60° and less than 120°. Furthermore, "orthogonal" means that the angle formed by two straight lines is greater than or equal to 80° and less than 100°. Therefore, it also includes angles greater than or equal to 85° and less than 95°.

[0045] In this instruction manual and the like, when referring to count values ​​or measurement values, objects, methods and phenomena converted into count values ​​or measurement values, the terms "same", "identical", "equal" or "uniform" are used, unless otherwise specified, an error of ±20% is included.

[0046] In this specification and the like, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the active layer of a transistor, it is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel-forming region of a transistor that includes at least one of amplification, rectification, and switching functions, it is called a metal oxide semiconductor, or simply OS. Furthermore, OS transistors may also be referred to as transistors containing metal oxides or oxide semiconductors.

[0047] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0048] Furthermore, the structures shown in each embodiment in this specification and the like can be appropriately combined with the structures shown in other embodiments to constitute an embodiment of the present invention. Moreover, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0049] Furthermore, the content (or a portion thereof) described in one embodiment can be applied / combined / replaced with at least one of the other content (or a portion thereof) described in that embodiment and the content (or a portion thereof) described in one or more other embodiments.

[0050] Note that the content described in the embodiments refers to the content illustrated using various diagrams or the content described using the text in the instruction manual.

[0051] Furthermore, more diagrams can be formed by combining a diagram (or a portion thereof) shown in one embodiment with other portions of that diagram, other diagrams (or a portion thereof) shown in that embodiment, and at least one diagram (or a portion thereof) shown in one or more other embodiments.

[0052] The embodiments described in this specification are illustrated with reference to the accompanying drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited only to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same element symbols are sometimes used in different drawings to represent the same parts or parts having the same function, and repeated descriptions are omitted. In perspective views or top views, for clarity, illustrations of some components are sometimes omitted.

[0053] In the drawings, for clarity, sizes, layer thicknesses, or areas are sometimes exaggerated. Therefore, the invention is not limited to the dimensions or aspect ratios shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples, and the invention is not limited to the shapes or values ​​shown in the drawings. For example, it may include non-uniformity of signals, voltages, or currents caused by noise or timing deviations.

[0054] Furthermore, in this specification and other documents, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as “_1”, “[n]”, and “[m,n]” are sometimes added to the symbol for identification. For example, two wiring GLs are sometimes denoted as wiring GL[1] and wiring GL[2].

[0055] Implementation Method 1 Figure 1A is a perspective view of a memory unit 100 according to an embodiment of the present invention. The memory unit 100 is a memory device having a three-dimensional stacked structure. In Figure 1A, a portion of the memory unit 100 is omitted for ease of understanding of its internal structure. Note that arrows indicating the X, Y, and Z directions are sometimes included in the figures. The X, Y, and Z directions are orthogonal to each other. In this specification, the X, Y, or Z direction is sometimes referred to as the "first direction." Furthermore, another direction is sometimes referred to as the "second direction." Additionally, the remaining direction is sometimes referred to as the "third direction." In Figures 1A and 1B, the direction parallel to the central axis 108 is referred to as the Z direction.

[0056] <Example of memory unit structure> Figure 1B is a cross-sectional view showing a portion of the memory cell 100 shown in Figure 1A. Furthermore, Figure 1B is a cross-sectional view of a portion of the memory cell 100 viewed from the Y direction. Additionally, Figure 1B is a cross-sectional view through the XZ plane of the central axis 108. Figure 3A is a cross-sectional view of the portion shown by dashed lines A1-A2 in Figure 1B viewed from the Z direction. Figure 3B is a cross-sectional view of the portion shown by dashed lines B1-B2 in Figure 1B viewed from the Z direction.

[0057] The memory cell 100 includes a plurality of insulators 101 disposed above a substrate (not shown). The plurality of insulators 101 are stacked sequentially from one side of the substrate. In this embodiment, etc., insulator 101[i] refers to the i-th (i is an integer greater than or equal to 1) insulator 101. FIG1B shows an insulator 101[i+1] disposed above insulator 101[i] and an insulator 101[i+2] disposed above insulator 101[i+1]. Furthermore, a conductor 102 is included between insulator 101[i] and insulator 101[i+1], and a conductor 103 is included between insulator 101[i+1] and insulator 101[i+2]. The insulator 101, conductor 102, and conductor 103 extend in the Y direction.

[0058] Furthermore, the memory unit 100 includes a structure 130. The structure 130 extends in the Z direction along the central axis 108. The structure 130 has a columnar or cylindrical shape. The structure 130 shown in Figures 1A to 3B includes an insulator 111, a conductor 112, a semiconductor 113, a semiconductor 114, an insulator 115, a semiconductor 116, an insulator 117, a conductor 118, etc. Figure 2A is a cross-sectional view in which the structure 130 is omitted.

[0059] Furthermore, in this embodiment, the outer periphery of the structure 130 is shown to be circular when viewed from the Z direction; however, the outer periphery of the structure 130 is not limited to a circle. For example, it can be a polygon such as a triangle or a quadrilateral. Furthermore, the outer periphery of the structure 130 can be composed of curves or a combination of curves and straight lines. Additionally, as shown in Figures 1A to 2B, the structure 130 has concave and convex surfaces on its side extending in the Z direction.

[0060] Furthermore, the memory cell 100 has a region 132. Region 132 is formed during the manufacturing process of the memory cell 100 by removing a portion of the insulator 101 and the conductor 103. Additionally, a semiconductor 121, an insulator 122, an insulator 123, and a conductor 102 are disposed in region 132. For ease of identification of region 132, a cross-sectional view omitting the components disposed in region 132 is shown in FIG. 2B.

[0061] Region 132 is disposed around structure 130. Furthermore, when viewed from a direction perpendicular to the Z direction, region 132 has a region 135 overlapping a recess of structure 130 and a region 136 overlapping a protrusion of structure 130 (see Figures 2A and 2B). Additionally, region 136 includes a region overlapping structure 130 with an insulator 101 and a region overlapping structure 130 with a conductor 103.

[0062] As described above, structure 130 has a columnar or cylindrical shape. Specifically, conductor 118 extends along the central axis 108 in the Z direction, and insulator 117 is adjacent to conductor 118. Furthermore, semiconductor 116 is adjacent to insulator 117. Furthermore, insulator 115 is adjacent to semiconductor 116. Furthermore, semiconductor 114 is adjacent to insulator 115. In addition, at the protrusion of structure 130, semiconductor 113 is adjacent to semiconductor 114, conductor 112 is adjacent to semiconductor 113, and insulator 111 is adjacent to conductor 112.

[0063] As shown in Figure 3A, in the recess of structure 130, insulator 117, semiconductor 116, insulator 115, and semiconductor 114 are arranged concentrically around conductor 118. Furthermore, in the recess of structure 130, semiconductor 114 is adjacent to semiconductor 121, and semiconductor 121 is adjacent to insulator 122. Additionally, conductor 102 extending in the Y direction intersects the recess of structure 130.

[0064] In the region of structure 130 that intersects (overlaps) with conductor 102, conductor 118, insulator 117, semiconductor 116, insulator 115, semiconductor 114, semiconductor 121, insulator 122, and conductor 102 are used as transistor WTr. That is, transistor WTr is formed at the intersection of structure 130 and conductor 102.

[0065] In memory cell 100, conductor 102 serves as the gate electrode of transistor WTr. Therefore, insulator 122 serves as the gate insulator. Additionally, semiconductor 121 can also be used as the gate insulator. Semiconductor 114 serves as the semiconductor in which the channel is formed. Furthermore, conductor 118 sometimes serves as the back gate electrode. Therefore, insulator 117, semiconductor 116, and insulator 115 sometimes serve as back gate insulators. Figure 3A is also a cross-sectional view of transistor WTr viewed from the Z direction.

[0066] Furthermore, as shown in Figure 3B, in the protrusion of structure 130, insulator 117, semiconductor 116, insulator 115, semiconductor 114, semiconductor 113, conductor 112, and insulator 111 are arranged concentrically around conductor 118. Additionally, conductor 103 extending in the Y direction intersects with the protrusion of structure 130.

[0067] In the structure 130, the conductor 118, insulator 117, semiconductor 116, insulator 115, semiconductor 114, semiconductor 113, and conductor 112 in the region (overlapping region) where they intersect with conductor 103 serve as transistor RTr. Furthermore, the overlapping region of conductor 103, insulator 111, and conductor 112 serves as capacitor Cs. In other words, transistor RTr and capacitor Cs are formed at the intersection of structure 130 and conductor 103.

[0068] In the transistor RTr, conductor 112 serves as the gate electrode of the transistor RTr. Additionally, semiconductors 113 and 114 are sometimes used as gate electrodes of the transistor RTr. In the transistor RTr, insulator 115 serves as the gate insulating layer, and semiconductor 116 serves as the semiconductor in which the channel is formed. As described above, conductor 118 is sometimes used as the back gate electrode. Consequently, insulator 117 is sometimes used as the back gate insulating layer. Figure 3B is also a cross-sectional view of the transistor RTr and capacitor Cs viewed from the Z direction.

[0069] Figure 4A is an equivalent circuit diagram of memory cell 100. In Figure 4A, one of the source and drain terminals of transistor WTr is electrically connected to conductor 112, and the other of the source and drain terminals is electrically connected to the gate of transistor RTr. The gate of transistor WTr is electrically connected to conductor 102. One electrode of capacitor Cs is electrically connected to the gate of transistor RTr, and the other electrode is electrically connected to conductor 103.

[0070] In this specification, the node where the gate of transistor RTR, the source and drain of transistor WTR, and one of the electrodes of capacitor Cs are electrically connected is called node ND.

[0071] A portion of semiconductor 116 serves as the channel forming region of transistor RTr. Furthermore, another portion of semiconductor 116 serves as the source or drain of transistor RTr. The transistor RTr shown in FIG. 4A is a transistor with a back gate. In this embodiment, a portion of conductor 118 serves as the back gate of transistor RTr. Furthermore, a portion of conductor 102 serves as the gate of transistor WTr. Furthermore, a portion of conductor 103 serves as another electrode in capacitor Cs. Furthermore, a portion of conductor 112 serves as one of the source and drain of transistor WTr.

[0072] Furthermore, as shown in Figure 4B, the transistor RTr may also not have a back gate. Figure 4B corresponds to the equivalent circuit diagram of the memory cell 100H described later. Furthermore, as shown in Figure 4C, the transistor WTr may also have a back gate. Figure 4C shows an example of a circuit structure in which the back gate of the transistor WTr is electrically connected to the conductor 118; however, in addition to the conductor 118, other conductors electrically connected to the back gate of the transistor WTr may also be provided. Furthermore, the circuit structures shown in Figures 5A or 5B may also be used.

[0073] Figure 6 is a cross-sectional view of a memory string 200 including four memory cells 100 (memory cells 100[1] to memory cells 100[4]). Figure 7 is an equivalent circuit diagram of the memory string 200. The memory string 200 has a structure in which the four memory cells 100 are connected in series. Thus, the memory string 200 is a memory device similar to that of the NAND type.

[0074] Furthermore, in equivalent circuit diagrams, etc., to clearly indicate that the transistor is an OS transistor, the circuit symbol of the transistor is sometimes added with "OS". Similarly, to clearly indicate that the transistor is a Si transistor (a transistor in which silicon is used in the semiconductor layer forming the channel), the circuit symbol of the transistor is sometimes added with "Si". In Figure 7, both transistors WTr and RTr are OS transistors.

[0075] In addition, the memory string 200 shown in FIG6 has 9 layers of insulator 101 (insulator 101[1] to insulator 101[9]) and 4 layers of conductor 102 (conductor 102[1] to conductor 102[4]) and 4 layers of conductor 103 (conductor 103[1] to conductor 103[4]).

[0076] Furthermore, in Figure 7, the transistor WTr, transistor RTr, and capacitor Cs of memory unit 100[1] are respectively denoted as transistor WTr[1], transistor RTr[1], and capacitor Cs[1]. The same applies to the transistor WTr, transistor RTr, and capacitor Cs of memory units 100[2] to 100[4].

[0077] Furthermore, the number of memory units 100 in the memory string 200 is not limited to 4. When the number of memory units 100 in the memory string 200 is n, n can be an integer greater than or equal to 2.

[0078] Furthermore, the "structure of multiple memory cells 100 connected in series" refers to the following structure: the drain (or source) of the transistor WTr[k] contained in memory cell 100[k] (k is an integer greater than 1 and less than n) is electrically connected to the source (or drain) of the transistor WTr[k+1] contained in memory cell 100[k+1], and the drain (or source) of the transistor RTr[k] contained in memory cell 100[k] is electrically connected to the source (or drain) of the transistor RTr[k+1] contained in memory cell 100[k+1].

[0079] The semiconductor in which the channel is formed in the transistor WTr and the transistor RTr can be one or more of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, and amorphous semiconductors. For example, silicon or germanium can be used as the semiconductor material. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0080] Furthermore, the semiconductor used in transistors can be a multilayer semiconductor. When the semiconductor layers have a multilayer structure, semiconductors with different crystal states can be used, and different semiconductor materials can be used separately.

[0081] In particular, the transistor WTr is preferably an oxide semiconductor transistor (also known as an "OS transistor") that uses one of the metal oxides in the semiconductor layer where the channel is formed. The band gap of the oxide semiconductor is 2 eV or more, resulting in very low off-state current. By using an OS transistor as the transistor WTr, the charge written to the node ND (also known as a "memory node") can be stored for a long time. When an OS transistor is used as the transistor constituting the memory cell 100, the memory cell 100 can be referred to as an "OS memory". Furthermore, the memory string 200 including the memory cell 100 can also be referred to as an "OS memory".

[0082] NAND-type memory devices that include OS memory are also called "OS NAND type" or "OS NAND type memory devices". In addition, OS NAND-type memory devices with a structure in which multiple OS memory modules are stacked in the Z direction are also called "3D OS NAND type" or "3D OS NAND type memory devices".

[0083] Furthermore, the transistor RTr can also be a silicon transistor (also known as a "Si transistor") used in the semiconductor layer where the channel is formed. The transistor RTr can be formed from a Si transistor, and the transistor WTr can be formed from an OS transistor. Figure 8 is an equivalent circuit diagram of the memory string 200 when the transistor WTr and the transistor RTr use OS transistors and Si transistors, respectively.

[0084] Even without power, OS memory can store written data for more than a year, or even more than 10 years. Therefore, OS memory can be regarded as non-volatile memory.

[0085] Furthermore, because the amount of charge written to the OS memory remains constant over a long period of time, the OS memory is not limited to two values ​​(1 bit) but can store multi-value (multi-bit) data.

[0086] Furthermore, OS memory uses OS transistors to write charge to nodes, eliminating the need for the high voltages required by conventional flash memory and enabling high-speed writing. OS memory also eliminates the need for the data deletion process required for flash memory. Moreover, it avoids charge injection and extraction from floating gates or charge trapping layers, allowing for virtually unlimited data writing and reading. Compared to conventional flash memory, OS memory exhibits less degradation and offers higher reliability.

[0087] Furthermore, OS memory does not undergo atomic-level structural changes like magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM). Therefore, OS memory has higher rewrite tolerance than MRAM and ReRAM.

[0088] Furthermore, even at high temperatures, the off-state current of the OS transistor hardly increases. Specifically, even at ambient temperatures above room temperature and below 200°C, the off-state current hardly increases. Moreover, even at high temperatures, the on-state current of the OS transistor does not easily decrease. Memory devices including OS memory operate stably and reliably even at high temperatures. Furthermore, the source-drain dielectric withstand voltage of the OS transistor is high. By using OS transistors as transistors in semiconductor devices, semiconductor devices that operate stably and reliably even at high temperatures can be realized.

[0089] Furthermore, as shown in Figure 9, depending on the purpose or application, the transistor WTr can be a Si transistor, and the transistor RTr can be an OS transistor. Furthermore, as shown in Figure 10, depending on the purpose or application, both the transistor WTr and the transistor RTr can be Si transistors.

[0090] Like memory string 200, by continuously arranging multiple memory units 100 in the Z direction, the memory capacity per unit area can be increased.

[0091] Furthermore, in order to increase the memory capacity of the semiconductor device using memory cells 100 or memory strings 200, the multiple memory cells 100 or multiple memory strings 200 can be arranged in an interlaced shape (see Figure 11A) or a grid shape (see Figure 11B). Figures 11A and 11B are top views of memory strings.

[0092] Table 1 shows a comparison between 3D NAND memory devices made of Si transistors and 3D OS NAND memory devices.

[0093] [Table 1]

[0094] [Variation Example] Next, a modified example of memory cell 100 will be described. The modified examples of memory cells described below can be appropriately combined with another memory cell shown in this specification, etc.

[0095] Figure 12A is a cross-sectional view of memory cell 100A. Memory cell 100A is a modified example of memory cell 100. Therefore, in this embodiment, the differences between memory cell 100A and memory cell 100 will be mainly explained.

[0096] As shown in the memory cell 100A in Figure 12A, the memory cell of one embodiment of the present invention may also remove the semiconductor 121, insulator 122, and conductor 102 in regions that do not overlap with insulator 101 and / or conductor 103 when viewed from the Z direction. Therefore, the insulator 123 of the memory cell 100A may also include regions contacting insulator 101, regions contacting conductor 103, regions contacting semiconductor 121, regions contacting insulator 122, and regions contacting conductor 102.

[0097] Figure 12B is a cross-sectional view of memory cell 100B. Memory cell 100B is a variation of memory cell 100A. Like memory cell 100B, the formation of semiconductor 121 can also be omitted. In memory cell 100B, conductor 118, insulator 117, semiconductor 116, insulator 115, semiconductor 114, insulator 122, and conductor 102 in the region (overlapping region) of structure 130 intersecting with conductor 102 serve as transistor WTr. By omitting semiconductor 121, the manufacturing process can be simplified, and the productivity of the memory device can be improved.

[0098] Figure 13A is a cross-sectional view of memory cell 100C. Memory cell 100C is a variation of memory cell 100A. Like memory cell 100C, the formation of semiconductor 113 can be omitted, and a structure in which conductor 112 contacts semiconductor 114 can be used instead. In memory cell 100C, conductor 118, insulator 117, semiconductor 116, insulator 115, semiconductor 114, and conductor 112 in the region (overlapping region) of structure 130 that intersects with conductor 103 serve as transistor RTr. By omitting semiconductor 113, the manufacturing process can be simplified, and the productivity of memory devices can be improved.

[0099] Figure 13B is a cross-sectional view of memory cell 100D. Memory cell 100D is a variation of memory cell 100B and also a variation of memory cell 100C. Like memory cell 100D, the formation of semiconductor 113 can be omitted, and a structure in which conductor 112 contacts semiconductor 114 can be used. The transistor WTr in memory cell 100D has the same structure as memory cell 100B. Furthermore, the transistor RTr in memory cell 100D has the same structure as memory cell 100C. By omitting semiconductor 113 and semiconductor 121, the manufacturing process can be simplified, and the productivity of memory devices can be improved.

[0100] Figure 14 is a cross-sectional view of memory cell 100E. Figure 14 is a cross-sectional view of memory cell 100E[k] and memory cell 100E[k+1] adjacent to memory cell 100E[k]. Memory cell 100E is a variation of memory cell 100A. Like memory cell 100E, the formation of insulator 101 can be omitted, and a structure in which conductor 103 contacts semiconductor 121 can be used. By omitting insulator 101, the manufacturing process can be simplified, and the productivity of memory devices can be improved.

[0101] Figure 15 is a cross-sectional view of memory cell 100F. Figure 15 is a cross-sectional view of memory cell 100F[k] and memory cell 100F[k+1] adjacent to memory cell 100F[k]. Memory cell 100F is a variation of memory cell 100B. Like memory cell 100F, the formation of insulator 101 can be omitted, and a structure in which conductor 103 contacts insulator 122 can be adopted. Furthermore, like memory cell 100D, the formation of semiconductor 113 can be omitted. By omitting insulator 101 and / or semiconductor 113, the manufacturing process can be simplified, and the productivity of memory devices can be improved.

[0102] Figure 16A is a cross-sectional view of memory cell 100G. Memory cell 100G is a variation of memory cell 100A. Like memory cell 100G, a stack of semiconductors 114a and 114b can also be used as semiconductor 114. Figure 16A shows an example with semiconductor 114a in contact with insulator 115 and semiconductor 114b in contact with semiconductor 114a. The stack is not limited to two layers and can also be three or more layers. Furthermore, semiconductor 116 can also be a stack of multiple semiconductors. Furthermore, the composition of semiconductor 114 when it is formed from a stack of oxide semiconductors will be described in detail later.

[0103] Figure 16B is a cross-sectional view of memory cell 100H. Memory cell 100H is a variation of memory cell 100A. Like memory cell 100H, the conductor 118 may be omitted. In Figure 16B, an insulator 117 is used instead of the conductor 118. Furthermore, the conductor 118 may be omitted, forming a void. By omitting the conductor 118, the manufacturing process can be simplified, and the productivity of the memory device can be improved.

[0104] Furthermore, in the memory cell 100H, the semiconductor 116, insulator 115, semiconductor 114, semiconductor 121, insulator 122, and conductor 102 in the region (overlapping region) of the structure 130 intersecting with conductor 102 are used as transistors WTr. Additionally, the semiconductor 116, insulator 115, semiconductor 114, semiconductor 113, and conductor 112 in the region (overlapping region) of the structure 130 intersecting with conductor 103 are used as transistors RTr.

[0105] Figure 17A is a cross-sectional view of memory cell 100I. Memory cell 100I is a variation of memory cell 100. Like memory cell 100I, semiconductor 121 may not be provided. By omitting semiconductor 121, the manufacturing process can be simplified, and the productivity of the memory device can be improved. Furthermore, memory cell 100I is also a variation of memory cell 100B. The transistors WTr and RTr in memory cell 100I have the same structure as in memory cell 100B.

[0106] Figure 17B is a cross-sectional view of memory cell 100J. Memory cell 100J is a variation of memory cell 100 and also a variation of memory cell 100D. Like memory cell 100J, semiconductors 121 and 113 may be omitted. By omitting semiconductors 121 and 113, the manufacturing process can be simplified, and the productivity of the memory device can be improved. Furthermore, memory cell 100J is also a variation of memory cell 100I. The transistors WTr and RTr in memory cell 100J have the same structure as in memory cell 100D.

[0107] Figure 18A is a perspective view of memory cell 100K. Furthermore, Figure 18B is a cross-sectional view of a portion of memory cell 100K. In Figure 18A, a portion of memory cell 100K is omitted for ease of understanding of its internal structure.

[0108] Memory cell 100K is a variation of memory cell 100G. In memory cell 100K, not only is semiconductor 114 a stacked structure of semiconductors 114a and 114b, as in memory cell 100G, but semiconductor 116 is also a stacked structure of semiconductors 116a, 116b, and 116c. Furthermore, the composition of semiconductor 116 when it is formed from a stack of oxide semiconductors will be described in detail later.

[0109] Figures 18A and 18B show examples of semiconductors 116a, 116b, 116c, and 115 that are in contact with insulator 117. Furthermore, insulator 115 may also be a stack of multiple insulators. The combination of multiple insulators when insulator 115 is formed will be described in detail later.

[0110] The memory cell 100K has a stacked structure of semiconductors 116a, 116b, 116c, insulator 115, 114a, 114b, 121, and insulator 122. This region may function as a superlattice. Furthermore, the insulator 122 may also be a stack of multiple insulators. The combination of multiple insulators when the insulator 122 is formed will be described in detail later.

[0111] Furthermore, in the memory cell 100K, the conductor 102 is a stack of conductors 102f and 102s. In Figures 18A and 18B, conductors 102f and 102s are provided that are in contact with the insulator 122. The configuration of the conductor 102 when it has a stacked structure will be described in detail later.

[0112] Figure 19A is a perspective view of memory cell 100L. Furthermore, Figure 19B is a cross-sectional view showing a portion of memory cell 100L. In Figure 19A, a portion of memory cell 100L is omitted for ease of understanding of its internal structure.

[0113] Memory cell 100L is a modified example of memory cell 100. Therefore, in this embodiment, the differences between memory cell 100L and memory cell 100 will be mainly described. Memory cell 100L has a structure in which semiconductors 113 and 114 are omitted from memory cell 100. By omitting semiconductors 113 and 114, the manufacturing process can be simplified and the productivity of memory devices can be improved.

[0114] In memory cell 100L, a portion of semiconductor 121 serves as a channel forming region for transistor WTr. Therefore, semiconductor 121 used in memory cell 100L can be made of the same material as semiconductor 114 in memory cell 100 or semiconductor 114b in memory cell 100G.

[0115] Figure 20A is a cross-sectional view of memory cell 100M. Furthermore, Figure 20B is a cross-sectional view of memory cell 100N. Memory cells 100M and 100N are both variations of memory cell 100A. Therefore, in this embodiment, the differences between memory cells 100M and 100N and memory cell 100A will be primarily explained.

[0116] Memory cell 100M has a structure in which semiconductors 113 and 114 are omitted from memory cell 100A. Memory cell 100N has a structure in which semiconductor 114 is omitted from memory cell 100A. By omitting semiconductors 113 and / or 114, the manufacturing process can be simplified and the productivity of memory devices can be improved.

[0117] Furthermore, memory cells 100M and 100N are also variations of memory cell 100L. Therefore, in memory cells 100M and 100N, a portion of semiconductor 121 is also used as a channel forming region for transistor WTr. The semiconductor 121 used in memory cells 100M or 100N can also be made of the same material as semiconductor 114 in memory cell 100 or semiconductor 114b in memory cell 100G.

[0118] Figure 21 is a cross-sectional view of memory cell 100P. Figure 22A is a cross-sectional view of the portion shown by the dotted lines C1-C2 in Figure 21, viewed from the Z direction. Figure 22B is a cross-sectional view of the portion shown by the dotted lines D1-D2 in Figure 21, viewed from the Z direction. Memory cell 100P is a modified example of memory cell 100. Therefore, in this embodiment, the differences between memory cell 100P and memory cell 100 will be mainly explained.

[0119] The memory cell 100P has a structure that cuts off the memory cell 100, the conductor 102, and the conductor 103 along a direction that passes through the center of the memory cell 100 and extends from the conductor 102 and the conductor 103. In this embodiment, an insulator 124 is provided in the cut-off area, but an insulator 124 may be provided as needed.

[0120] Insulator 101, conductor 102, conductor 103, semiconductor 121, insulator 122 and structure 130 are respectively divided into insulator 101a (not shown) and insulator 101b (not shown), conductor 102a and conductor 102b, conductor 103a and conductor 103b, semiconductor 121a and semiconductor 121b, insulator 122a and insulator 122b, and structure 130a and structure 130b.

[0121] The insulator 111, conductor 112, semiconductor 113, semiconductor 114, insulator 115, semiconductor 116, insulator 117 and conductor 118 included in the structure 130 are respectively divided into insulator 111a and insulator 111b, conductor 112a and conductor 112b, semiconductor 113a and semiconductor 113b, semiconductor 114a and semiconductor 114b, insulator 115a and insulator 115b, semiconductor 116a and semiconductor 116b, insulator 117a and insulator 117b, conductor 118a and conductor 118b.

[0122] Therefore, structure 130a includes insulator 111a, conductor 112a, semiconductor 113a, semiconductor 114a, insulator 115a, semiconductor 116a, insulator 117a, and conductor 118a. Furthermore, structure 130b includes insulator 111b, conductor 112b, semiconductor 113b, semiconductor 114b, insulator 115b, semiconductor 116b, insulator 117b, and conductor 118b.

[0123] Furthermore, memory cell 100P is divided into memory cell 100Pa and memory cell 100Pb. Therefore, it can be said that memory cell 100P includes a region used as memory cell 100Pa and a region used as memory cell 100Pb. Memory cell 100Pa includes structure 130a, etc., while memory cell 100Pb includes structure 130b, etc.

[0124] Therefore, in memory cell 100P, transistor RTr, transistor WTr, and capacitor Cs are respectively divided into transistors RTrA and RTrB, transistor WTrA and WTrB, and capacitors CsA and CsB. Transistor RTrA, transistor WTrA, and capacitor CsA are included in memory cell 100PA. Transistor RTrB, transistor WTrB, and capacitor CsB are included in memory cell 100Pb.

[0125] The overlapping region of conductor 112a, semiconductor 113a, semiconductor 114a, insulator 115a, semiconductor 116a, insulator 117a, and conductor 118a is used as transistor RTrA. The overlapping region of conductor 112b, semiconductor 113b, semiconductor 114b, insulator 115b, semiconductor 116b, insulator 117b, and conductor 118b is used as transistor RTrB. The overlapping region of conductor 103a, insulator 111a, and conductor 112a is used as capacitor CsA. The overlapping region of conductor 103b, insulator 111b, and conductor 112b is used as capacitor CsB. The overlapping region of conductor 102a, conductor 112a, semiconductor 121a, semiconductor 114a, insulator 115a, semiconductor 116a, insulator 117a, and conductor 118a is used as transistor WTrA. The overlapping region of conductor 102b, conductor 112b, semiconductor 121b, semiconductor 114b, insulator 115b, semiconductor 116b, insulator 117b and conductor 118b is used as transistor WTrB.

[0126] Similar to memory cell 100P, by dividing memory cell 100, storage density (memory capacity per unit area) can be increased. This allows for an increase in the memory capacity of semiconductor devices including memory cell 100. Memory cells 100A to 100N, etc., can also be divided into memory cells in the same way as memory cell 100P.

[0127] Alternatively, the memory cells can be divided along the X direction (see Figure 23A). When the memory cells are divided along the X direction, the insulator 124 does not completely traverse the conductor 102 and the conductor 103.

[0128] Alternatively, the memory cells can be divided along an inclined direction when viewed from the Z direction (the direction intersecting the X and Y directions) (see Figure 23B). When dividing the memory cells along an inclined direction, the insulator 124 does not completely traverse the conductor 102 and conductor 103.

[0129] The number of memory cell divisions is not limited to 2. For example, as shown in Figure 24A, the memory cell can also be divided into 3. Figure 24A shows the state in which structure 130, semiconductor 121, and insulator 122 are divided into structure 130a, structure 130b, structure 130c, semiconductor 121a, semiconductor 121b, semiconductor 121c, insulator 122a, insulator 122b, and insulator 122c, with Y-shaped insulator 124 as the boundary.

[0130] Furthermore, as shown in Figure 24B, the shape of the insulator 124 when viewed from the Z direction can also have a curved portion.

[0131] Furthermore, as shown in Figure 25A, the number of memory cell divisions can also be 4. Figure 25A shows the state in which structure 130, semiconductor 121, and insulator 122 are divided into structure 130a, structure 130b, structure 130c, structure 130d, semiconductor 121a, semiconductor 121b, semiconductor 121c, semiconductor 121d, insulator 122a, insulator 122b, insulator 122c, and insulator 122d, with the cross-shaped insulator 124 as the boundary.

[0132] Furthermore, as shown in Figure 25B, the insulator 124 can partially traverse the conductors 102a and 102b. Similarly, the insulator 124 can partially traverse the conductors 103a and 103b.

[0133] Furthermore, as shown in Figures 11A and 11B, when multiple memory cells 100 or multiple memory strings 200 are provided, as shown in Figure 26, the shape of the insulator 124 used to divide the memory cells 100 or memory strings 200 can be different for each memory cell 100 or memory string 200. Alternatively, the insulator 124 can be used together to divide different memory cells 100 or memory strings 200.

[0134] [Materials that make up a memory cell] The following description can be applied to the constituent materials of memory cell 100, etc.

[0135] [Substrate] The memory cell 100 and memory string 200 can be disposed on the substrate. The substrate can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride (GaN). Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. In addition, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Alternatively, substrates with components disposed on these substrates can also be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0136] [Insulator] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0137] In this specification, "oxynitride" refers to a material containing more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material containing more oxygen than nitrogen. Furthermore, in this specification, "nitrogen oxide" refers to a material containing more nitrogen than oxygen. For example, "aluminum oxynitride" refers to an aluminum material containing more nitrogen than oxygen.

[0138] For example, when miniaturizing and hyper-integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using high-k materials as the gate insulator, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. On the other hand, by using materials with relatively low permittivity in the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0139] Examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0140] Examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide or resin.

[0141] Furthermore, by surrounding the OS transistor with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical properties of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride, can be used as insulators that suppress the permeation of impurities such as hydrogen and oxygen.

[0142] Furthermore, when using oxide semiconductors as semiconductors 116, 114, 113, and / or 121, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is removed by heating is contacted with semiconductors 114 and / or 116, the oxygen vacancies contained in semiconductors 114 and / or 116 can be filled.

[0143] Furthermore, as an insulator, either a single insulating layer formed from the aforementioned material or a stack of multiple insulating layers formed from the aforementioned material can be used.

[0144] For example, when an insulator is provided in contact with a conductor, the insulator is preferably an insulator that inhibits oxygen permeation to prevent oxidation of the conductor. For example, hafnium oxide, aluminum oxide, or silicon nitride are preferably used as such an insulator.

[0145] Furthermore, when a multilayer insulator is provided in contact with a conductor, the insulator in contact with the conductor is preferably an insulator that has the function of suppressing oxygen permeation. For example, hafnium oxide can be used to form the insulator in contact with the conductor, and silicon oxynitride can be used to form the insulator in contact with the insulator.

[0146] [Conductor] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, so they are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicates can also be used.

[0147] Furthermore, as a conductor, either a single conductive layer formed from the aforementioned materials or a stack of multiple conductive layers formed from the aforementioned materials can be used. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0148] Furthermore, when using an oxide semiconductor, which is one type of metal oxide, in the channel formation region of a transistor, it is preferable to employ a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material as the conductor used as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from the conductive material can be easily supplied to the channel formation region.

[0149] In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the oxide semiconductor in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide can also be used. By using the above materials, hydrogen contained in the oxide semiconductor in which the channel is formed can sometimes be trapped. Or, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0150] [Oxide Semiconductor] Semiconductors 116, 114, 113, and / or 121 are preferably oxide semiconductors. In particular, semiconductor 114 is preferably an oxide semiconductor. The oxide semiconductor that can be used in memory cell 100 will be described below.

[0151] The oxide semiconductor preferably contains at least indium or zinc. More preferably, it contains both indium and zinc. Furthermore, it preferably also contains aluminum, gallium, yttrium, tin, etc. Additionally, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0152] This section considers the case where the oxide semiconductor is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M can be one or more of aluminum, gallium, yttrium, or tin. Other elements that can be used with element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. Note that multiple of these elements can sometimes be combined as element M.

[0153] [Classification of Crystal Structures] First, the classification of crystal structures in oxide semiconductors will be explained with reference to Figure 27A. Figure 27A is a diagram illustrating the classification of crystal structures in oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0154] As shown in Figure 27A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." Furthermore, "completely amorphous" is included within "Amorphous." Additionally, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Moreover, the "Crystalline" classification does not include single crystal, poly crystal, or completely amorphous. Furthermore, "Crystal" includes both single crystal and poly crystal.

[0155] Furthermore, the structure in the thickened portion of Figure 27A is an intermediate state between "amorphous" and "crystal," belonging to a novel crystalline phase. In other words, this structure is completely different from "crystal" or the energy-unstable "amorphous."

[0156] X-ray diffraction (XRD) spectroscopy can be used to evaluate the crystal structure of films or substrates. Here, Figure 27B shows the XRD spectrum of a CAAC-IGZO film classified as "Crystalline" obtained by GIXD (Grazing-Incidence XRD). Furthermore, the GIXD method is also known as the thin film method or the Seemann-Bohlin method. The XRD spectrum obtained by the GIXD measurement shown in Figure 27B will be simply referred to as the XRD spectrum. Furthermore, the composition of the CAAC-IGZO film shown in Figure 27B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Furthermore, the thickness of the CAAC-IGZO film shown in Figure 27B is 500 nm.

[0157] As shown in Figure 27B, peaks indicating clear crystallinity were detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis alignment was detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 27B, the peak near 2θ=31° is asymmetrical about the angle at which the peak intensity was detected.

[0158] Furthermore, the crystal structure of the film or substrate can be evaluated using diffraction patterns observed by nanobeam electron diffraction (NBED). Figure 27C shows the diffraction pattern of the CAAC-IGZO film. Figure 27C is the diffraction pattern observed by NBED with an electron beam incident in a direction parallel to the substrate. Furthermore, the composition of the CAAC-IGZO film shown in Figure 27C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Additionally, in nanobeam electron diffraction, an electron diffraction method with a beam diameter of 1 nm was performed.

[0159] As shown in Figure 27C, multiple spots representing c-axis alignment were observed in the diffraction pattern of the CAAC-IGZO film.

[0160] [Structure of oxide semiconductors] Furthermore, when focusing on the crystal structure of oxide semiconductors, the classification of oxide semiconductors sometimes differs from that in Figure 27A. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include, for example, the aforementioned CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) and nc-OS (nanocrystalline Oxide Semiconductor). In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0161] Here, we will explain the details of CAAC-OS, nc-OS, and a-like OS.

[0162] [CAAC-OS] CAAC-OS is an oxide semiconductor comprising multiple crystalline regions, whose c-axis is aligned in a specific direction. This specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. Furthermore, a crystalline region is a region exhibiting a periodic atomic arrangement. Note that when atomic arrangement is considered as lattice arrangement, a crystalline region is also a region with a consistent lattice arrangement. Moreover, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and sometimes this region exhibits distortion. Distortion refers to the portion of the lattice arrangement direction that changes between lattice-aligned regions and other lattice-aligned regions within the region where multiple crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor with c-axis alignment but no obvious alignment in the ab-plane direction.

[0163] Furthermore, each of the aforementioned crystalline regions is composed of one or more microcrystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single microcrystal, the maximum diameter of that region is less than 10 nm. Conversely, when a crystalline region is composed of multiple microcrystals, the size of that region can sometimes be around tens of nm.

[0164] Furthermore, in In-M-Zn oxides, CAAC-OS tends to have a layered crystal structure (also called a layered structure) comprising layers containing stacked indium (In) and oxygen (hereinafter, In layers) and layers containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layers). In addition, indium and element M can substitute for each other. Therefore, sometimes the (M,Zn) layer contains indium. Furthermore, sometimes the In layer contains element M. Note that sometimes the In layer contains Zn. This layered structure is observed, for example, as a lattice image in high-resolution TEM images.

[0165] For example, when performing structural analysis on CAAC-OS films using an XRD apparatus, the peak value of the c-axis alignment is detected at or near 2θ = 31° in out-of-plane XRD measurements using θ / 2θ scanning. Note that the position (2θ value) representing the peak value of the c-axis alignment sometimes varies depending on the type and composition of the metallic elements constituting CAAC-OS.

[0166] Furthermore, for example, multiple bright spots (spots) were observed in the electron diffraction pattern of the CAAC-OS film. Additionally, when the spot of the incident electron beam passing through the sample (also known as the direct spot) is taken as the center of symmetry, one spot and other spots were observed at point-symmetrical positions.

[0167] When observing the crystalline region from the aforementioned specific directions, although the lattice arrangement in this region is primarily hexagonal, the unit lattice is not limited to a regular hexagon; there are also cases where it is non-regular hexagonal. Furthermore, in the aforementioned distortions, pentagonal, heptagonal, and other lattice arrangements are sometimes observed. Moreover, no clear grain boundary is observed near the distortion of CAAC-OS. That is, the distortion of the lattice arrangement inhibits the formation of grain boundaries. This may be because CAAC-OS can tolerate distortions caused by reasons such as a low density of oxygen atoms in the ab-plane direction or changes in the bonding distance between atoms due to the substitution of metal atoms.

[0168] Furthermore, a crystalline structure with clearly defined grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially leading to a decrease in the transistor's on-state current and field-effect mobility. Therefore, CAAC-OS, which lacks clearly defined grain boundaries, is one of the crystalline oxides that provides an excellent crystalline structure for the semiconductor layer of the transistor. Note that a Zn-containing structure is preferred for constructing CAAC-OS. For example, In-Zn oxides and In-Ga-Zn oxides are preferred because they can further suppress grain boundary formation compared to In oxides.

[0169] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Furthermore, the crystallinity of oxide semiconductors can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen defects). Consequently, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Thus, oxide semiconductors containing CAAC-OS possess high heat resistance and good reliability. In addition, CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS in OS transistors, process flexibility can be increased.

[0170] [nc-OS] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. In other words, nc-OS possesses tiny crystallinity. Furthermore, for example, these tiny crystallinity sizes are between 1 nm and 10 nm, particularly between 1 nm and 3 nm; these tiny crystallinity sizes are referred to as nanocrystals. Moreover, no regularity in crystallinity orientation is observed between different nanocrystals in nc-OS. Therefore, no alignment is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods. For example, when performing structural analysis on nc-OS films using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when performing electron diffraction (also known as selected area electron diffraction) on nc-OS films using an electron beam with a beam diameter larger than that of nanocrystals (e.g., larger than 50 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also known as nano-beam electron beam) is performed on nc-OS films using an electron beam whose beam diameter is close to or smaller than the size of nanocrystals (e.g., above 1 nm and below 30 nm), sometimes an electron diffraction pattern of multiple spots is observed in an annular region centered on a direct spot.

[0171] [a-like OS] a-like OS is an oxide semiconductor with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the hydrogen concentration in a-like OS films is higher than that in nc-OS and CAAC-OS films.

[0172] [Structure of oxide semiconductors] Next, the details of CAC-OS will be explained. Furthermore, it will be explained that CAC-OS is related to material composition.

[0173] [CAC-OS] CAC-OS, for example, refers to a composition in which elements are non-uniformly distributed within a metal oxide, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed within a metal oxide and the regions containing those metal elements are mixed is also referred to as mosaic or patch-like, wherein the size of the region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately.

[0174] Furthermore, CAC-OS refers to a structure in which the material is divided into a first region and a second region, forming a mosaic-like structure, with the first region distributed throughout the film (hereinafter also referred to as cloud-like). In other words, CAC-OS refers to a composite metal oxide having a structure that combines the first and second regions.

[0175] Here, each of the atomic ratios of In, Ga, and Zn, relative to the metal elements constituting the CAC-OS in In-Ga-Zn oxide, is denoted as [In], [Ga], and [Zn]. For example, in the CAC-OS of In-Ga-Zn oxide, a first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. Furthermore, a second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Alternatively, for example, a first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. Furthermore, a second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0176] Specifically, the first region mentioned above is a region whose main component is indium oxide or indium zinc oxide. Furthermore, the second region mentioned above is a region whose main component is gallium oxide or gallium zinc oxide. In other words, the first region can be referred to as a region whose main component is In. Furthermore, the second region can be referred to as a region whose main component is Ga.

[0177] Note that sometimes the clear boundaries between the first region and the second region mentioned above are not observable.

[0178] For example, in CAC-OS of In-Ga-Zn oxide, based on the EDX analysis image (EDX-mapping) obtained by Energy Dispersive X-ray spectroscopy (EDX), a structure with an unevenly distributed and mixed structure of regions with In as the main component (first region) and regions with Ga as the main component (second region) can be identified.

[0179] When CAC-OS is used in transistors, the complementary effect of conductivity arising from the first region and insulation arising from the second region enables CAC-OS to possess switching functionality (the function of controlling conduction / turn-off). In other words, a part of the CAC-OS material has conductive functionality and another part has insulating functionality, while the entire material functions as a semiconductor. By separating the conductive and insulating functions, each function can be maximized. Therefore, by using CAC-OS in transistors, high on-state current (Ion), high field-effect mobility (μ), and good switching operation can be achieved.

[0180] Oxide semiconductors possess various structures and properties. In one embodiment of the present invention, the oxide semiconductor may also include two or more of the following: amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0181] <Including oxide semiconductor transistors> Here, we will explain the case where the above-mentioned oxide semiconductor is used as a transistor.

[0182] By using the aforementioned oxide semiconductors in transistors, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can be achieved.

[0183] Furthermore, it is preferable to use an oxide conductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably below 1×10¹⁸ cm⁻³, more preferably below 1×10¹⁷ cm⁻³, further preferably below 1×10¹⁶ cm⁻³, even more preferably below 1×10¹³ cm⁻³, and still more preferably below 1×10¹² cm⁻³. When the purpose is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high purity nature" or "substantially high purity nature". In addition, oxide semiconductors with low carrier concentration are sometimes referred to as "high purity nature" or "oxide semiconductors with substantially high purity nature". Furthermore, high purity nature or substantially high purity nature is sometimes referred to as "type I" or "substantially type I".

[0184] Because high-purity or essentially high-purity oxide semiconductor films have a low defect state density, they may also have a low trap state density.

[0185] Furthermore, the charge trapped in the trap state level of an oxide semiconductor takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical properties of transistors forming channel formation regions in oxide semiconductors with high trap state density are sometimes unstable.

[0186] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical properties of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0187] [Impurities] Here, we will explain the effects of various impurities in oxide semiconductors.

[0188] When an oxide semiconductor contains silicon or carbon, one of the elements in Group 14, a defect energy level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel-forming region of the oxide semiconductor, and the concentration of silicon or carbon near the interface between the oxide semiconductor and the channel-forming region (the concentration measured by secondary ion mass spectrometry (SIMS)) are set to 2 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁷ atoms / cm³ or less.

[0189] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect energy levels can sometimes be formed, thus creating carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to have always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel-forming region of the oxide semiconductor, as measured by SIMS analysis, is set to 1 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁶ atoms / cm³ or less.

[0190] When oxide semiconductors contain nitrogen, electrons are readily generated as carriers, increasing the carrier concentration and resulting in n-type characteristics. Consequently, transistors using nitrogen-containing oxide semiconductors tend to exhibit normally-on characteristics. Alternatively, when oxide semiconductors contain nitrogen, trap levels can sometimes form. As a result, the electrical properties of the transistors can sometimes be unstable. Therefore, the nitrogen concentration in the channel-forming region of the oxide semiconductor, as measured by SIMS, is set to be below 5 × 10¹⁹ atoms / cm³, preferably below 5 × 10¹⁸ atoms / cm³, more preferably below 1 × 10¹⁸ atoms / cm³, and even more preferably below 5 × 10¹⁷ atoms / cm³.

[0191] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, thus sometimes creating oxygen vacancies. When hydrogen enters this oxygen vacancy, electrons are sometimes generated as carriers. Furthermore, sometimes a portion of the hydrogen bonds with oxygen bonded to a metal atom, generating electrons as carriers. Therefore, transistors having an oxide semiconductor containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel-forming region of the oxide semiconductor. Specifically, in the channel-forming region of the oxide semiconductor, the hydrogen concentration measured using SIMS is set to be less than 1 × 10²⁰ atoms / cm³, preferably less than 5 × 10¹⁹ atoms / cm³, more preferably less than 1 × 10¹⁹ atoms / cm³, further preferably less than 5 × 10¹⁸ atoms / cm³, and even more preferably less than 1 × 10¹⁸ atoms / cm³.

[0192] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can be made to have stable electrical characteristics.

[0193] [Other Semiconductor Materials] The semiconductor materials that can be used for semiconductors 116, 114, 113, and / or 121 are not limited to the aforementioned oxide semiconductors. Semiconductor materials with band gaps (semiconductor materials that are not zero-bandgap semiconductors) can also be used as semiconductors 116, 114, 113, and / or 121. For example, semiconductors of a single element such as silicon, compound semiconductors such as gallium arsenide, and layered materials used as semiconductors (also called atomic-layer materials, two-dimensional materials, etc.) can be used as semiconductor materials. In particular, it is preferred to use layered materials used as semiconductors as semiconductor materials.

[0194] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity, intended for use as a semiconductor, in the channel-forming region, transistors with large on-state currents can be provided.

[0195] As layered materials, examples include graphene, silicon, and chalcogenides. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0196] As a semiconductor material for a semiconductor device used in one embodiment of the present invention, a transition metal chalcogenide is preferably used as a semiconductor. Specifically, examples include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0197] [Film Formation Method] When forming conductors, insulators, or semiconductors, sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD) methods can be used.

[0198] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD, also known as chemical vapor deposition), thermal CVD (TCVD), and photo CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD, also known as metal-organic chemical vapor deposition) and metal-organic CVD (MOCVD).

[0199] By utilizing plasma CVD, high-quality films can be obtained at lower temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece can be reduced. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage the wiring, electrodes, and components in the semiconductor device. On the other hand, since this plasma damage does not occur in thermal CVD, the yield of semiconductor devices can be improved. Moreover, since plasma damage during film formation is not generated in thermal CVD, films with fewer defects can be obtained.

[0200] Furthermore, ALD is a film formation method that can reduce plasma damage to the treated material. Moreover, since no plasma damage occurs during film formation using the ALD method, films with fewer defects can be obtained.

[0201] Unlike film deposition methods that use particles released from a target, CVD and ALD methods form films based on the reaction on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed by ALD have excellent step coverage and thickness uniformity, making ALD suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes better used in combination with other film deposition methods such as CVD, which have a faster deposition rate.

[0202] CVD or ALD methods allow control of the film composition by adjusting the source gas flow rate. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate. Furthermore, for example, when using CVD or ALD, films with continuously varying compositions can be formed by changing the source gas flow rate while forming the film. When forming a film while changing the source gas flow rate, the time required for pressure adjustment and transmission is eliminated, thus shortening the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0203] Furthermore, film formation using the ALD method is performed as follows: the pressure inside the processing chamber is set to atmospheric pressure or reduced pressure, and the source gases used for the reaction are introduced into the processing chamber sequentially, and the gases are introduced repeatedly in this order. For example, two or more source gases are supplied sequentially to the processing chamber by switching various switching valves (also called high-speed valves). To prevent mixing of multiple source gases, an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the introduction of the first source gas, and then the second source gas is introduced. Note that when the first source gas and the inert gas are introduced simultaneously, the inert gas is used as the carrier gas. Alternatively, the inert gas can be introduced simultaneously with the introduction of the second source gas. Alternatively, the first source gas can be evacuated by vacuum pumping without introducing the inert gas, and then the second source gas can be introduced. The first source gas adheres to the substrate surface to form a first thinner layer, and the second source gas introduced subsequently reacts with this first layer, thereby stacking the second thinner layer on the first thinner layer to form a thin film. By repeatedly introducing the gas in this order until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the thin film can be adjusted according to the number of times the gas is introduced in sequence, the ALD method can accurately adjust the thickness and is suitable for manufacturing micro FETs.

[0204] Thermal CVD methods such as MOCVD or ALD can be used to form various films, including metal films, semiconductor films, and inorganic insulating films. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. Furthermore, not limited to the above combinations, triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0205] For example, when forming a hafnium oxide film using an ALD deposition apparatus, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, tetradimethylamine hafnium (TDMAH, Hf[N(CH3)2]4), etc.); and ozone (O3) as an oxidant. Other materials include tetra(ethylmethylamine)hafnium.

[0206] For example, when forming an alumina film using an ALD deposition apparatus, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)); and H2O as an oxidant. Other materials include tris(dimethylamino)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid).

[0207] For example, when forming a silicon oxide film using a deposition apparatus employing the ALD method, hexachlorosilane is attached to the surface to be film-forming, and free radicals of oxidizing gases (O2, nitrous oxide) are supplied to react with the attached material.

[0208] For example, when forming a tungsten film using an ALD deposition apparatus, WF6 gas and B2H6 gas are introduced sequentially and repeatedly to form an initial tungsten film, followed by the sequential and repeated introduction of WF6 gas and H2 gas to form the final tungsten film. Note that SiH4 gas can also be used instead of B2H6 gas.

[0209] For example, when forming oxide semiconductor films such as In-Ga-Zn-O films using an ALD deposition apparatus, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form an In-O layer, then Ga(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form a GaO layer, and finally Zn(CH3)2 gas and O3 gas are introduced sequentially and repeatedly to form a ZnO layer. Note that the order of these layers is not limited to the example above. Furthermore, these gases can also be used to form mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, etc. Note that although H2O gas obtained by bubbling with an inert gas such as Ar can be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Additionally, In(C2H5)3 gas can be used instead of In(CH3)3 gas. Furthermore, Ga(C2H5)3 gas can be used instead of Ga(CH3)3 gas. Furthermore, Zn(C2H5)2 gas can be used instead of Zn(CH3)2 gas.

[0210] <Examples of Memory Device Manufacturing Methods> The following is an example of the manufacturing method of memory cell 100.

[0211] First, the stack 140 shown in FIG28A is manufactured. The stack 140 includes an insulator 101, a sacrificial layer 141, and a conductor 103. The insulator 101[i] is disposed on top of a substrate (not shown), the sacrificial layer 141 is disposed on the insulator 101[i], the insulator 101[i+1] is disposed on the sacrificial layer 141, the conductor 103 is disposed on the insulator 101[i+1], and the insulator 101[i+2] is disposed on the conductor 103.

[0212] Various materials can be used as the sacrificial layer 141. For example, insulators such as silicon nitride, silicon oxide, and aluminum oxide can be used. Semiconductors such as silicon, gallium, and germanium can also be used. Conductors such as aluminum, copper, titanium, tungsten, and tantalum can also be used. Organic materials such as acrylic resin, polyimide resin, phenolic resin, and epoxy resin can also be used. In other words, because the sacrificial layer is removed later, the material used as the sacrificial layer 141 is one that achieves a higher etching rate relative to the materials used in other parts during the subsequent etching process.

[0213] As the insulator 101, it is preferable to use a material that reduces the concentration of impurities such as water or hydrogen. For example, in thermal desorption spectroscopy (TDS), within a temperature range of 50°C to 500°C, the amount of hydrogen molecules removed per unit area of ​​the insulator 101 should be 2 × 10¹⁵ molecules / cm² or less, preferably 1 × 10¹⁵ molecules / cm² or less, and more preferably 5 × 10¹⁴ molecules / cm² or less. Furthermore, the insulator 101 can be an insulator that releases oxygen upon heating. However, the materials that can be used for the insulator 101 are not limited to those described above.

[0214] Furthermore, the insulator 101 may have a stacked structure of multiple insulators. For example, the insulator 101 may have a stack of hafnium oxide and silicon oxynitride. Among the multiple insulators constituting the insulator 101, the insulator in contact with the conductor 103 is preferably an insulator that has the function of suppressing oxygen permeation as described above.

[0215] Next, a photoresist mask is formed on the stack 140, and an etching process is performed using the photoresist mask as a mask to remove a portion of the insulator 101, conductor 103 and sacrificial layer 141, so as to form an opening 131 in the stack 140 (see Figure 28B).

[0216] For example, photoresist masks can be formed using methods such as lithography, printing, and inkjet printing. When forming photoresist masks using inkjet printing, no photomask is used, which can sometimes reduce manufacturing costs. Furthermore, when performing etching, both dry etching and wet etching methods can be used, or both. Dry etching is suitable for microfabrication.

[0217] Furthermore, in photolithography, the photoresist is first exposed using a mask. Then, a developing solution is used to remove or retain the exposed area, forming a photoresist mask.

[0218] The desired shape of a conductor, semiconductor, or insulator is formed by etching through the photoresist mask. For example, the photoresist mask can be formed by exposing the photoresist to light using a KrF excimer laser, an ArF excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion etching can be used, where the space between the substrate and the projection lens is filled with a liquid (e.g., water). Electron beams or ion beams can also be used instead of the aforementioned light. Note that a mask is not required when using electron beams or ion beams. Furthermore, when removing the photoresist mask, dry etching (such as ashing) or wet etching can be performed, or a combination of dry and wet etching can be performed.

[0219] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating or conductive film that serves as the hard mask material can be formed on a conductive film, and a photoresist mask can be formed on it. The hard mask material is then etched to form a hard mask of the desired shape.

[0220] As a dry etching apparatus for etching using the dry etching method, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used, for example. The CCP etching apparatus including parallel planar electrodes can also employ a structure that supplies high-frequency power to one of the parallel planar electrodes. Alternatively, it can employ a structure that supplies multiple different high-frequency powers to one of the parallel planar electrodes. Alternatively, it can employ a structure that supplies the same high-frequency power to each of the parallel planar electrodes. Alternatively, it can employ a structure that supplies different high-frequency power to each of the parallel planar electrodes. Alternatively, a dry etching apparatus with a high-density plasma source can also be used. For example, as a dry etching apparatus with a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0221] Next, an insulator 111 is formed along the side of the opening 131 (see Figure 29A). The insulator 101, conductor 103 and sacrificial layer 141 exposed in the opening 131 are all covered by the insulator 111.

[0222] Furthermore, the insulator 111 may have a stacked structure of multiple insulators. Among the multiple insulators constituting the insulator 111, the insulator in contact with the conductor 103 and / or the conductor 112 is preferably an insulator with the function of suppressing oxygen permeation as described above. For example, the insulator 111 may have a stack of hafnium oxide and silicon oxynitride. The insulator 111 may also have a three-layer structure, for example, with hafnium oxide sandwiched between two layers of silicon oxynitride. Furthermore, the insulator 111 may also have a three-layer structure, for example, with silicon oxynitride sandwiched between two layers of hafnium oxide.

[0223] Next, a conductor 112 is formed along the surface of the insulator 111 (see Figure 29B). The conductor 112 is processed in subsequent processes, thereby serving as the source and / or drain of the transistor WTr and / or the transistor RTr, as the gate of the transistor RTr, and as an electrode in the capacitor Cs.

[0224] The conductor 112 is preferably made of a material with high conductivity. Examples of preferred conductors 112 include nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum. In one embodiment of the invention, a nitride containing tantalum is particularly preferred. Furthermore, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may also be used, for example. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen.

[0225] Especially when using an oxide semiconductor as the semiconductor, the conductor 112 is preferably a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen. In this case, the conductor 112 is preferably made of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide.

[0226] For example, in the case where the conductor 112 has a stack of multiple layers, a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen can be used in the layer on the insulator 111 side, and a conductive material that is not easily oxidized or a material that maintains conductivity even when absorbing oxygen can be used in the layer on the semiconductor 113 side.

[0227] Next, a semiconductor 113 is formed along the surface of the conductor 112 (see Figure 30A). In this embodiment, an oxide semiconductor with an In:Ga:Zn ratio of 1:3:4 or approximately [atomic number ratio] is used as the semiconductor 113. Note that "approximate composition" includes a range of ±30% of the desired atomic number ratio.

[0228] Furthermore, as the semiconductor material for semiconductor 113, for example, metal oxides with compositions of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1 and similar compositions can be used.

[0229] Next, semiconductor 114 is formed along the surface of semiconductor 113 (see Figure 30B). In this embodiment, an oxide semiconductor with an In:Ga:Zn ratio of 4:2:3 or approximately is used as semiconductor 114.

[0230] Furthermore, as the semiconductor material for semiconductor 114, metal oxides having compositions of In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3 and similar compositions can be used. Additionally, metal oxides having compositions of In:Zn=5:1, or In:Zn=10:1 and similar compositions can also be used as the semiconductor material for semiconductor 114. Furthermore, indium oxide can also be used for semiconductor 114.

[0231] As the semiconductor material for the semiconductor 121 to be formed later, metal oxides with compositions of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2 or In:Ga:Zn=1:1:1 and similar compositions may also be used.

[0232] When using oxide semiconductors as semiconductor 121 and semiconductor 114, semiconductor 121 and semiconductor 114 preferably contain the same metal element. More preferably, they contain multiple identical metal elements. Furthermore, semiconductor 121 and semiconductor 114 preferably contain multiple identical metal elements, and the atomic ratio of these multiple metal elements is not the same.

[0233] For example, when semiconductors 121 and 114 use an In-M-Zn oxide comprising indium, element M, and zinc, the number of atoms of element M in the metal elements contained in semiconductor 121 is preferably greater than the number of atoms of element M in the metal elements contained in semiconductor 114. Furthermore, the number of atoms of element M relative to In in semiconductor 121 is preferably greater than the number of atoms of element M relative to In in semiconductor 114. Additionally, the number of atoms of In relative to element M in semiconductor 114 is preferably greater than the number of atoms of In relative to element M in semiconductor 121.

[0234] Preferably, the conduction band bottom energy of semiconductor 121 is higher than that of semiconductor 114. In other words, the electron affinity of semiconductor 121 is preferably lower than that of semiconductor 114.

[0235] Here, at the junction of semiconductor 121 and semiconductor 114, the energy level of the conduction band bottom changes gradually. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of semiconductor 121 and semiconductor 114 changing continuously or continuously. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface of semiconductor 121 and semiconductor 114.

[0236] Specifically, by including common elements (as the main components) in semiconductors 121 and 114 except for oxygen, a mixed layer with low defect state density can be formed. For example, when semiconductor 114 is In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide as semiconductor 121.

[0237] At this point, the primary pathway for carriers is through semiconductor 114. By equipping semiconductor 121 with the aforementioned structure, the defect state density at the interface between semiconductor 121 and semiconductor 114 can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, thereby increasing the on-state current of transistor WTr.

[0238] Furthermore, by providing semiconductor 121, impurity diffusion from semiconductor 121 to semiconductor 114 can be suppressed. The thickness of semiconductor 121 can be 1 nm or more and 10 nm or less, or 1 nm or more and 5 nm or less.

[0239] Furthermore, as shown in FIG16A, in the case where the semiconductor 114 is a stack of semiconductor 114a and semiconductor 114b, semiconductor 114b may have the same structure as semiconductor 114, and semiconductor 114a may have the same structure as semiconductor 121.

[0240] For example, as semiconductor 114a, an oxide semiconductor with an In:Ga:Zn ratio of 1:3:4 or similar can also be used. The thickness of semiconductor 114a can be 1 nm or more and 10 nm or more and 5 nm or less. Furthermore, as semiconductor 114b, an oxide semiconductor with an In:Ga:Zn ratio of 4:2:3 or similar can also be used. As described above, as semiconductor 114b, an oxide semiconductor with an In:Ga:Zn ratio of 5:1:3 or similar can also be used. The thickness of semiconductor 114b can be 5 nm or more and 20 nm or more and 5 nm or more and 15 nm or less.

[0241] By employing the above structure, the energy level of the conduction band bottom changes smoothly at the junction of semiconductor 121 and semiconductor 114b and at the junction of semiconductor 114b and semiconductor 114a. Furthermore, a mixed layer with low defect state density can be formed at the interface between semiconductor 121 and semiconductor 114b and at the interface between semiconductor 114b and semiconductor 114a.

[0242] By arranging semiconductors 121 and 114a in a manner that clamps semiconductor 114b, the influence of interface scattering on carrier conduction can be reduced, thereby increasing the on-state current of the transistor.

[0243] Furthermore, by providing semiconductor 114a, the diffusion of impurities from semiconductor 114a to semiconductor 114b can be suppressed.

[0244] Furthermore, in the fabrication process of the memory cell, the heat treatment is preferably performed with the surface of the semiconductor 114 exposed. This heat treatment is preferably performed at a temperature of 100°C or higher and 600°C or lower, more preferably at 350°C or higher and 550°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the semiconductor 114, thereby reducing oxygen vacancies (Vo). The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to fill the detached oxygen, in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. Alternatively, the heat treatment can be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas, and then continuously in a nitrogen or inert gas atmosphere.

[0245] Furthermore, by supplying oxygen to the semiconductor 114 (oxidation treatment), the supplied oxygen can fill the oxygen vacancies in the semiconductor 114, in other words, it can promote the reaction "Vo + O → null". Moreover, the hydrogen remaining in the semiconductor 114 reacts with the supplied oxygen to remove the hydrogen in the form of H2O (dehydration). Thus, the recombination of hydrogen and oxygen vacancies remaining in the semiconductor 114 to form VoH can be suppressed.

[0246] Furthermore, oxidation treatment can be performed by microwave treatment in an oxygen-containing atmosphere. In this case, the semiconductor 114 is irradiated with microwaves, RF, or other high-frequency radiation, oxygen plasma, oxygen free radicals, etc. Microwave treatment is preferably performed using a microwave processing apparatus that includes a power supply for generating high-density plasma using microwaves. The microwave processing apparatus may also include a power supply that applies RF to one side of the substrate. By using high-density plasma, high-density oxygen free radicals can be generated. Furthermore, by applying RF to one side of the substrate (not shown), oxygen ions generated by the high-density plasma can be efficiently introduced into the opening 131. Furthermore, the above microwave treatment is preferably performed under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. An oxygen flow rate ratio of O2 / (O2+Ar) of 50% or less is used, preferably 10% to 30% or less. Furthermore, the processing temperature is 750°C or less, preferably 500°C or less, for example, around 400°C. In addition, heating can be performed continuously after microwave treatment without exposure to air.

[0247] By using plasma, microwaves, or other methods, the VoH in semiconductor 114 can be separated, thus removing hydrogen (H) from semiconductor 114. In other words, the reactions "VoH→H+Vo" and "Vo+O→null" occur in semiconductor 114, reducing the hydrogen concentration contained in semiconductor 114. Therefore, oxygen vacancies and VoH in semiconductor 114 can be reduced, thereby lowering the carrier concentration.

[0248] Next, an insulator 115 is formed along the surface of the semiconductor 114 (see Figure 31A). When using an oxide semiconductor as the semiconductor 114, silicon oxide, silicon oxynitride, etc., can be appropriately used as the insulator 115. By providing an oxygen-containing insulator in contact with the semiconductor 114, oxygen vacancies in the semiconductor 114 can be reduced, thereby improving the reliability of the transistor.

[0249] Specifically, the insulator 115 is preferably an oxide material that undergoes partial oxygen removal upon heating, i.e., an insulator material with excess oxygen regions. The oxide material undergoing oxygen removal upon heating refers to an oxide film in which the amount of oxygen molecules removed during TDS analysis is 1.0 × 10¹⁸ molecules / cm³ or more, preferably 1.0 × 10¹⁹ molecules / cm³ or more, further preferably 2.0 × 10¹⁹ molecules / cm³ or more, or 3.0 × 10²⁰ molecules / cm³ or more. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower. The thickness of the insulator 115 can be 3 nm or higher and 15 nm or lower, or 3 nm or higher and 10 nm or lower.

[0250] Alternatively, the above-mentioned oxidation treatment can be performed after the insulator 115 is formed.

[0251] When using oxide semiconductors as semiconductors 116 and 114, insulator 115 is preferably an insulator having a region containing oxygen that is removed by heating. Furthermore, insulator 115 may also have a stacked structure of multiple insulators. For example, when using oxide semiconductors as semiconductors 116 and 114, insulator 115 may also have a three-layer structure of silicon oxide or silicon oxynitride, hafnium oxide or aluminum oxide, and silicon oxide or silicon oxynitride. That is, it may also have a structure consisting of two layers of silicon oxide or silicon oxynitride sandwiching a layer of hafnium oxide or aluminum oxide. Furthermore, insulator 115 may have a two-layer stacked structure or a stacked structure of four or more layers.

[0252] Next, a semiconductor 116 is formed along the surface of the insulator 115 (see Figure 31B). In this embodiment, an oxide semiconductor with an In:Ga:Zn ratio of 4:2:3 or approximately is used as the semiconductor 116.

[0253] Furthermore, as the semiconductor material for semiconductor 116, metal oxides having compositions of In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3 and similar compositions can be used. Additionally, metal oxides having compositions of In:Zn=5:1, or In:Zn=10:1 and similar compositions can also be used as the semiconductor material for semiconductor 116. Furthermore, indium oxide can also be used for semiconductor 116.

[0254] When using an oxide semiconductor as semiconductor 116, an oxidation process can be performed after semiconductor 116 is formed.

[0255] When using a Si transistor as the transistor RTr, a silicon-formed semiconductor 116 can be used.

[0256] Furthermore, as shown in Figures 18A and 18B, when the semiconductor 116 is a stack of semiconductors 116a, 116b and 116c, semiconductors 116a and 116c can have the same structure as semiconductor 114a, and semiconductor 116b can have the same structure as semiconductor 114b.

[0257] Next, an insulator 117 is formed along the surface of the semiconductor 116 (see Figure 32A). The insulator 117 can be formed using the same material and method as the insulator 115. Alternatively, an oxidation process can be performed after the insulator 117 is formed.

[0258] Insulator 117 may also have a stacked structure of multiple insulators. When using an oxide semiconductor as semiconductor 116, among the multiple insulators constituting insulator 117, the insulator in contact with semiconductor 116 is preferably an insulator having a region containing oxygen that is removed by heating. Furthermore, the insulator in contact with conductor 118 is preferably an insulator that has the aforementioned function of suppressing oxygen permeation. For example, among the multiple insulators constituting insulator 117, the insulator in contact with semiconductor 116 can be silicon oxide or silicon oxynitride. Furthermore, among the multiple insulators constituting insulator 117, the insulator in contact with conductor 118 can be hafnium oxide or aluminum oxide.

[0259] Furthermore, for example, insulator 117 may also have a stack of silicon oxide or silicon oxynitride, aluminum oxide, and silicon nitride. Moreover, when silicon nitride is used in insulator 117, it is preferable to use silicon nitride with a low hydrogen content.

[0260] Next, after forming the insulator 117, the conductor 118 is formed (see Figure 32B). In this embodiment, tungsten is used as the conductor 118. The conductor 118 may also have a stacked structure of multiple conductors. Among the multiple conductors constituting the conductor 118, the conductor in contact with the insulator 117 is preferably made of a conductive material that is not easily oxidized. For example, in the conductor 118, the conductor in contact with the insulator 117 may be titanium nitride. For example, the conductor 118 may have a stack of titanium nitride and tungsten.

[0261] Insulator 111, conductor 112, semiconductor 113, semiconductor 114 (semiconductor 114a, semiconductor 114b), insulator 115, semiconductor 116 (semiconductor 116a, semiconductor 116b, semiconductor 116c), insulator 117 and conductor 118 can be continuously formed by CVD (MOCVD, etc.) or ALD.

[0262] Following the steps described above, a structure 130a is formed within the opening 131. Next, a portion of the laminate 140 is removed from the region that does not overlap with the structure 130a when viewed from the Z direction, to form region 132 (see Figure 33A). Region 132 can be formed using the same method as the opening 131.

[0263] Next, the sacrificial layer 141 is removed (see Figure 33B). To remove the sacrificial layer 141, one or both of dry etching and wet etching methods can be used.

[0264] Next, the insulator 111, conductor 112, and semiconductor 113 overlapping the area where the sacrificial layer 141 was removed are removed to expose a portion of the semiconductor 114 (see Figure 34A). To remove the insulator 111, conductor 112, and semiconductor 113, one or both dry etching and wet etching methods can be used. Furthermore, the etching method and etching conditions can be appropriately changed depending on the type of material being removed. Alternatively, the removal of the sacrificial layer 141 and the removal of the insulator 111, conductor 112, and semiconductor 113 can be performed continuously. Furthermore, the formation of region 132 can be performed continuously until the removal of the semiconductor 113. Thus, structure 130 is formed.

[0265] Then, oxidation treatment can also be performed. For example, microwave treatment can be performed in an atmosphere containing oxygen 10. In this case, oxygen 10 is supplied from region 132, but oxygen 10 can also be supplied via the terminal extraction section shown in FIG34B. Furthermore, FIG34B is a perspective view of the laminate 140 near the terminal extraction section.

[0266] Next, a semiconductor 121 is formed along the surfaces of the insulator 101, conductor 103, insulator 111, conductor 112, semiconductor 113, and semiconductor 114 exposed due to the formation region 132 (see Figure 35A). Alternatively, an oxidation process may be performed after the semiconductor 121 is formed.

[0267] Next, an insulator 122 is formed along the surface of the semiconductor 121 (see Figure 35A). Alternatively, an oxidation process may be performed after the insulator 122 is formed. The insulator 122 can be formed of the same material as the insulator 115.

[0268] Furthermore, the insulator 122 may also have a stacked structure of multiple insulators. When an oxide semiconductor is used as the semiconductor 121, among the multiple insulators constituting the insulator 122, the insulator in contact with the semiconductor 121 is preferably the insulator described above that has a region containing oxygen that is removed by heating. Furthermore, the insulator in contact with the conductor 102 is preferably the insulator described above that has the function of suppressing oxygen permeation. For example, among the multiple insulators constituting the insulator 122, the insulator in contact with the semiconductor 121 can be silicon oxide or silicon oxynitride. Furthermore, among the multiple insulators constituting the insulator 122, the insulator in contact with the conductor 102 can be hafnium oxide.

[0269] Furthermore, for example, the insulator 122 may also have a stack of silicon oxide or silicon oxynitride, aluminum oxide, and silicon nitride. Moreover, when silicon nitride is used in the insulator 122, it is preferable to use silicon nitride with a low hydrogen content.

[0270] Next, a conductor 102 is formed along the surface of the insulator 122 (see Figure 35B). In this embodiment, the conductor 102 is a single layer, but it may also be a stack of multiple layers.

[0271] For example, as shown in Figures 18A and 18B, in the case where the conductor 102 is a stack of conductors 102f and 102s, the conductor 102f that contacts the insulator 122 is preferably made of a conductive material that is not easily oxidized. For example, titanium nitride can be used for conductor 102f, and tungsten can be used for conductor 102s.

[0272] Next, a portion of the conductor 102 is removed to expose a portion of the insulator 122 (see Figure 36A).

[0273] Next, an insulator 123 is formed along a portion of the exposed insulator 122 and the surface of the conductor 102 (see Figure 36B). Preferably, the insulator 123 is an insulating material that inhibits the permeation of impurities such as water and hydrogen. For example, alumina can be used as the insulator 123.

[0274] Furthermore, the insulator 123 may have a stacked structure of multiple insulators. For example, the insulator 123 may have a stack of hafnium oxide and silicon oxynitride. Among the multiple insulators constituting the insulator 123, the insulator in contact with the conductor 102 may be an insulator with the function of suppressing oxygen permeation as described above.

[0275] The memory unit 100 can be manufactured through the above steps.

[0276] Furthermore, as shown in Figures 21 to 22B, when the memory cell 100 is divided into multiple memory cells, a slit (not shown) is then formed to divide the memory cell 100 into multiple memory cells. After forming the slit, an insulator 124 may be provided within the slit. The insulator 124 may be formed of the same material as the insulator 123.

[0277] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0278] Implementation Method 2 In this embodiment, examples of the circuit structure and operation method of a semiconductor device 300 including multiple memory strings 200 are described with reference to the drawings.

[0279] <Circuit Structure Example> The circuit structure of the semiconductor device 300 will be described with reference to FIG37. The semiconductor device 300 includes m memory strings 200. In this embodiment, the memory string 200[1], the memory string 200[m] (m is an integer of 1 or more), and the memory string 200[j] (j is an integer of 1 or more and less than m) are respectively used to represent the first memory string 200, the m-th memory string 200, and the j-th memory string 200.

[0280] Furthermore, the memory string 200 includes n memory cells 100. Figure 37 shows a memory cell 100 having the circuit structure shown in Figure 4A, but a memory cell 100 having the circuit structure shown in Figures 4B, 4C, 5A, and 5B can also be used. In this embodiment, the memory cell 100 included in the j-th memory string 200 is referred to as memory cell 100[k,j].

[0281] The semiconductor device 300 shown in Figure 37 includes n wirings WWL, n wirings RWL, m wirings WBL, m wirings RBL, and m wirings BGL. In this embodiment, the k-th wiring WWL[k] and wiring RWL[k] are respectively shown. Furthermore, the j-th wirings WBL, RBL, and BGL are respectively shown as wiring WBL[j], wiring RBL[j], and wiring BGL[j].

[0282] Wiring WWL[1] is electrically connected to the gate (conductor 102) of the transistor WTr included in each of memory cells 100[1,1] to 100[1,m]. Wiring WWL[k] is electrically connected to the gate (conductor 102) of the transistor WTr included in each of memory cells 100[k,1] to 100[k,m]. Wiring WWL[n] is electrically connected to the gate (conductor 102) of the transistor WTr included in each of memory cells 100[n,1] to 100[n,m].

[0283] Wiring RWL[1] is electrically connected to capacitor Cs included in each of memory cells 100[1,1] to 100[1,m]. Wiring RWL[k] is electrically connected to capacitor Cs included in each of memory cells 100[k,1] to 100[k,m]. Wiring RWL[n] is electrically connected to capacitor Cs included in each of memory cells 100[n,1] to 100[n,m]. Wiring RWL is connected to the gate (conductor 112) of transistor RTr via capacitor Cs.

[0284] Wiring WBL[1] is electrically connected to one of the source and drain (conductor 112) of the transistor WTR included in memory cell 100[1,1]. Wiring WBL[j] is electrically connected to one of the source and drain (conductor 112) of the transistor WTR included in memory cell 100[1,j]. Wiring WBL[m] is electrically connected to one of the source and drain (conductor 112) of the transistor WTR included in memory cell 100[1,m].

[0285] Wiring RBL[1] is electrically connected to one of the source and drain (semiconductor 116) of the transistor RTR included in memory cell 100[1,1]. Wiring RBL[j] is electrically connected to one of the source and drain (semiconductor 116) of the transistor RTR included in memory cell 100[1,j]. Wiring RBL[m] is electrically connected to one of the source and drain (semiconductor 116) of the transistor RTR included in memory cell 100[1,m].

[0286] Wiring BGL[1] is electrically connected to the back gate (conductor 118) of the transistor RTR included in each of memory cells 100[1,1] to 100[n,1]. Wiring BGL[j] is electrically connected to the back gate (conductor 118) of the transistor RTR included in each of memory cells 100[1,j] to 100[n,j]. Wiring BGL[m] is electrically connected to the back gate (conductor 118) of the transistor RTR included in each of memory cells 100[1,m] to 100[n,m].

[0287] The WWL wire is used as the write word line, the RWL wire is used as the read word line, the WBL wire is used as the write bit line, and the RBL wire is used as the read bit line.

[0288] Furthermore, in the memory string 200[1] shown in FIG37, node N1[1] indicates another region electrically connected to the source and drain of the transistor RTR included in the memory cell 100[1,1], and node N2[1] indicates one of the source and drain of the transistor RTR included in the memory cell 100[n,1]. Similarly, nodes N1[j] and N2[j] of the memory string 200[j] are shown respectively. Furthermore, nodes N1[m] and N2[m] of the memory string 200[m] are shown respectively.

[0289] <Example of work method> Next, an example of the operation of the semiconductor device 300 shown in FIG37 will be described. In this embodiment, an example of writing and reading data to the memory cells 100 included in the memory string 200 [1] will be described.

[0290] Furthermore, in the following explanation, "Low potential" and "High potential" do not refer to specific potentials, and their specific potentials may vary depending on each wiring. For example, the low potential and high potential applied to the WWL of a wiring may be different from the low potential and high potential applied to the RWL of a wiring.

[0291] Furthermore, in this example of the working method, the wiring BGL is pre-applied with a potential within the normal operating range of the transistor RTR and transistor WTR.

[0292] Figure 38A is a timing diagram illustrating an example of writing data to memory string 200[1], and Figure 38B is a timing diagram illustrating an example of reading data from memory string 200[1]. Each timing diagram in Figures 38A and 38B shows the changes in the potential magnitudes of wiring WWL[1], wiring WWL[2], wiring WWL[n-1], wiring WWL[n], wiring RWL[1], wiring RWL[2] or wiring RWL[n-1], wiring RWL[n], node N1[1], and node N2[1]. In addition, wiring WBL[1] shows the data supplied to wiring WBL[1].

[0293] Furthermore, Figure 38A shows an example of writing data D[1] to data D[n] into memory cells 100[1,1] to memory cells 100[n,1], respectively. Data D[1] to data D[n] can be two-valued or multi-valued. In addition, data D[1] to data D[n] are supplied from wiring WBL[1].

[0294] Data is written to memory string 200[1] sequentially from memory cell 100[n,1] to memory cell 100[1,1]. When data is written to memory cell 100[2,1] after data is written to memory cell 100[1,1], the data stored in memory cell 100[1,1] will be lost during the writing phase of memory cell 100[2,1]. Therefore, it is necessary to read out the data written to memory cell 100[1,1] in advance and store it in another part.

[0295] In the circuit structure of memory string 200, when data is written to memory cell 100[k,1], in order to prevent the data stored in memory cells 100[n,1] to 100[k+1,1] from being overwritten, a low-level potential is supplied to wiring WWL[n] to wiring WWL[k+1], so that the transistor WTr of each of memory cells 100[n,1] to 100[k+1,1] is turned off. Thus, the data stored in memory cells 100[n,1] to 100[k+1,1] can be preserved.

[0296] Furthermore, when data is written to memory cell 100[k,1], since data is supplied from wiring WBL[1], a high-level potential is supplied to wirings WWL[1] to WWL[k], so that the transistor WTr of each of memory cells 100[1,1] to 100[k,1] is fully turned on. Thus, data can be stored at the storage node of memory cell 100[k,1].

[0297] Furthermore, when writing data to memory cells 100[1,1] to 100[n,1], since the wiring RBL[1] can be controlled independently, it is not necessary to set the wiring RBL[1] to a specific potential. For example, the potential of the wiring RBL[1] can be set to a low-level potential. In addition, the potentials of nodes N1[1] and N2[1] can be set to low-level potentials.

[0298] Writing Work Considering the above situation, the writing operation example is described with reference to the timing diagram of Figure 38A. During the period T10, the potentials of the wiring WWL[1] to wiring WWL[n], wiring RWL[1] to wiring RWL[n], wiring WBL[1], node N1[1] and node N2[1] are low-level potentials.

[0299] During T11, wiring WWL[1] to wiring WWL[n] is supplied with a high-level potential. Thus, the transistor WTr of each of memory cells 100[1,1] to 100[n,1] is fully turned on. Furthermore, wiring WBL[1] is supplied with data D[n]. Because the transistor WTr of each of memory cells 100[1,1] to 100[n,1] is fully turned on, data D[n] is supplied to the storage node of memory cell 100[n,1].

[0300] During period T12, wiring WWL[n] is supplied with a low-level potential, and wirings WWL[n-1] to WWL[1] are continuously supplied with a high-level potential. Thus, the transistor WTr of memory cell 100[n,1] is turned off, and the transistor WTr of each of memory cells 100[n-1,1] to 100[1,1] remains on. Furthermore, wiring WBL[1] is supplied with data D[n-1]. Because the transistor WTr of each of memory cells 100[n-1,1] to 100[1,1] is fully on, data D[n-1] is supplied to the storage node of memory cell 100[n-1,1]. Furthermore, the transistor WTr of memory cell 100[n,1] is turned off, thereby maintaining the data D[n] written to memory cell 100[n,1] during period T11.

[0301] During period T13, similar to periods T11 and T12, memory units 100[n-2,1] to 100[2,1] are sequentially written to data D[n-2] to data D[2].

[0302] Specifically, the transistors WTr of memory cells 100[n,1] to 100[k+1,1] that have been written with data are turned off, while the transistors WTr of memory cells 100[k,1] to 100[1,1] that have not been written with data are fully turned on. Data D[k] is supplied from the wiring WBL and written to the storage node of memory cell 100[k,1]. After writing data D[k] to memory cell 100[k,1], the transistors WTr of memory cell 100[k,1] are turned off. Then, the operation of supplying data D[k-1] from the wiring WBL[1] and writing it to the storage node of memory cell 100[k-1,1] is performed.

[0303] Furthermore, the write operation when k is 1 is explained with reference to period T14. During period T14, wiring WWL[n] to wiring WWL[2] is supplied with a low-level potential, and wiring WWL[1] is continuously supplied with a high-level potential. As a result, the transistors WTr of memory cells 100[n,1] to 100[2,1] are turned off, and the transistors WTr of memory cell 100[1,1] remain on. In addition, data D[1] is supplied to wiring WBL[1]. Because the transistors WTr of memory cell 100[1,1] are fully on, data D[1] is written to the storage node of memory cell 100[1,1]. In addition, because the transistors WTr of memory cells 100[n,1] to 100[2,1] are turned off, the data D[n] to D[2] stored in each of memory cells 100[n,1] to 100[2,1] can be kept on.

[0304] Through the above work, data can be written to memory cells 100[1,1] to 100[n,1].

[0305] In this embodiment, the writing operation is described with reference to memory string 200[1]. However, in the circuit structure of semiconductor device 300, when wiring WWL[k] is supplied with a high level potential, all transistors WTr electrically connected to wiring WWL[k] become on. Thus, in addition to memory string 200[1], data writing to memory string 200[2] to memory string 200[m] is performed simultaneously.

[0306] The memory unit 100 shown in this embodiment is OS memory. Therefore, the semiconductor device 300 including the memory unit 100 does not require deletion before data rewriting and can achieve high-speed writing.

[0307] Furthermore, when writing data (rewriting) to a memory cell 100 that is close to the wiring WBL, the data writing operation for memory cells 100 that are farther away from the wiring WBL compared to that memory cell 100 can be omitted. For example, when writing data (rewriting) to memory cell 100[1,1], the data writing operation for memory cells 100[2,1] to memory cells 100[n,1] can be omitted. Furthermore, when writing data to memory cell 100[2,1], the data writing operation for memory cells 100[3,1] to memory cells 100[n,1] can be omitted.

[0308] By storing frequently rewritten data in memory cells 100 located close to the wiring WBL, the time required for data writing (rewriting) can be shortened. In other words, the data writing (rewriting) speed can be increased.

[0309] By doing so, OS NAND type (including 3D OS NAND type) memory devices can function like RAM.

[0310] Reading Out Your Job Figure 38B shows an example of reading data D[1] to D[n] from memory cell 100[1,1] to memory cell 100[n,1]. In this case, to maintain the data stored in each memory cell 100, the transistor WTr needs to be in the off state. Therefore, during the operation of reading data from memory cell 100[1,1] to memory cell 100[n,1], the potential of wiring WWL[1] to wiring WWL[n] is a low-level potential.

[0311] In the circuit structure of the semiconductor device 300 shown in Figure 37, when data from a specific memory cell 100 is read, the transistor RTr of the memory cell 100 to be read is operated in the saturation region while the transistors RTr of the other memory cells 100 are fully turned on. That is, the magnitude of the current flowing between the source and drain of the transistor RTr of the memory cell 100 to be read depends on the voltage between the source and drain and the data stored in the memory cell 100 to be read.

[0312] For example, consider the case of reading the data stored in memory cell 100[k,1]. During the readout operation, in order to fully turn on the transistor RTr of each of memory cells 100[1,1] to 100[n,1] other than memory cell 100[k,1], a high-level potential is supplied to wirings RWL[1] to RWL[n] other than wiring RWL[k].

[0313] On the other hand, in order for the transistor RTr of memory cell 100[k,1] to switch between on and off states according to the data stored in memory cell 100[k,1], the potential of wiring RWL[k] needs to be set to the same potential as when writing data to memory cell 100[k,1]. Here, it is assumed that the potential of wiring RWL[k] is a low-level potential during write and read operations.

[0314] For example, +3V and 0V potentials are supplied to nodes N1[1] and N2[1], respectively. Furthermore, after making node N2[1] float, the potential of node N2[1] is measured. When the potentials of wirings RWL[1] to RWL[n] other than wiring RWL[k] are set to high level potentials, the transistor RTr of each of the memory cells 100[1,1] to 100[n,1] other than memory cells 100[k,1] is fully turned on.

[0315] On the other hand, the voltage between the source and drain of the transistor RTR in the memory cell 100[k,1] depends on the gate potential of the transistor RTR and the potential of node N1[1], and thus the potential of node N2[1] depends on the data stored in the storage node of the memory cell 100[k,1].

[0316] Through the above work, the data stored in memory unit 100[k,1] can be read.

[0317] Considering the above, the readout operation example is described with reference to the timing diagram of FIG38B. During T20, the potentials of wiring WWL[1] to wiring WWL[n], wiring RWL[1] to wiring RWL[n], wiring WBL[1], node N1[1], and node N2[1] are all low-level potentials. In particular, node N2[1] is in a floating state. In addition, the storage nodes of memory cells 100[1,1] to memory cells 100[n,1] respectively hold data D[1] to data D[n].

[0318] During T21, wiring RWL[1] is supplied with a low-level potential, and wiring RWL[2] to wiring RWL[n] are supplied with a high-level potential. Thus, the transistor RTr of each of memory cells 100[2,1] to 100[n,1] is fully turned on. Furthermore, the transistor RTr of memory cell 100[1,1] switches between on and off states according to the data D[1] stored in the memory node of memory cell 100[1,1].

[0319] Furthermore, the wiring RBL[1] is supplied with a potential VR. Thus, the potential of node N1[1] becomes VR, and the potential of node N2[1] depends on the potential VR of node N1[1] and the data stored in the storage node of memory unit 100[1,1]. Here, the potential of node N2[1] is VD[1]. By measuring the potential VD[1] of node N2[1], the data D[1] stored in the storage node of memory unit 100[1,1] can be read.

[0320] During period T22, wiring RWL[1] to wiring RWL[n] is supplied with a low-level potential. Additionally, node N2[1] is supplied with a low-level potential, and then node N2[1] becomes floating. That is, during period T22, the potentials of wiring RWL[1] to wiring RWL[n] and node N2[1] become the same as during period T20. Furthermore, wiring RBL[1] can also be continuously supplied with potential VR, or it can be supplied with a low-level potential. In this example, wiring RBL[1] is continuously supplied with potential VR after period T21. Therefore, node N1[1] is continuously supplied with potential VR.

[0321] During T23, wiring RWL[2] is supplied with a low-level potential, and wiring RWL[1], wiring RWL[3] to wiring RWL[n] are supplied with a high-level potential. Thus, the transistor RTr of each of memory cells 100[1,1], 100[3,1] to 100[n,1] is fully turned on. Furthermore, the transistor RTr of memory cell 100[2,1] switches between on and off states according to the data D[2] stored in the storage node of memory cell 100[2,1]. Additionally, wiring RBL[1] is supplied with a potential VR. Thus, the potential of node N2[1] depends on the potential VR of node N1[1] and the data stored in the storage node of memory cell 100[2,1]. Here, the potential of node N2[1] is VD[2]. By measuring the potential VD[2] of node N2[1], the data D[2] stored in the storage node of memory unit 100[2,1] can be read.

[0322] During period T24, similar to the reading operations during periods T22 and T23, data D[3] to data D[n-1] are read sequentially from memory unit 100[3,1] to memory unit 100[n-1,1].

[0323] Specifically, when data D[k] is read from memory cell 100[k,1], the potential of node N2[1] is made low-level and node N2[1] is made floating. Then, a high-level potential is supplied to wiring RWL[1] to wiring RWL[n] other than wiring RWL[k], so that the transistors RTr of memory cells 100[1,1] to memory cells 100[n,1] other than memory cell 100[k,1] are fully turned on, and thus the transistors RTr of memory cell 100[k,1] are turned on according to data D[k]. Next, by setting the potential of node N1[1] to VR, the potential of node N2[1] becomes the potential according to data D[k], and by measuring this potential, data D[k] can be read. In addition, after reading the data D[k] stored in memory cell 100[k,1], in order to prepare for the next read operation, a low-level potential is supplied to the wiring RWL[1] to the wiring RWL[n], and a low-level potential is supplied to node N2[1], and then node N2[1] becomes a floating state.

[0324] During period T25, wiring RWL[1] to wiring RWL[n] is supplied with a low-level potential. In addition, node N2[1] is supplied with a low-level potential, and then node N2[1] becomes a floating state. That is, during period T25, the potentials of wiring RWL[1] to wiring RWL[n] and node N2[1] become the same as those during period T20.

[0325] During T26, wiring RWL[n] is supplied with a low-level potential, and wiring RWL[1] to wiring RWL[n-1] are supplied with a high-level potential. Thus, the transistor RTr of each of memory cells 100[1,1] to 100[n-1,1] is fully turned on. Furthermore, the transistor RTr of memory cell 100[n,1] is turned on according to the data D[n] stored in the memory node of memory cell 100[n,1]. Additionally, wiring RBL[1] is continuously supplied with a potential VR. Thus, the potential of node N2[1] depends on the potential VR of node N1[1] and the data stored in the memory node of memory cell 100[n,1]. Here, the potential of node N2[1] is VD[n]. By measuring the potential VD[n] of node N2[1], the data D[n] stored in the memory node of memory cell 100[n,1] can be read.

[0326] Through the above work, the data stored in memory units 100[1,1] to 100[n,1] can be read.

[0327] In this embodiment, the read operation is described with reference to memory string 200[1]. However, in the circuit structure of semiconductor device 300, data is read from memory string 200[2] to memory string 200[m] simultaneously, in addition to memory string 200[1]. Furthermore, by turning off transistor WTr, data stored in the memory node can be prevented from being corrupted during data read operation. Thus, data included in any memory string 200 can be read.

[0328] <Examples of semiconductor device structures> The following describes a structural example of semiconductor device 300.

[0329] Figures 39A to 39C are examples of schematic diagrams showing a portion of a semiconductor device 300. Figure 39A is a perspective view of a portion of the semiconductor device, and Figure 39B is a top view of a portion of the semiconductor device. Furthermore, Figure 39C is a cross-sectional view corresponding to the dashed lines Z1-Z2 in Figure 39B.

[0330] The semiconductor device includes a structure with a wiring WL (wiring WWL or wiring RWL) and an insulator (the unshaded areas in Figures 39A to 39C) stacked together.

[0331] An opening is formed in the structure that extends through both the insulator and the wiring WL. Furthermore, to house the memory cell 100 in the region AR extending through the wiring WL, the opening is formed with an insulator, a conductor, and a semiconductor. The conductor serves as the source or drain electrode of the transistor included in the memory cell 100, and the semiconductor serves as a channel forming region for the transistor included in the memory cell 100. Alternatively, a conductor may not be formed, but a channel forming region and a low-resistance region may be formed in the semiconductor, with the low-resistance region used as the source or drain of the transistor.

[0332] In Figures 39A to 39C, the region where the opening, insulator, conductor, and semiconductor are formed is designated as region HL. Particularly in Figure 39A, region HL, located inside the structure, is indicated by a dashed line. Furthermore, if the transistor included in the memory cell 100 has a back gate, the conductor included in region HL can be used as wiring BGL for electrical connection to the back gate. That is, the memory string 200 is formed in region HL. Additionally, the memory string 200 is formed in region SA.

[0333] Furthermore, the area TM exposing the wiring WL is used as a connection terminal for supplying potential to the wiring WL. In other words, by electrically connecting the wiring WL to any wiring in the area TM, a potential can be supplied to the gate of the transistor included in the memory cell 100. Note that the wiring WL corresponds to conductor 102 or conductor 103 in FIG. 1A.

[0334] Note that the shape of region TM is not limited to the structural examples shown in Figures 39A to 39C. As one embodiment of the present invention, the semiconductor device 300, for example, as shown in Figures 40A to 40C, may have an insulator formed on region TM, an opening formed in the insulator, and a conductor PG formed in such a way that the opening is filled.

[0335] Figure 40A is a perspective view of a portion of the semiconductor device, and Figure 40B is a top view of a portion of the semiconductor device. Furthermore, Figure 40C is a cross-sectional view corresponding to the dashed lines Z1-Z2 in Figure 40B. Additionally, wiring ER is formed on the conductor PG, thereby electrically connecting wiring ER to wiring WL. In Figure 40A, the conductor PG disposed inside the structure is indicated by dashed lines, and the dashed lines of region HL are omitted.

[0336] <Example of connection with peripheral circuits> In a semiconductor device 300 according to one embodiment of the present invention, peripheral circuitry of a memory cell array, such as a readout circuit and a precharge circuit, can be formed on its lower layer. In this case, Si transistors are formed on a silicon substrate or the like to constitute this peripheral circuitry, and then the semiconductor device 300 according to one embodiment of the present invention is formed on this peripheral circuitry. FIG41A is a cross-sectional view of a semiconductor device 300 according to one embodiment of the present invention with peripheral circuitry composed of planar Si transistors and formed on its upper layer. Furthermore, FIG42A is a cross-sectional view of a semiconductor device 300 according to one embodiment of the present invention with peripheral circuitry composed of FIN-type Si transistors and formed on its upper layer.

[0337] In Figures 41A and 42A, Si transistors constituting peripheral circuits are formed on substrate 1700. A component separation layer 1701 is formed between the plurality of Si transistors. Conductors 1712 are formed as the source and drain electrodes of the Si transistors. Conductors 1730 are formed and connected to other Si transistors or conductors 1712 (not shown) in a manner that extends in the channel width direction.

[0338] As substrate 1700, the substrate shown in the above embodiment can be used. For example, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon and germanium, an SOI (Silicon on Insulator) substrate, etc. can be used.

[0339] Furthermore, the substrate 1700 can be made of, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminated film, or a paper or substrate film containing fibrous material. Additionally, a semiconductor element can be formed on one substrate and then transferred to another substrate. Figures 41A and 42A illustrate, as an example, the use of a single-crystal silicon wafer on substrate 1700.

[0340] Figures 41A and 42A show conductors 1221, 1222, 1223, and insulator 1202 disposed on memory string 200 in region SA. Conductor 1221 is electrically connected to the source or drain of transistor RTR located at the end of memory string 200.

[0341] Insulator 1202 covers conductor 1221. Conductor 1222 is embedded in insulator 1202 in the region overlapping with conductor 118. Conductor 1223 is disposed above insulator 1202, and is electrically connected to conductor 118 via conductor 1222.

[0342] Furthermore, in Figures 41A and 42A, an insulator 1203 is also provided to cover the conductor 1223, the insulator 1202, and the memory string 200. Preferably, the insulator 1203 is an insulator that suppresses the permeation of impurities such as hydrogen and oxygen. By using an insulator 1203 that suppresses the permeation of impurities such as hydrogen and oxygen, the diffusion of impurities from the outside (e.g., water molecules, hydrogen atoms, water molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, and NO2, etc.)) into the memory string 200 can be suppressed.

[0343] Here, the details of the Si transistor are explained. Figure 41A shows a cross-sectional view along the channel length direction of the planar Si transistor, and Figure 41B shows a cross-sectional view along the channel width direction of the planar Si transistor. The Si transistor includes a channel forming region 1793, a low-concentration impurity region 1794, and a high-concentration impurity region 1795 (which can also be simply referred to as the impurity region) disposed in the well 1792, a conductive region 1796 disposed in contact with the impurity region, a gate insulating film 1797 disposed on the channel forming region 1793, a gate electrode 1790 disposed on the gate insulating film 1797, a sidewall insulating layer 1798 disposed on the side of the gate electrode 1790, and a sidewall insulating layer 1799. In addition, the conductive region 1796 may also use metal silicides or the like.

[0344] Furthermore, Figure 42A shows a cross-sectional view of the FIN-type Si transistor along the channel length direction, and Figure 42B shows a cross-sectional view of the FIN-type Si transistor along the channel width direction. The channel forming region 1793 of the Si transistor shown in Figures 42A and 42B has a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along its side and top surfaces. Although this embodiment shows a case where a portion of the semiconductor substrate is processed to form the convex portion, the SOI substrate can also be processed to form a semiconductor layer with a convex shape. Note that the symbols in Figures 42A and 42B are the same as those in Figures 41A and 41B.

[0345] This embodiment can be implemented by appropriately combining it with other structures shown in this embodiment, etc.

[0346] Implementation Method 3 In this embodiment, a semiconductor device 400 including a semiconductor device according to one embodiment of the present invention is described. The semiconductor device 400 can be used as a memory device.

[0347] Figure 43 is a block diagram illustrating a structural example of a semiconductor device 400. The semiconductor device 400 shown in Figure 43 includes a driving circuit 410 and a memory array 420. The memory array 420 includes one or more memory cells 30. Figure 43 shows an example of a memory array 420 including multiple memory cells 30 configured in a matrix.

[0348] The drive circuit 410 includes PSW241 (power switch), PSW242 and peripheral circuit 415. The peripheral circuit 415 includes peripheral circuit 411, control circuit 412 and voltage generation circuit 428.

[0349] In the semiconductor device 400, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0350] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gate control signals. Furthermore, signals PON1 and PON2 can also be generated in control circuit 412.

[0351] The control circuit 412 is a logic circuit that controls the overall operation of the semiconductor device 400. For example, the control circuit 412 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 400 (e.g., write operation, read operation). Alternatively, the control circuit 412 generates control signals for the peripheral circuit 411 to execute the aforementioned operating mode.

[0352] The voltage generation circuit 428 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 428. For example, when the signal WAKE is given an H-level signal, the signal CLK is input to the voltage generation circuit 428, and the voltage generation circuit 428 generates a negative voltage.

[0353] Peripheral circuit 411 is used to write and read data from memory cell 30. Peripheral circuit 411 includes row decoder 441, column decoder 442, row driver 423, column driver 424, input circuit 425, output circuit 426, and sense amplifier 427.

[0354] Row decoder 441 and column decoder 442 are used to decode the ADDR signal. Row decoder 441 is used to specify the circuit to be accessed in a row, and column decoder 442 is used to specify the circuit to be accessed in a column. Row driver 423 is used to select the wiring WL specified by row decoder 441. Column driver 424 has the following functions: writing data to memory unit 30; reading data from memory unit 30; and storing the read data.

[0355] Input circuit 425 has the function of holding signal WDA. The data held in input circuit 425 is output to column driver 424. The output data of input circuit 425 is the data written to memory cell 30 (Din). The data read from memory cell 30 by column driver 424 (Dout) is output to output circuit 426. Output circuit 426 has the function of holding Dout. In addition, output circuit 426 has the function of outputting Dout to the outside of semiconductor device 400. The data signal output from output circuit 426 is signal RDA.

[0356] PSW241 controls the supply of VDD to the peripheral circuit 415. PSW242 controls the supply of VHM to the row driver 423. Here, the high supply voltage of the semiconductor device 400 is VDD, and the low supply voltage is GND (ground potential). Furthermore, VHM is a high supply voltage used to make the word line a high level, which is higher than VDD. The on / off state of PSW241 is controlled by signal PON1, and the on / off state of PSW242 is controlled by signal PON2. In Figure 43, the number of power domains supplied with VDD in the peripheral circuit 415 is one, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0357] Memory string 200 can be used as memory unit 30. Alternatively, memory units other than memory string 200 can also be used as memory unit 30. Examples of memory unit structures that can be applied to memory unit 30 are described below with reference to Figures 44A to 45B.

[0358] [DOSRAM] Figure 44A shows an example of the circuit structure of a DRAM-type memory cell. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 31 includes transistor M1 and capacitor CA. Transistor M1 includes a front gate (sometimes simply called the gate) and a back gate.

[0359] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0360] The BIL (Bit Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Civil Line) is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL.

[0361] Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0362] Data writing and reading are performed by applying a high level potential to the wiring WOL to turn on the transistor M1, thereby connecting the wiring BIL to the first terminal of the capacitor CA.

[0363] Furthermore, the memory cell that can be used in memory cell 30 is not limited to memory cell 31, and the circuit structure can be changed. For example, it can have the structure of memory cell 32 shown in FIG44B. In memory cell 32, the back gate of transistor M1 is connected to wiring WOL but not to wiring BGL. By adopting this structure, the same potential as the gate of transistor M1 can be applied to the back gate of transistor M1, thereby increasing the current flowing through transistor M1 when transistor M1 is in the on state.

[0364] Furthermore, for example, the memory cell that can be used in memory cell 30 can also be composed of a single-gate transistor, that is, a transistor M1 without a back gate. Figure 44C shows an example of the circuit structure of this memory cell. The memory cell 33 shown in Figure 44C has a structure in which the back gate has been removed from the transistor M1 of memory cell 31. In addition, by applying memory cell 33 to memory cell 30, the manufacturing process of memory cell 30 can be shortened compared with memory cell 31 and memory cell 32 because the transistor M1 does not have a back gate.

[0365] It is preferable to use an OS transistor for transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor for transistor M1, the leakage current of transistor M1 can be made very low. That is to say, the written data can be retained by transistor M1 for a long time, thereby reducing the update frequency of memory cells. In addition, the update operation of memory cells can be eliminated. Furthermore, since the leakage current is very low, multi-valued data or analog data can be retained for memory cells 31, 32, and 33.

[0366] [NOSRAM] Figure 44D shows an example of a circuit structure for a gain-cell type memory cell including two transistors and a capacitor. Memory cell 34 includes transistor M2, transistor M3, and capacitor CB. Transistor M2 includes a front gate and a back gate. In this specification, etc., a memory device including a gain-cell type memory cell that uses an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0367] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0368] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0369] Wiring BGL is used to apply a potential to the back gate of transistor M2. The critical voltage of transistor M2 can be controlled by applying any potential to wiring BGL.

[0370] Data writing is performed by applying a high-level potential to wiring WOL, turning on transistor M2 to connect wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL to turn on transistor M2, thereby storing the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0371] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0372] Furthermore, the memory unit that can be used in memory unit 30 is not limited to memory unit 34, and the circuit structure can be appropriately modified.

[0373] Furthermore, the memory cell that can be used in memory cell 30 can also have the structure of memory cell 35 shown in FIG. 44E. In memory cell 35, similar to the transistor M1 in memory cell 32 shown in FIG. 44B, the back gate of transistor M2 is connected to wiring WOL but not to wiring BGL. By adopting this structure, the same potential as the gate of transistor M2 can be applied to the back gate of transistor M2, thereby increasing the current flowing through transistor M2 when transistor M2 is in the on state.

[0374] Furthermore, for example, the memory cell that can be used in memory cell 30 can also be composed of a transistor M2 without a back gate. Figure 44F shows an example of the circuit structure of this memory cell. Memory cell 36 has a structure in which the back gate is removed from the transistor M2 of memory cell 34. In addition, by applying memory cell 36 to memory cell 30, the manufacturing process of memory cell 30 can be shortened compared to memory cell 34 and memory cell 35 because the transistor M2 does not have a back gate.

[0375] For example, a structure can be adopted in which the wiring WBL and wiring RBL are combined into a single wiring BIL. Figure 44G shows an example of the circuit structure of the memory cell in this case. In memory cell 37, the wiring WBL and wiring RBL of memory cell 34 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 37 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0376] Furthermore, the channel forming regions of transistors M2 and / or M3 may use oxide semiconductors containing at least one of indium, element M, and zinc. That is, transistors M2 and / or M3 are preferably OS transistors. In particular, the channel forming regions of transistors M2 and / or M3 are preferably oxide semiconductors containing indium, gallium, and zinc.

[0377] Because OS transistors have extremely low off-state current, using OS transistors as transistors M2 and / or M3 can result in very low leakage current for transistors M2 and / or M3. In particular, transistor M2 can retain written data for extended periods, thereby reducing the update frequency of memory cells. Furthermore, memory cell update operations can be eliminated. Moreover, due to the very low leakage current, multi-valued or analog data can be retained in memory cells 34, 35, 36, and 37.

[0378] The memory cells 34, 35, 36, and 37, which use OS transistors as transistor M2, are an implementation of NOSRAM.

[0379] Si transistors can also be used as transistor M3. The field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystallization state of silicon used in the semiconductor layer.

[0380] Furthermore, when an OS transistor is used as transistor M3, the memory cell can be constructed from a unipolar circuit.

[0381] Furthermore, Figure 45A shows a gain-type memory cell with three transistors and one capacitor. Memory cell 38 includes transistors M4, M5, and M6, and capacitor CC. Additionally, transistor M4 has a front gate and a back gate.

[0382] The first terminal of transistor M4 is connected to the first terminal of capacitor CC. The second terminal of transistor M4 is connected to wiring BIL. The gate of transistor M4 is connected to wiring WWL. The back gate of transistor M4 is electrically connected to wiring BGL. The second terminal of capacitor CC is electrically connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6. The gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL. The gate of transistor M6 is connected to wiring RWL.

[0383] The BIL (Bite Line) is used as the bit line, the WWL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line.

[0384] The wiring BGL is used to apply a potential to the back gate of transistor M4. By applying any potential to the wiring BGL, the threshold voltage of transistor M4 can be increased or decreased.

[0385] GNDL wiring is wiring that supplies low-level potentials.

[0386] Data writing is performed by applying a high-level potential to the wiring WWL, turning on transistor M4 to connect the wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to the wiring WWL, turning off transistor M4, thereby storing the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0387] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floated and applying a high-level potential to the wiring RWL. By making the wiring RWL high-level, transistor M6 becomes conductive, and the wiring BIL and the second terminal of transistor M5 become electrically connected. At this time, the second terminal of transistor M5 is supplied with the potential of the wiring BIL, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0388] Furthermore, the circuit structure of the memory cell that can be used in memory cell 30 can be appropriately modified. For example, like the transistor M1 in memory cell 32 shown in FIG. 44B and the transistor M2 in memory cell 35 shown in FIG. 44E, in memory cell 38, the back gate of transistor M4 is connected to wiring WOL but not to wiring BGL. By adopting this structure, the same potential as the gate of transistor M4 can be applied to the back gate of transistor M4, thereby increasing the current flowing through transistor M4 when transistor M4 is in the on state. Furthermore, for example, like the transistor M1 in memory cell 33 shown in FIG. 44C and the transistor M2 in memory cell 36 shown in FIG. 44F, the transistor M4 in memory cell 38 may also not have a back gate. By adopting this structure, the manufacturing process of the memory cell can be shortened because transistor M4 does not have a back gate.

[0389] Transistors M4 to M6 are preferably OS transistors. OS transistors have the characteristic of extremely low off-state current, thus, by using OS transistors for transistors M4 to M6, the leakage current of transistors M4 to M6 can be made very low. In particular, transistor M4 can retain written data for a longer period of time, thereby reducing the update frequency of the memory cells. In addition, the memory cell update operation can be eliminated.

[0390] The transistors M5 and M6 described in this embodiment can also be Si transistors. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on the crystal state of silicon used in the semiconductor layer.

[0391] Furthermore, when OS transistors are used as transistors M5 and M6, the memory unit can be constructed from unipolar circuits.

[0392] [OS-SRAM] Figure 45B shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification, the SRAM using an OS transistor is referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, the memory cell 39 shown in Figure 45B is an SRAM-type memory cell capable of backup.

[0393] Memory unit 39 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors M7 to M10 have a front gate and a back gate. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0394] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1, MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL, and its back gate is connected to wiring BGL1. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2, MS4, MS1, MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL, and its back gate is connected to wiring BGL2.

[0395] The second terminal of transistor MS1 is electrically connected to wiring VDL. The second terminal of transistor MS2 is electrically connected to wiring VDL. The second terminal of transistor MS3 is electrically connected to wiring GNDL. The second terminal of transistor MS4 is electrically connected to wiring GNDL.

[0396] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1. The gate of transistor M9 is connected to wiring BRL, and the back gate of transistor M9 is connected to wiring BGL3. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2. The gate of transistor M10 is connected to wiring BRL, and the back gate of transistor M10 is connected to wiring BGL4.

[0397] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0398] The BIL and BILB wiring are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the conduction and non-conduction states of transistors M9 and M10.

[0399] Wiring BGL1 to BGL4 are used to apply potentials to the back gates of transistors M7 to M10, respectively. By applying any potential to wiring BGL1 to BGL4, the threshold voltages of transistors M7 to M10 can be increased or decreased, respectively.

[0400] Wiring VDL provides a high-level potential, while wiring GNDL provides a low-level potential.

[0401] Data is written by applying a high-level potential to the wiring WOL and the wiring BRL. Specifically, when the transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, so that the potential is written to the second terminal side of the transistor M10.

[0402] Memory unit 39 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the potential applied to the wiring BIL, that is, the inverted signal of the signal input to the wiring BIL, is output to the wiring BIL. In addition, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistors M7 and M8 are maintained by the first terminals of capacitors CD2 and CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL, transistors M7 to M10 are turned off, thereby storing the potentials of the first terminals of capacitors CD1 and CD2.

[0403] Data is read out using the following method: First, wiring BIL and wiring BILB are pre-charged to a predetermined potential. Then, a high-level potential is applied to wiring WOL and wiring BRL. As a result, the potential of the first terminal of capacitor CD1 is updated by the inverter loop of memory cell 39 and output to wiring BILB. Similarly, the potential of the first terminal of capacitor CD2 is updated by the inverter loop of memory cell 39 and output to wiring BIL. Since wiring BIL and wiring BILB change from the pre-charged potential to the potential of the first terminal of capacitor CD2 and the first terminal of capacitor CD1, respectively, the potential held by the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0404] Transistors M7 to M10 are preferably OS transistors. In particular, the channel forming region of transistors M7 to M10 is preferably an oxide semiconductor containing indium, gallium, and zinc. OS transistors containing indium, gallium, and zinc oxide have the characteristic of extremely low off-state current; therefore, by using OS transistors as transistors M7 to M10, the leakage current of transistors M7 to M10 can be made very low. In particular, transistors M7 to M10 can retain written data for a longer period, thereby reducing the update frequency of the memory cells. Furthermore, the memory cell update operation can be eliminated.

[0405] Furthermore, Si transistors are preferred as transistors MS1 to MS4.

[0406] By using memory string 200 as memory cell 30, semiconductor device 400 can be used as NAND type memory device. Furthermore, by using memory cells 31 to 39 as memory cell 30, semiconductor device 400 can be used as NOR type memory device.

[0407] The driving circuit 410 and memory array 420 of the semiconductor device 400 are disposed on the same plane. Furthermore, as shown in FIG46A, the driving circuit 410 and memory array 420 may also overlap. By overlapping the driving circuit 410 and memory array 420, the signal transmission distance can be shortened. As shown in FIG46B, multiple memory arrays 420 may also be stacked on the driving circuit 410.

[0408] Furthermore, as shown in Figure 46C, memory arrays 420 can also be arranged in the upper and lower layers of the driving circuit 410. Figure 46C shows an example of arranging one layer of memory array 420 in the upper and lower layers of the driving circuit 410 respectively. By sandwiching the driving circuit 410 with multiple memory arrays 420, the signal transmission distance can be further shortened. In addition, the number of memory arrays 420 stacked in the upper layer of the driving circuit 410 and the number of memory arrays 420 stacked in the lower layer of the driving circuit 410 can both be one or more. Preferably, the number of memory arrays 420 stacked in the upper layer of the driving circuit 410 and the number of memory arrays 420 stacked in the lower layer of the driving circuit 410 are equal.

[0409] This embodiment can be implemented by appropriately combining it with other structures shown in this embodiment, etc.

[0410] Implementation Method 4 This embodiment shows an example of a semiconductor wafer forming a semiconductor device or the like shown in the above embodiment, and electronic components assembled with the semiconductor device.

[0411] Semiconductor wafers First, an example of a semiconductor wafer on which semiconductor devices are formed will be illustrated using Figure 47A.

[0412] The semiconductor wafer 4800 shown in Figure 47A includes a wafer 4801 and a plurality of circuit portions 4802 disposed on the top surface of the wafer 4801. The portion on the top surface of the wafer 4801 where no circuit portions 4802 are disposed corresponds to a gap 4803, which is an area for dicing.

[0413] Semiconductor wafer 4800 can be manufactured by forming multiple circuit portions 4802 on the surface of wafer 4801 in a previous process. Furthermore, the back side of wafer 4801 with the multiple circuit portions 4802 formed can be polished to reduce the thickness of wafer 4801. Through the above processes, wafer 4801 warpage and other defects can be reduced, thereby achieving miniaturization of the component.

[0414] The cutting process is then performed. Cutting is carried out along the dividing lines SCL1 and SCL2 (sometimes referred to as cutting lines or severance lines) shown by the dotted lines. For ease of cutting, it is preferable to set the gap 4803 in such a way that multiple dividing lines SCL1 are parallel, multiple dividing lines SCL2 are parallel, and dividing lines SCL1 and SCL2 are perpendicular.

[0415] By performing a dicing process, a wafer 4800a as shown in FIG47B can be diced from a semiconductor wafer 4800. Wafer 4800a includes a wafer 4801a, a circuit section 4802, and a gap 4803a. Furthermore, the gap 4803a is preferably as small as possible. In this case, the width of the gap 4803a between adjacent circuit sections 4802 only needs to be approximately equal to the dividing portion of dividing line SCL1 and the dividing portion of dividing line SCL2.

[0416] Furthermore, the shape of the component substrate in one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 47A. For example, it can be a rectangular semiconductor wafer. In addition, the shape of the component substrate can be appropriately changed according to the component manufacturing process and the manufacturing equipment.

[0417] <Electronic Components> Figure 47C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Figure 47C includes a chip 4800a in a mold 4711. The semiconductor device described in the above embodiment can be used as the circuit section 4802.

[0418] In Figure 47C, a portion of the electronic component 4700 is omitted to show its internal structure. The electronic component 4700 includes a connecting land 4712 on the outside of the mold 4711. The connecting land 4712 is electrically connected to electrode pads 4713, which are electrically connected to the chip 4800a via leads 4714. The electronic component 4700 is mounted, for example, on a printed circuit board 4702. By assembling multiple such electronic components and electrically connecting them individually on the printed circuit board 4702, a mounting substrate 4704 is thus completed.

[0419] Figure 47D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 4730, an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and semiconductor devices 4735 and multiple semiconductor devices 4710 are provided on the interposer 4731.

[0420] Semiconductor device 4710 may be, for example, a chip 4800a, a semiconductor device described in the above embodiments, or a high-bandwidth memory (HBM). Furthermore, semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, or memory device.

[0421] The packaging substrate 4732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The through-hole board 4731 can be a silicon through-hole board, a resin through-hole board, etc.

[0422] The through-hole board 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal spacings. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 4731 functions to electrically connect the integrated circuits disposed on the through-hole board 4731 to electrodes disposed on the package substrate 4732. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate." Additionally, sometimes a through electrode is provided in the through-hole board 4731 to electrically connect the integrated circuits to the package substrate 4732. Furthermore, when using a silicon through-hole board, a TSV (Through Silicon Via) can also be used as the through electrode.

[0423] Silicon interposers are preferred for the 4731. Since silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. Wiring formation on silicon interposers can be performed during semiconductor manufacturing processes, and resin interposers are easier to form with fine wiring.

[0424] In HBM, achieving wide memory bandwidth requires connecting numerous traces. Therefore, the board on which HBM is mounted needs to be able to form fine traces at high density. Thus, silicon boards are preferred for mounting HBM.

[0425] Furthermore, in SiP or MCM applications using silicon through-hole boards, reliability degradation due to differences in the coefficients of thermal expansion between integrated circuits and the through-hole board is less likely to occur. Additionally, due to the high surface flatness of silicon through-hole boards, poor connections between integrated circuits mounted on the board and the board itself are less likely to occur. It is particularly preferable to use silicon through-hole boards in 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the through-hole board.

[0426] Alternatively, a heat sink (heat plate) may be disposed overlapping with the electronic component 4730. When a heat sink is disposed, it is preferable that the height of the integrated circuit disposed on the insert 4731 is the same. For example, in the electronic component 4730 shown in this embodiment, it is preferable that the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.

[0427] To mount the electronic component 4730 onto other substrates, electrodes 4733 can be disposed on the bottom of the package substrate 4732. Figure 47D shows an example of forming electrodes 4733 using solder balls. By arranging solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 4733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0428] Electronic component 4730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0429] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0430] Implementation Method 5 In this embodiment, an example of a computing processing apparatus that can include a semiconductor device such as a memory device as described in the above embodiments will be described.

[0431] Figure 48 is a block diagram of an example of the structure of the central processing unit 1100. Figure 48 shows an example of the structure of the CPU as an example of the structure that can be used in the central processing unit 1100.

[0432] The central processing unit 1100 shown in Figure 48 has the following components on a substrate 1190: an ALU 1191 (ALU: Arithmetic Logic Unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189. The substrate 1190 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 can also be located on different chips.

[0433] Cache 1199 is connected to main memory located on different chips via cache interface 1189. Cache interface 1189 has the function of supplying a portion of the data stored in main memory to cache 1199. Cache 1199 has the function of storing this data.

[0434] Of course, the central processing unit 1100 shown in Figure 48 is just one example with a simplified structure, so the actual central processing unit 1100 has various structures depending on its purpose. For example, multiple such cores can be set up and made to work simultaneously, i.e., like a GPU, based on the structure including the central processing unit 1100 or the arithmetic circuit shown in Figure 48. In addition, the number of bits that can be processed in the internal arithmetic circuit or data bus of the central processing unit 1100 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0435] Instructions input to the central processing unit 1100 via the bus interface 1198 are input to the instruction decoder 1193 and decoded before being input to the ALU controller 1192, interrupt controller 1194, temporary register controller 1197, and timing controller 1195.

[0436] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals to control the operation of the ALU 1191. Furthermore, when executing the program of the central processing unit 1100, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or masking state. The register controller 1197 generates the address of the register 1196 and reads or writes the register 1196 according to the state of the central processing unit 1100.

[0437] Furthermore, the timing controller 1195 generates signals to control the operating timing of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0438] In the central processing unit 1100 shown in FIG48, a memory device is provided in the temporary register 1196 and the cache 1199. As this memory device, the memory device shown in the above embodiment or the like can be used.

[0439] In the central processing unit 1100 shown in Figure 48, the register controller 1197 selects the retention operation in the register 1196 according to the instructions of the ALU 1191. In other words, the register controller 1197 selects whether the data in the memory cells of the register 1196 is retained by a flip-flop or by a capacitor. When the data is retained by the flip-flop, a power supply voltage is supplied to the memory cells in the register 1196. When the data is retained by the capacitor, the data is overwritten by the capacitor, and the power supply voltage to the memory cells in the register 1196 can be stopped.

[0440] The semiconductor device 400 and the central processing unit 1100 shown in the above embodiment can overlap. Figures 49A and 49B are perspective views of the semiconductor device 1150A. The semiconductor device 1150A includes the semiconductor device 400, which serves as a memory device, on the central processing unit 1100. The central processing unit 1100 and the semiconductor device 400 include overlapping areas. To facilitate understanding of the structure of the semiconductor device 1150A, Figure 49B shows the central processing unit 1100 and the semiconductor device 400, respectively.

[0441] By overlapping the semiconductor device 400 and the central processing unit 1100, the connection distance between them can be shortened. This improves communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0442] As shown in the above embodiment, by using an OS NAND type memory device in the semiconductor device 400, one or all of the plurality of memory cells 30 provided by the semiconductor device 400 can be used as RAM. Therefore, the semiconductor device 400 can be used as main memory. The semiconductor device 400 used as main memory is connected to the cache 1199 via the cache interface 1189.

[0443] Whether the semiconductor device 400 is used as main memory (RAM) or as a temporary register depends on the control circuit 412 shown in FIG43. The control circuit 412 may use a portion of the plurality of memory cells 30 contained in the semiconductor device 400 as RAM based on signals supplied from the central processing unit 1100.

[0444] Semiconductor device 400 can use a portion of the plurality of memory cells 30 as RAM and the rest as temporary storage. By using OS NAND type memory devices in semiconductor device 400, it can function as both main memory and temporary storage. Semiconductor device 400 of one embodiment of the present invention can, for example, be used as general purpose memory.

[0445] When the semiconductor device 400 is used as main memory, the memory capacity can be increased or decreased as needed. Furthermore, when the semiconductor device 400 is used as cache, the memory capacity can be increased or decreased as needed.

[0446] Furthermore, the control circuit 412 shown in FIG43 may also have the function of performing error checking and correction (also known as ECC) when transferring or copying data between the area used as a temporary storage and the area used as main memory in the semiconductor device 400. Additionally, the control circuit 412 may also have the function of performing ECC when transferring or copying data between the area used as main memory and the cache 1199 in the semiconductor device 400.

[0447] Furthermore, the semiconductor device 400 and the central processing unit 1100 may overlap. Figures 50A and 50B are perspective views of the semiconductor device 1150B. The semiconductor device 1150B includes semiconductor devices 400a and 400b on the central processing unit 1100. The central processing unit 1100 and semiconductor devices 400a and 400b include overlapping areas. To facilitate understanding of the structure of the semiconductor device 1150B, Figure 50B shows the central processing unit 1100, semiconductor devices 400a and 400b respectively.

[0448] Semiconductor devices 400a and 400b are used as memory devices. For example, NOR type memory can be used as semiconductor device 400a. Furthermore, NAND type memory can be used as semiconductor device 400b. NOR type memory devices operate at higher speeds than NAND type memory devices, therefore, for example, a portion of semiconductor device 400a can be used as main memory and / or cache 1199. Furthermore, the overlapping order of semiconductor devices 400a and 400b can be reversed.

[0449] Figures 51A and 51B are perspective views of semiconductor device 1150C. Semiconductor device 1150C has a structure in which a central processing unit 1100 is sandwiched between semiconductor devices 400a and 400b. Thus, the central processing unit 1100 and semiconductor devices 400a and 400b include overlapping areas. For easier understanding of the structure of semiconductor device 1150C, Figure 51B shows the central processing unit 1100, semiconductor devices 400a and 400b respectively.

[0450] By employing the structure of semiconductor device 1150C, both the communication speed between semiconductor device 400a and central processing unit 1100 and the communication speed between semiconductor device 400b and central processing unit 1100 can be improved. Furthermore, compared to semiconductor device 1150B, power consumption can be further reduced.

[0451] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0452] Implementation Method 6 This embodiment illustrates an application example of a memory device according to one embodiment of the present invention.

[0453] Generally, various memory devices can be used in semiconductor devices such as computers, depending on their application. Figure 52A shows the different levels of memory devices used in semiconductor devices. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger memory capacities and higher recording densities. In Figure 52A, from top to bottom, the following are shown in sequence: memory installed as temporary storage in processing devices such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0454] Because the memory installed in processing devices such as CPUs, which is used for temporary storage of calculation results, is accessed frequently by the processing device. Therefore, a faster operating speed is required compared to memory capacity. Furthermore, the temporary memory also has the function of holding settings information of the processing device.

[0455] SRAM is used, for example, as a cache. A cache has the function of copying and maintaining a portion of the information held in main memory. By copying frequently used data to the cache, the speed of data access can be improved. The cache requires less memory capacity than main memory, but the cache requires a higher operating speed than main memory. Furthermore, data that is overwritten in the cache is copied and supplied to main memory.

[0456] DRAM is used, for example, in main memory. Main memory has the function of holding programs or data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm².

[0457] 3D NAND memory is used, for example, for storage. Storage has the function of holding data that needs to be preserved for a long time and various programs used by computing devices. Therefore, compared with faster operating speeds, storage requires larger memory capacity and higher recording density. The recording density of memory devices used for storage is approximately 0.6 Gbit / mm² or higher and 6.0 Gbit / mm² or lower.

[0458] A memory device according to one embodiment of the present invention operates at high speed and can retain data for a long period of time. A memory device according to one embodiment of the present invention can be used as a memory device located in the boundary region 901 between the cache layer and the main memory layer. Furthermore, a memory device according to one embodiment of the present invention can be used as a memory device located in the boundary region 902 between the main memory layer and the storage layer.

[0459] Furthermore, a memory device according to one embodiment of the present invention is suitable for both the main memory hierarchy and the storage hierarchy. Additionally, a memory device according to one embodiment of the present invention is suitable for the cache hierarchy. Figure 52B illustrates memory devices of different levels from those in Figure 52A.

[0460] In Figure 52B, from top to bottom, the memory installed as a temporary storage device in an arithmetic processing unit such as a CPU, the SRAM used as a cache, and the 3D OS NAND memory are shown in sequence. The memory device of one embodiment of the present invention can be used as a cache, main memory, and a temporary storage device. In the case where high-speed memory of 1 GHz or higher is required as a cache, this cache is installed in an arithmetic processing unit such as a CPU.

[0461] The memory device in one embodiment of the present invention is not limited to NAND type but can be NOR type. Furthermore, NAND type and NOR type can also be used in combination.

[0462] The memory device according to one embodiment of the present invention can be applied to memory devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras, video recording devices, navigation systems, game consoles, etc.). Furthermore, it can be used in image sensors, IoT (Internet of Things), and medical applications. Here, "computer" includes tablet computers, laptops, desktop computers, and mainframe computers such as server systems.

[0463] Figures 53A to 53J and Figures 54A to 54E show the case where electronic component 4700 or electronic component 4730 with the memory device is included in each electronic device.

[0464] [Mobile Phone] The information terminal 5500 shown in Figure 53A is a mobile phone (smartphone), one type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. The display unit 5511 has a touch panel as an input interface, and buttons are provided on the housing 5510.

[0465] By applying the memory device of one embodiment of the present invention to the information terminal 5500, documents temporarily generated during program execution (e.g., cache when using a web browser) can be stored.

[0466] Wearable devices Furthermore, Figure 53B shows an example of a wearable terminal, an information terminal 5900. The information terminal 5900 includes a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, a watch strap 5905, etc.

[0467] Similar to the aforementioned information terminal 5500, by applying the memory device of one embodiment of the present invention to a wearable terminal, documents temporarily generated during program execution can be stored.

[0468] [Information Terminal] Figure 53C shows a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal body 5301, a display unit 5302, and a keyboard 5303.

[0469] Similar to the aforementioned information terminal 5500, by applying the memory device of one embodiment of the present invention to the desktop information terminal 5300, documents temporarily generated during program execution can be stored.

[0470] Note that in the examples above, Figures 53A to 53C show smartphones, wearable terminals, and desktop information terminals as examples of electronic devices. However, information terminals other than smartphones, wearable terminals, and desktop information terminals can also be used. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), laptop information terminals, and workstations.

[0471] [Electrical Products] Furthermore, Figure 53D shows an example of an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes a housing 5801, a refrigerator door 5802, and a freezer door 5803, etc. For example, the electric refrigerator / freezer 5800 is an electric refrigerator / freezer corresponding to the Internet of Things (IoT).

[0472] The memory device according to one embodiment of the present invention can be applied to an electric refrigerator / freezer 5800. By utilizing the Internet or the like, the electric refrigerator / freezer 5800 can send information such as the food stored in the electric refrigerator / freezer 5800 or the expiration date of the food to an information terminal or the like. The electric refrigerator / freezer 5800 can store documents temporarily generated when sending this information in the memory device.

[0473] In the above example, the electric refrigerator / freezer is described as an electrical appliance. However, other electrical appliances could include, for example, vacuum cleaners, microwave ovens, electric ovens, electric rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners), washing machines, dryers, and audio-visual equipment.

[0474] [Game console] Furthermore, Figure 53E shows an example of a portable game console 5200. The portable game console 5200 includes a casing 5201, a display unit 5202, buttons 5203, etc.

[0475] Furthermore, Figure 53F shows an example of a fixed game console 7500. The fixed game console 7500 includes a main unit 7520 and a controller 7522. The main unit 7520 can be connected to the controller 7522 wirelessly or via a wired connection. Although not shown in Figure 53F, the controller 7522 may include a display unit for showing game images, a touch panel and joystick as an input interface other than buttons, a rotating grip, a sliding grip, etc. Furthermore, the controller 7522 is not limited to the shape shown in Figure 53F; its shape can be changed depending on the type of game. For example, in shooting games such as FPS (First Person Shooter), a controller shaped like a gun can be used as a trigger button. Additionally, for example, in music games, a controller shaped like a musical instrument or other musical device can be used. Moreover, the fixed game console may also be equipped with a camera, depth sensor, microphone, etc., allowing the player to operate it via gestures and / or voice, replacing the shape of the controller.

[0476] Furthermore, the images from the aforementioned game consoles can be output from display devices such as televisions, personal computer monitors, game monitors, and head-mounted displays.

[0477] By using the memory device described in the above embodiments in a portable game console 5200 or a stationary game console 7500, a low-power portable game console 5200 or a stationary game console 7500 can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuits, and modules.

[0478] Furthermore, by using the memory device described in the above embodiments in a portable game console 5200 or a stationary game console 7500, it is possible to store calculation files temporarily generated during game execution.

[0479] Figure 53E shows a portable game console as an example. Figure 53F shows a home-based stationary game console. The electronic device according to one embodiment of the present invention is not limited thereto. Examples of electronic devices applying one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0480] [Moving Object] The memory device described in the above embodiments can be applied to a car as a mobile object and to the vicinity of the driver's seat of the car.

[0481] Figure 53G shows a car 5700 as an example of a moving body.

[0482] The 5700 car has an instrument panel near the driver's seat that displays various information such as speedometer, tachometer, distance traveled, fuel level, gear position, and air conditioning settings. Alternatively, a display device showing the aforementioned information may also be installed near the driver's seat.

[0483] In particular, by displaying images captured by a camera device (not shown) installed on the vehicle 5700 on the aforementioned display device, obstructions such as those caused by pillars and blind spots near the driver's seat can be provided to the driver, thereby improving safety. In other words, by displaying images captured by a camera device located on the outside of the vehicle 5700, the field of vision can be supplemented to avoid blind spots and improve safety.

[0484] The memory device described in the above embodiments can temporarily store data. For example, this memory device can be used in the autonomous driving system of the car 5700, navigation, hazard prediction, and other systems to temporarily store necessary data. In addition, it can also store recordings from a dashcam installed in the car 5700.

[0485] While the above example illustrates a moving object like a car, moving objects are not limited to cars. Examples of moving objects include trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets), etc.

[0486] [camera] The memory device described in the above embodiments can be applied to a camera.

[0487] Figure 53H shows an example of a camera device, a digital camera 6240. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and is equipped with a detachable lens 6246. Here, the digital camera 6240 employs a structure where the lens 6246 can be detached from the housing 6241, but the lens 6246 and the housing 6241 are formed as a single unit. Furthermore, the digital camera 6240 may also include separately mounted flash units and viewfinders, etc.

[0488] By using the memory device described in the above embodiments in the digital camera 6240, a low-power digital camera 6240 can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuitry, and the module.

[0489] [Video camera] The memory device described in the above embodiments can be applied to video cameras.

[0490] Figure 53I shows an example of a video camera 6300. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, and a connecting part 6306. The operation switch 6304 and the lens 6305 are disposed on the first housing 6301, and the display unit 6303 is disposed on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connecting part 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting part 6306. The image displayed on the display unit 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connecting part 6306.

[0491] When recording images captured by the video camera 6300, encoding is required according to the data recording method. With the aid of the aforementioned memory device, the video camera 6300 can store documents temporarily generated during encoding.

[0492] [ICD] The memory device described in the above embodiments can be applied to implantable cardioverter defibrillators (ICDs).

[0493] Figure 53J is a cross-sectional schematic diagram showing an example of an ICD. The ICD body 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 extending to the right atrium, and a wire 5403 extending to the right ventricle.

[0494] The ICD body 5400 is surgically implanted in the body. Two metal wires pass through the subclavian vein 5405 and the superior vena cava 5406, with the tip of one metal wire placed in the right ventricle and the tip of the other metal wire placed in the right atrium.

[0495] The ICD main unit 5400 has the function of a cardiac pacemaker, pacing the heart when the heart rhythm is outside the prescribed range. In addition, it can be used for defibrillation treatment when the heart rhythm does not improve even when pacing is performed (such as rapid ventricular tachycardia or ventricular fibrillation).

[0496] In order to perform pacing and defibrillation properly, the ICD body 5400 needs to monitor the heart rhythm frequently. Therefore, the ICD body 5400 includes a sensor for detecting the heart rhythm. In addition, the ICD body 5400 can store data on the heart rhythm measured by the sensor, the number of pacing treatments, the duration, etc., in the electronic component 4700.

[0497] Furthermore, power is received by antenna 5404 and this power is used to charge battery 5401. Additionally, by including multiple batteries in the ICD body 5400, safety can be improved. Specifically, even if some batteries in the ICD body 5400 fail, the other batteries can function and be used as auxiliary power.

[0498] In addition to the antenna 5404, which can receive power, it may also include an antenna capable of transmitting physiological signals. For example, it may also constitute a system for monitoring cardiac activity that can be confirmed by an external monitoring device with physiological signals such as pulse, respiratory rate, heart rate, and body temperature.

[0499] [PC Expansion Devices] The memory device described in the above embodiments can be applied to expansion devices for computers and information terminals such as PCs (Personal Computers).

[0500] Figure 54A shows an example of a portable expansion device 6100 external to a PC, equipped with a data storage chip. The expansion device 6100 can store data, for example, by connecting to the PC via a USB (Universal Serial Bus) or similar means. Note that although Figure 54A shows a portable expansion device 6100, the expansion device according to one embodiment of the present invention is not limited to this; for example, a larger expansion device with a cooling fan or similar structure may also be used.

[0501] The expansion device 6100 includes a housing 6101, a cover 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed within the housing 6101. The substrate 6104 is provided with circuitry for driving memory devices, etc., as described in the above embodiments. For example, the substrate 6104 is mounted with electronic components 4700 and a controller chip 6106. The USB connector 6103 serves as an interface for connecting to external devices.

[0502] [SD card] The memory device described in the above embodiments can be applied to SD cards that can be installed in electronic devices such as information terminals or digital cameras.

[0503] Figure 54B is a schematic diagram of the external appearance of an SD card, and Figure 54C is a schematic diagram of the internal structure of an SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 has the function of an interface for connecting to an external device. The substrate 5113 is housed within the housing 5111. The substrate 5113 is provided with a memory device and circuitry for driving the memory device. For example, the substrate 5113 is equipped with an electronic component 4700 and a controller chip 5115. Furthermore, the circuit structures of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit structures can be appropriately modified as needed. For example, the write circuit, line driver, read circuit, etc., provided by the electronic component may be mounted on the controller chip 5115 instead of the electronic component 4700.

[0504] By also providing electronic components 4700 on one side of the back of the substrate 5113, the capacity of the SD card 5110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can be provided on the substrate 5113. This enables wireless communication between external devices and the SD card 5110, and allows for reading and writing data from the electronic components 4700.

[0505] [SSD] The memory device described in the above embodiments can be applied to solid-state drives (SSDs) that can be installed in electronic devices such as information terminals.

[0506] Figure 54D is a schematic diagram of the external appearance of the SSD, and Figure 54E is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 has an interface for connecting to an external device. The substrate 5153 is housed within the housing 5151. The substrate 5153 is provided with a memory device and circuitry for driving the memory device. For example, the substrate 5153 may house an electronic component 4700, a memory chip 5155, and a controller chip 5156. By also providing the electronic component 4700 on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. The memory chip 5155 contains working memory. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 contains a processor, ECC circuitry, etc. Note that the circuit structures of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and the circuit structures can be appropriately modified as needed. For example, a memory that can be used as working memory can also be set in the controller chip 5156.

[0507] [computer] The computer 5600 shown in Figure 55A is an example of a mainframe computer. In computer 5600, multiple rack-mounted computers 5620 are housed in rack 5610.

[0508] Computer 5620 may, for example, have the structure shown in the perspective view of Figure 55B. In Figure 55B, computer 5620 includes a motherboard 5630, which includes multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into the slots 5631. Furthermore, the personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0509] The personal computer card 5621 shown in Figure 55C is an example of a processing board including a CPU, GPU, memory devices, etc. The personal computer card 5621 has a board 5622. Furthermore, the board 5622 includes connection terminals 5623, 5624, and 5625, semiconductor devices 5626, 5627, and 5628, and connection terminals 5629. Note that Figure 55C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628; for a description of these semiconductor devices, refer to the description of semiconductor devices 5626, 5627, and 5628 described below.

[0510] The connector 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630. The connector 5629 is used as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of connector 5629 specifications include PCIe.

[0511] Connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5621. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5621. Examples of the specifications for each of connection terminals 5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Unit System Interface). Furthermore, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of the specifications include HDMI (registered trademark).

[0512] Semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting the terminals into a socket (not shown) included in board 5622, semiconductor device 5626 and board 5622 can be electrically connected.

[0513] Semiconductor device 5627 includes multiple terminals, which can be electrically connected to board 5622 by reflow soldering the terminals to the wiring provided on board 5622. Examples of semiconductor devices 5627 include FPGA, GPU, and CPU. Electronic component 4730 can also be used as a semiconductor device 5627.

[0514] Semiconductor device 5628 includes multiple terminals, which can be electrically connected to board 5622 by reflow soldering the terminals to wiring provided on board 5622. Examples of semiconductor devices 5628 include memory devices. Electronic component 4700 can also be used as a semiconductor device 5628.

[0515] The PC 5600 can be used as a parallel computer. By using the PC 5600 as a parallel computer, large-scale calculations required for artificial intelligence learning and inference can be performed, for example.

[0516] By using the semiconductor device according to one embodiment of the present invention in the various electronic devices described above, miniaturization, high speed, or low power consumption of the electronic devices can be achieved. Furthermore, the semiconductor device according to one embodiment of the present invention consumes less power, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Moreover, by using the semiconductor device according to one embodiment of the present invention, electronic devices can operate stably even in high-temperature environments. This improves the reliability of the electronic devices.

[0517] Next, an example of the structure of a computer system that can be applied to computer 5600 will be described. Figure 56 is a diagram illustrating an example of the structure of computer system 700. Computer system 700 includes software and hardware. Note that the hardware included in the computer system is sometimes referred to as a signal processing device.

[0518] The software constituting the computer system 700 includes an operating system containing device drivers, middleware, various development environments, AI applications, and applications unrelated to AI.

[0519] Device drivers include applications used to control external connection devices such as auxiliary memory devices, display devices, and printers.

[0520] The hardware constituting the computer system 700 includes a first arithmetic processing unit, a second arithmetic processing unit, and a first memory device. Furthermore, the second arithmetic processing unit includes a second memory device.

[0521] As the primary processing unit, a central processing unit such as an Noff OS CPU is preferably used. The Noff OS CPU includes a memory unit (e.g., non-volatile memory) using OS transistors, which has the function of storing necessary information in the memory unit and stopping power supply to the central processing unit when not in use. By using an Noff OS CPU as the primary processing unit, the power consumption of the computer system 700 can be reduced.

[0522] As a secondary computing device, a GPU or FPGA can be used, for example. Preferably, an AI OS accelerator is used. An AI OS accelerator consists of OS transistors and includes computing units such as multiplication and arithmetic circuits. AI OS accelerators consume less power than typical GPUs. By using an AI OS accelerator as a secondary computing device, the power consumption of the computer system 700 can be reduced.

[0523] The first and second memory devices are preferably memory devices using an embodiment of the present invention. For example, a 3D OS NAND type memory device is preferred. The 3D OS NAND type memory device can be used as a cache, main memory, and temporary storage. Furthermore, by using a 3D OS NAND type memory device, a non-Neumann computer system can be easily implemented.

[0524] 3D OS NAND memory devices consume less power than 3D NAND memory devices using Si transistors. By using 3D OS NAND memory devices as memory, the power consumption of the computer system 700 can be reduced. Furthermore, 3D OS NAND memory devices can be used as general-purpose memory, thereby reducing the number of components constituting the memory devices in the computer system 700.

[0525] The semiconductor devices that make up the hardware are composed of semiconductor devices including OS transistors, which makes it easy to monolithize the hardware, including the central processing unit, arithmetic processing unit, and memory device. By monolithizing the hardware, not only can miniaturization, weight reduction, and thinning be achieved, but power consumption can also be easily reduced.

[0526] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0527] Implementation Method 7 By utilizing the memory cells or memory devices shown in this specification, a normally off CPU (also known as a "Noff-CPU") can be implemented. An Noff-CPU refers to an integrated circuit that includes a normally off transistor that is in a non-conducting state (also known as an off state) even when the gate voltage is 0V.

[0528] In Noff-CPU, power can be cut off to circuits that are not in operation, putting those circuits into a standby state. In a standby state with power cut off, no power is consumed. Therefore, Noff-CPU can minimize power consumption. Furthermore, even with power cut off, Noff-CPU can retain information necessary for operation, such as settings, for an extended period. When resuming from standby, simply restarting power to the circuit is sufficient; there is no need to rewrite the settings. In other words, it can resume from standby at high speed. Thus, Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0529] As a memory device for retaining information such as settings even when power to the Noff-CPU is stopped, a memory device according to one embodiment of the present invention can be used. Furthermore, the memory device according to one embodiment of the present invention can be applied to the cache of the Noff-CPU, and also to the main memory of the Noff-CPU.

[0530] Noff-CPUs can be used, for example, in small-scale systems such as IoT terminal devices (“also known as endpoint microcomputers”) like the 803 in the IoT field.

[0531] Figure 57 illustrates the layered structure of IoT networks and the trend of demand specifications. In Figure 57, power consumption 804 and processing performance 805 are shown as demand specifications. The layered structure of IoT networks is broadly divided into an upper-layer cloud domain 801 and a lower-layer embedded domain 802. For example, servers are included in the cloud domain 801. For example, machinery, industrial robots, automotive devices, and home appliances are included in the embedded domain 802.

[0532] The higher the layer, the greater the demand for high processing performance compared to low power consumption. Therefore, in the cloud domain, high-performance CPUs, high-performance GPUs, and large-scale SoCs (System on a Chip) are used. Furthermore, the lower the layer, the greater the demand for low power consumption compared to high processing performance, and the number of devices increases dramatically. A semiconductor device according to one embodiment of the present invention can be applied to the communication devices of IoT terminal devices that require low power consumption.

[0533] Furthermore, "endpoint" refers to the terminal area in the embedded systems field 802. For example, microcomputers used in factories, home appliances, infrastructure, agriculture, etc., are equivalent to devices used at the endpoint.

[0534] Figure 58 illustrates a factory automation scenario as an example of an endpoint microcomputer application. Factory 884 is connected to cloud 883 via the Internet. Furthermore, cloud 883 is connected to home 881 and company 882 via the Internet. The Internet can be either wired or wireless. For example, in the case of wireless communication, a fourth-generation (4G) or fifth-generation (5G) mobile communication system can be used. Factory 884 can also connect to factories 885 and 886 via the Internet.

[0535] Factory 884 includes a main device (control device) 831. The main device 831 has the function of sending and receiving information by connecting to the cloud 883. Furthermore, the main device 831 connects to multiple industrial robots 842, including an IoT terminal device 841, via an M2M (machine-to-machine) interface 832. The M2M interface 832 can be, for example, an industrial Ethernet (wired communication method) or a local 5G (wireless communication method).

[0536] Factory managers can check work status from home (881) or office (882) via cloud (883) connection to the factory (884). Furthermore, they can check for product errors and shortages, indicate placement locations, and measure takt time.

[0537] In recent years, driven by the concept of "smart factories," IoT has been adopted in factories worldwide. Examples of smart factories include those that utilize endpoint microcomputers not only for inspection and monitoring but also for fault detection and anomaly prediction.

[0538] In small-scale systems such as endpoint microcomputers, the overall system power consumption is often low during operation, making the CPU's power consumption a relatively large proportion. Therefore, the power reduction effect of Noff-CPU in standby mode is more significant in these systems. On the other hand, embedded applications in IoT sometimes require rapid response capabilities, and Noff-CPU can enable quick recovery from standby mode.

[0539] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment.

[0540] 100: Memory Unit 101: Insulator 102: Conductor 103: Conductor 108: Central axis 111: Insulator 112: Conductor 113: Semiconductors 114: Semiconductors 115: Insulator 116: Semiconductors 117: Insulator 118: Conductor 121: Semiconductors 122: Insulator 123: Insulator 130: Structure 131: Opening 132: Area 135: Area 136: Area 140: Laminated body 141: Sacrifice Layer

Claims

1. A semiconductor device comprising: a plurality of first openings disposed adjacent to each other; a plurality of first transistors disposed adjacent to each other; a plurality of second transistors disposed on the plurality of first transistors; a plurality of third transistors disposed on the plurality of second transistors; and a plurality of first capacitors, wherein... One of the plurality of first capacitors surrounds one of the plurality of third transistors; wherein one of the plurality of second transistors is filled into one of the plurality of first openings; wherein one of the plurality of third transistors is filled into the one of the plurality of first openings; wherein one of the source and drain electrodes of one of the plurality of second transistors is electrically connected to the gate electrode of one of the plurality of third transistors and an electrode of one of the plurality of first capacitors; and wherein a first conductor configured to serve as the gate electrode of one of the plurality of third transistors and a first insulating system contained in one of the plurality of first capacitors extend vertically and are parallel to each other.

2. A semiconductor device comprising: a plurality of first openings arranged adjacent to each other; a plurality of first transistors arranged adjacent to each other; a plurality of second transistors on the plurality of first transistors; a plurality of third transistors on the plurality of second transistors; and a plurality of first capacitors, wherein... One of the plurality of first capacitors surrounds one of the plurality of third transistors; A plurality of fourth transistors are disposed on the plurality of third transistors; a plurality of fifth transistors are disposed on the plurality of fourth transistors; and a plurality of second capacitors are disposed on the plurality of fifth transistors; wherein one of the plurality of second transistors is filled into one of the plurality of first openings; wherein one of the plurality of third transistors is filled into that one of the plurality of first openings; wherein one of the plurality of fourth transistors is filled into that one of the plurality of first openings; wherein one of the plurality of fifth transistors is filled into that one of the plurality of first openings; wherein one of the source and drain electrodes of one of the plurality of second transistors is electrically connected to the gate electrode of one of the plurality of third transistors, an electrode of one of the plurality of first capacitors, and one of the source and drain electrodes of one of the plurality of fourth transistors. Wherein, the source electrode of one of the plurality of fourth transistors and the drain electrode of another of the plurality of fifth transistors are electrically connected to the gate electrode of one of the plurality of fifth transistors and an electrode of one of the plurality of second capacitors; wherein, a first conductor configured to serve as the gate electrode of one of the plurality of third transistors and a first insulating system in contact with one electrode of one of the plurality of first capacitors and another electrode of one of the plurality of first capacitors extend perpendicularly and are parallel to each other; and wherein, a second conductor configured to serve as the gate electrode of one of the plurality of fifth transistors and a second insulating system in contact with one electrode of one of the plurality of second capacitors and another electrode of one of the plurality of second capacitors extend perpendicularly and are parallel to each other.

3. A semiconductor device comprising: a plurality of first openings arranged adjacent to each other; a plurality of first transistors arranged adjacent to each other; a plurality of second transistors on the plurality of first transistors; a plurality of third transistors on the plurality of second transistors; and a plurality of first capacitors, wherein... One of the plurality of first capacitors is adjacent to one of the plurality of third transistors; A plurality of fourth transistors are disposed on the plurality of third transistors; a plurality of fifth transistors are disposed on the plurality of fourth transistors; and a plurality of second capacitors are disposed adjacent to one of the plurality of fifth transistors; wherein one of the plurality of second transistors is filled into one of the plurality of first openings; wherein one of the plurality of third transistors is filled into that one of the plurality of first openings; wherein one of the plurality of fourth transistors is filled into one of the plurality of first openings; wherein one of the plurality of fifth transistors is filled into that one of the plurality of first openings; wherein one of the source and drain electrodes of one of the plurality of second transistors is electrically connected to a first gate electrode of one of the plurality of third transistors, an electrode of one of the plurality of first capacitors, and one of the source and drain electrodes of one of the plurality of fourth transistors; In this configuration, the source electrode of one of the plurality of fourth transistors and the drain electrode of the other are electrically connected to the first gate electrode of one of the plurality of fifth transistors and an electrode of one of the plurality of second capacitors; the second gate electrode of one of the plurality of third transistors is electrically connected to the second gate electrode of one of the plurality of fifth transistors; a first conductor configured as the gate electrode of one of the plurality of third transistors and a first insulating system contained in one of the plurality of first capacitors extend vertically and are parallel to each other; and a second conductor configured as the gate electrode of one of the plurality of fifth transistors and a second insulating system contained in one of the plurality of second capacitors extend vertically and are parallel to each other.

4. A semiconductor device comprising: a plurality of first openings disposed adjacent to each other; a plurality of first transistors disposed adjacent to each other; a plurality of second transistors disposed on the plurality of first transistors; a plurality of third transistors disposed on the plurality of second transistors; and a plurality of first capacitors, wherein... One of the plurality of first capacitors surrounds one of the plurality of third transistors; wherein one of the plurality of second transistors is filled into one of the plurality of first openings; wherein one of the plurality of third transistors is filled into the one of the plurality of first openings; wherein one of the source and drain electrodes of one of the plurality of second transistors is electrically connected to the gate electrode of one of the plurality of third transistors and an electrode of one of the plurality of first capacitors; wherein a first conductor configured as the gate electrode of one of the plurality of third transistors and a first insulating system contained in one of the plurality of first capacitors extend vertically and are parallel to each other; and wherein a second conductor configured as the gate electrode of one of the plurality of second transistors overlaps with a third conductor configured as another electrode of one of the plurality of first capacitors.

5. A semiconductor device comprising: a plurality of first openings disposed adjacent to each other; a plurality of first transistors disposed adjacent to each other; a plurality of second transistors disposed on the plurality of first transistors; a plurality of third transistors disposed on the plurality of second transistors; and a plurality of first capacitors, wherein... One of the plurality of first capacitors surrounds one of the plurality of third transistors; wherein one of the plurality of second transistors is filled into one of the plurality of first openings; wherein one of the plurality of third transistors is filled into the first opening; wherein one of the source and drain electrodes of one of the plurality of second transistors is electrically connected to the gate electrode of one of the plurality of third transistors and an electrode of one of the plurality of first capacitors; wherein one of the plurality of first transistors contains silicon in the channel forming region; wherein one of the plurality of second transistors contains oxide semiconductor in the channel forming region; wherein one of the plurality of third transistors contains oxide semiconductor in the channel forming region; and wherein a first conductor configured to serve as the gate electrode of one of the plurality of third transistors and a first insulating system contained in one of the plurality of first capacitors extend vertically and are parallel to each other.

6. A semiconductor device comprising: a plurality of first openings disposed adjacent to each other; a plurality of first transistors disposed adjacent to each other; a plurality of second transistors disposed on the plurality of first transistors; a plurality of third transistors disposed on the plurality of second transistors; and a plurality of first capacitors, wherein... One of the plurality of first capacitors surrounds one of the plurality of third transistors; wherein one of the plurality of second transistors is filled into one of the plurality of first openings; wherein one of the plurality of third transistors is filled into the first opening; wherein one of the source and drain electrodes of one of the plurality of second transistors is electrically connected to the gate electrode of one of the plurality of third transistors and an electrode of one of the plurality of first capacitors; wherein one of the plurality of first transistors contains single-crystal silicon in the channel forming region; wherein one of the plurality of second transistors contains silicon in the channel forming region; wherein one of the plurality of third transistors contains oxide semiconductor in the channel forming region; and wherein a first conductor configured to serve as the gate electrode of one of the plurality of third transistors and a first insulating system contained in one of the plurality of first capacitors extend vertically and are parallel to each other.

7. A semiconductor device comprising: a first circuit including: a plurality of planar transistors arranged adjacent to each other; and a memory cell on the first circuit, the memory cell including: a first transistor; a second transistor; and a first capacitor; wherein, One of the source and drain electrodes of the first transistor is electrically connected to an electrode of the first capacitor and the gate of the second transistor; wherein the plurality of planar transistors are formed on a silicon substrate; wherein the first semiconductor extends in a direction perpendicular to the silicon substrate and not in a direction parallel to the top surface of the silicon substrate; wherein the second semiconductor extends in the same direction perpendicular to the silicon substrate; wherein the first semiconductor includes a channel forming region of the first transistor; and wherein the second semiconductor includes a channel forming region of the second transistor.

8. A semiconductor device comprising: a first circuit including: a plurality of planar transistors arranged adjacent to each other; and a memory cell on the first circuit, the memory cell including: a first transistor; a second transistor; and a first capacitor; wherein, One of the source and drain electrodes of the first transistor is electrically connected to an electrode of the first capacitor and the gate electrode of the second transistor; wherein the plurality of planar transistors are formed on a semiconductor substrate; wherein the first semiconductor extends in a direction perpendicular to the semiconductor substrate and not in a direction parallel to the top surface of the semiconductor substrate; wherein the second semiconductor extends in the same direction perpendicular to the semiconductor substrate; wherein the first semiconductor includes a channel forming region of the first transistor; wherein the second semiconductor includes a channel forming region of the second transistor; and wherein at least one of the first semiconductor and the second semiconductor comprises an oxide semiconductor.

9. A semiconductor device comprising: a first circuit including: a plurality of transistors arranged adjacent to each other; and a memory cell on the first circuit, the memory cell including: a first transistor; a second transistor; and a first capacitor; wherein, One of the source and drain electrodes of the first transistor is electrically connected to an electrode of the first capacitor and the gate of the second transistor; wherein a channel forming region of one of the plurality of transistors is disposed in a semiconductor substrate; wherein the channel forming region of the transistor extends in a first direction; wherein the first semiconductor extends in a second direction intersecting the first direction, but does not extend in the first direction; wherein the second semiconductor extends in the second direction; wherein the first semiconductor includes the channel forming region of the first transistor; wherein the second semiconductor includes the channel forming region of the second transistor; and wherein at least one of the first semiconductor and the second semiconductor comprises an oxide semiconductor.

10. A semiconductor device comprising: a first circuit including: a plurality of planar transistors arranged adjacent to each other; and a memory cell on the first circuit, the memory cell including: a first transistor; a second transistor; and a first capacitor; wherein, One of the source and drain electrodes of the first transistor is electrically connected to an electrode of the first capacitor and the gate of the second transistor; wherein the plurality of planar transistors are formed on a silicon substrate; wherein the first semiconductor extends in a direction perpendicular to the silicon substrate and not in a direction parallel to the top surface of the silicon substrate; wherein the second semiconductor extends in the same direction perpendicular to the silicon substrate; wherein the first semiconductor includes a channel forming region of the first transistor; wherein the second semiconductor includes a channel forming region of the second transistor; wherein the first semiconductor has a columnar shape; and wherein the second semiconductor has a columnar shape.

11. A semiconductor device comprising: a first circuit including: a plurality of planar transistors arranged adjacent to each other; and a memory cell on the first circuit, the memory cell including: a first transistor; a second transistor; and a first capacitor; wherein, One of the source and drain electrodes of the first transistor is electrically connected to an electrode of the first capacitor and the gate of the second transistor; wherein the plurality of planar transistors are formed on a silicon substrate; wherein the first semiconductor extends in a direction perpendicular to the silicon substrate, but not in a direction parallel to the top surface of the silicon substrate; wherein the second semiconductor extends in the direction perpendicular to the silicon substrate; wherein the first semiconductor includes a channel forming region of the first transistor; wherein the second semiconductor includes a channel forming region of the second transistor; wherein the first conductor includes a region configured to serve as another electrode of the first capacitor; wherein the first conductor extends in a direction parallel to the top surface of the silicon substrate; wherein the second conductor includes a region configured to serve as the gate of the first transistor; and wherein the second conductor extends in the direction parallel to the top surface of the silicon substrate.

Images