Semiconductor device and methods of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a high-voltage electrostatic discharge (ESD) trigger device comprising a combination of an isolation region (e.g., a shallow trench isolation (STI) region) and a barrier protective oxide (RPO) structure on a doped region of a substrate. The RPO structure partially overlaps the STI region in a region between the doped collector and doped emitter of the high-voltage ESD trigger device. The width of the STI region partially overlapping the RPO structure allows charge carriers (e.g., holes) to move unimpeded from the region between the doped collector and doped emitter to the doped collector. As a result, the on-resistance (Ron) of the high-voltage ESD trigger device disclosed herein is reduced compared to high-voltage ESD trigger devices with other isolation region arrangements. Furthermore, the breakdown voltage is preserved to increase the operating efficiency and performance of the high-voltage ESD trigger device including the isolation region and the RPO structure arrangement.

Claims

1. A semiconductor device, comprising: Device circuitry; An electrostatic discharge (ESD) circuit is coupled to the device circuitry; The device includes an ESD trigger circuit coupled to the ESD circuit and the device circuitry, comprising: a substrate; a PNP ESD trigger device in the substrate, comprising: a p-type doped collector including a plurality of first doped regions; and a p-type doped emitter including a plurality of second doped regions; a shallow trench isolation (STI) region in the substrate and located between the p-type doped collector and the p-type doped emitter, wherein the STI region contacts the plurality of second doped regions, wherein the plurality of first doped regions include a p-type well region and a first p-type region within the p-type well region, and wherein the STI region is spaced apart from the first p-type region; and a barrier protective oxide (RPO) structure on the substrate, wherein the RPO structure is located above a portion of the p-type doped collector, a portion of the p-type doped emitter, and a portion of the STI region.

2. The semiconductor device of claim 1, wherein the plurality of first doped regions further includes a second p-type region within the first p-type region, and wherein the STI region is spaced apart from the second p-type region.

3. The semiconductor device of claim 2, wherein a portion of the p-type well region is located in the space between the edge of the STI region and the edge of the first p-type region.

4. The semiconductor device of claim 2, wherein a portion of the edge of the STI region is spaced apart from the p-type well region.

5. The semiconductor device of claim 1, wherein the plurality of second doped regions include an n-type well region, an n-type region within the n-type well region, and a p-type region within the n-type region, and wherein the RPO structure is located above the n-type well region and the n-type region.

6. A method of forming a semiconductor device, comprising: Multiple shallow trench isolation (STI) regions are formed in the substrate of the semiconductor device; A PNP electrostatic discharge (ESD) triggering device for the semiconductor device includes a p-type doped emitter formed in the substrate between a first STI region and a second STI region of a plurality of STI regions, wherein the first STI region and the second STI region are adjacent to a plurality of doped regions of the p-type doped emitter; a p-type doped collector formed in the substrate between a second STI region and a third STI region of the plurality of STI regions, wherein one or more doped regions of the p-type doped collector include a p-type well region and a first p-type region in the p-type well region, and wherein the second STI region and the third STI region are spaced apart from the first p-type region; and a plurality of barrier protection oxide (RPO) structures formed on the substrate, wherein a first RPO structure of the plurality of RPO structures partially overlaps the first STI region, a second RPO structure of the plurality of RPO structures partially overlaps the second STI region, and a third RPO structure of the plurality of RPO structures partially overlaps the third STI region.

7. The method of claim 6, wherein the second RPO structure overlaps the first space between the edge of the second STI region and the one or more doped regions of the p-type doped collector, and wherein the third RPO structure overlaps the second space between the edge of the third STI region and the one or more doped regions of the p-type doped collector.

8. The method of claim 6, further comprising forming an additional p-type doped emitter in the substrate for the PNP ESD triggering device, wherein the additional p-type doped emitter is formed between the third STI region and a fourth STI region of the plurality of STI regions, and wherein the third STI region and the fourth STI region are adjacent to a plurality of doped regions of the additional p-type doped emitter.

9. A semiconductor device, comprising: Base; The first plurality of shallow trench isolation (STI) regions in the substrate; The substrate contains a second plurality of STI regions, wherein the first plurality of STI regions have a larger dimension in a lateral direction along the top surface of the substrate than the second plurality of STI regions in that lateral direction; a first doped structure in the substrate and located between the first STI regions and the second STI regions of the first plurality of STI regions; a second doped structure in the substrate and located between the second STI regions of the first plurality of STI regions and the first STI regions of the second plurality of STI regions, wherein the second doped structure includes a p-type doped well and one or more doped regions in the p-type doped well, and the one or more doped regions include a first p-type region, and wherein the first STI regions of the second plurality of STI regions are spaced apart from the first p-type regions; a third doped structure in the substrate and located between the first STI regions and the second STI regions of the second plurality of STI regions, wherein the third doped structure includes a plurality of doped regions, and wherein the first STI regions and the second STI regions of the second plurality of STI regions are in contact with the plurality of doped regions; and a plurality of barrier protective oxide (RPO) structures on the substrate. The RPO structure in the plurality of RPO structures is located above a portion of the second doped structure and above a portion of the space between the first STI region and the one or more doped regions in the plurality of STI regions.

10. The semiconductor device as claimed in claim 9, further comprising: A first doped barrier region located in the substrate and below the first doped structure; And a second doped barrier region in the substrate and located below the third doped structure, wherein the first doped barrier region and the second doped barrier region are spaced apart from each other and arranged in the lateral direction.

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