Bandgap reference circuit

Abstract

A band-difference reference circuit comprising: a band-difference voltage generator and a detector. Band differential voltage generators, including: operational amplifiers, input circuits and load circuits. Detectors include: control circuits and reaction circuits. The two input terminals of the operational amplifier are connected to the first and second nodes, respectively, and the output terminals of the operational amplifier are connected to the bias node. The load circuit connects to the third node. The input circuit is connected to the first and second nodes. The control circuit acts to sense the signal according to the bias voltage. When the signal action is sensed, the reaction circuit connects the bias node to the supply voltage. When the sensing signal does not act, the reaction circuit disconnects that bias node to the supply voltage.

Description

[Technical Field]

[0001] The present invention relates to a voltage generating circuit, and more particularly to a bandgap reference circuit. [Previous Technology]

[0002] As is well known, the function of a bandgap reference circuit is to provide a stable bandgap voltage (VBG) that does not change with process technology or temperature. In the field of non-volatile memory, the bandgap voltage VBG can be used to generate more operating voltage.

[0003] For example, a non-volatile memory includes a charge pump (not shown). During programming, the charge pump receives a band differential voltage VBG and generates a programming voltage, causing the non-volatile memory to be programmed. There is a specific proportional relationship between the band differential voltage VBG and the programming voltage. Alternatively, during erasure, the charge pump receives a band differential voltage VBG and generates an erase voltage, causing the non-volatile memory to be erased. There is another specific proportional relationship between the band differential voltage VBG and the erase voltage. Because the band differential reference circuit can provide a stable band differential voltage VBG, the charge pump can also generate a stable programming voltage or erase voltage. [Summary of the Invention]

[0004] The invention relates to a band-difference reference circuit comprising: a band-difference voltage generator comprising: a mirror circuit, an operational amplifier, an input circuit and a load circuit, wherein a negative input terminal of the operational amplifier is connected to a first node of the mirror circuit An output of the arithmetic amplifier is connected to a bias node of the mirror circuit, the load circuit is connected to a third node of the mirror circuit, the input circuit is connected to the first node and the second node of the mirror circuit, the voltage of the third node is a band differential voltage; one of the bias node and the third node, the control circuit acts a sensing signal according to the one bias voltage of the biasing node or according to the band difference voltage of the third node; supply voltage, or the connection of such second node to that second supply voltage;

[0005] In order to have a better understanding of the above and other aspects of the present invention, better embodiments are hereafter, together with the appended diagrams, elaborated as follows: [Implementation Method]

[0007] Refer to FIG., which is shown as a bandgap voltage generator 100 . The band differential voltage generator 100 includes: mirroring circuit 12, operating amplifier 15, input circuit 20, and load circuit 30 .

[0008] The mirror circuit 12 includes three P-type field-effect transistors (FETs) M1, M2, and M3. The gates of transistors M1, M2, and M3 are interconnected and connected to a bias node (d). The sources of transistors M1, M2, and M3 receive a power supply voltage VDD. The drains of transistors M1, M2, and M3 are connected to nodes a, b, and c, respectively. The drain of transistor M1 can output a current IA, the drain of transistor M2 can output a current IB, and the drain of transistor M3 can output a current IC.

[0009] The output terminal of operational amplifier 15 is connected to the bias node d in the mirror circuit 12. The negative input terminal of operational amplifier 15 is connected to node a. The positive input terminal of operational amplifier 15 is connected to node b.

[0010] Input circuit 20 is connected to nodes a and b. Input circuit 20 includes two PNP bipolar junction transistors (PNP BJT transistors) Q1 and Q2. The base and collector of transistor Q1 receive the power supply voltage VSS, making transistor Q1 diode-connected. The base and collector of transistor Q2 receive the power supply voltage VSS, making transistor Q2 diode-connected. The power supply voltage VDD is greater than the power supply voltage VSS. For example, the power supply voltage VSS is ground. Additionally, the emitter of transistor Q1 is connected to node a, and a first resistor R1 is connected between the emitter of transistor Q2 and node b.

[0011] The load circuit 30 is connected to node c. The load circuit 30 includes a PNP bipolar transistor Q3. The base and collector of transistor Q3 receive the power supply voltage VSS. The emitter of transistor Q3 is connected to node c via a second resistor R2. The voltage at node c is the differential voltage VBG.

[0012] For example, in the differential voltage generator 100 in Figure 1, transistors M1, M2, and M3 have the same aspect ratio (W / L), the area of ​​transistor Q2 is m times the area of ​​transistor Q1, and the area of ​​transistor Q3 is the same as the area of ​​transistor Q1. Of course, the aspect ratio relationship between the three transistors M1, M2, and M3 can be modified according to actual needs. Similarly, the area relationship between the three transistors Q1, Q2, and Q3 can also be modified according to actual needs.

[0013] Since transistors M1, M2, and M3 have the same aspect ratio, the output current IA of transistor M1, the output current IB of transistor M2, and the output current IC of transistor M3 are the same. That is, IA=IB=IC---(1).

[0014] In addition, when the operational amplifier 15 has an infinite open loop gain, the voltage at the negative input terminal (VA) of the operational amplifier 15 will be equal to the voltage at the positive input terminal (VB). Therefore, --- (2). Wherein, VEB1 is the emitter-base voltage of transistor Q1, and VEB2 is the emitter-base voltage of transistor Q2.

[0015] Since transistors Q1 and Q2 form a diode connection and the area of ​​transistor Q2 is m times the area of ​​transistor Q1, therefore, , and.

[0016] Therefore, we can deduce ---(3) and ---(4).

[0017] In (3) and (4), IS is the saturation current of Q2 and VT is the thermal voltage.

[0018] Combining (1), (2), (3), and (4), the band difference voltage can be obtained as (5). Among them, VEB3 is the emitter-base voltage of transistor Q3.

[0019] As can be seen from equation (5), the differential voltage VBG can be regarded as the result of a base-emitter voltage VBE3 plus the thermal voltage VT multiplied by a constant C1 (temperature-independent scalar). That is, VBG = VBE3 + C1·VT, where C1 = (R2 / R1)·ln(m).

[0020] Because the base-emitter voltage VBE3 has a negative temperature coefficient, while the thermal voltage VT has a positive temperature coefficient, a voltage value with a zero temperature coefficient can be obtained by multiplying the thermal voltage VT by a coefficient C1 and adding it to the base-emitter voltage VBE3. That is, at any temperature, the band differential voltage VBG can be almost constant, so the band differential voltage VBG hardly changes with temperature.

[0021] As can be seen from the above description, when the differential voltage generator 100 is operating normally, it can generate a differential voltage VBG that does not change with temperature. However, when the power supply voltage VDD or VSS is disturbed, generating excessive power noise or ground noise, the differential voltage generator 100 may fail and thus be unable to output a normal differential voltage VBG.

[0022] For example, when a non-volatile memory is programmed or erased, the current inside the non-volatile memory is very large, causing disturbances in the power supply voltages VDD and VSS. When the power supply noise or ground noise is large, the differential voltage generator 100 will fail. When the differential voltage generator 100 fails, the non-volatile memory will be unable to generate normal programming and erasing voltages to perform programming and erasing operations.

[0023] When power supply noise or ground noise is high, the voltage VB at node b in the band differential voltage generator 100 will rise and the voltage VA at node a will fall, causing the voltage at the output of the operational amplifier 15 (i.e., the bias node d) to rise and the band differential voltage VBG to fall, resulting in the failure of the band differential voltage generator 100. Therefore, in order to prevent the band differential voltage generator 100 from failing during operation, this invention designs a band differential reference circuit. This invention further designs a detector in the band differential reference circuit. The detector can detect changes in the node voltages in the band differential voltage generator 100 to determine whether the band differential voltage generator 100 is about to fail and force the band differential voltage generator 100 to return to normal operation.

[0024] Please refer to Figure 2A, which illustrates a band differential reference circuit according to a first embodiment of the present invention. The band differential reference circuit 200 includes a band differential voltage generator 110 and a detector 210.

[0025] Compared to the band differential voltage generator 100 in Figure 1, the band differential voltage generator 110 of the present invention further includes: a P-type field-effect transistor M EN1. The connection relationship of the P-type field-effect transistor M EN1 will only be described below; the rest will not be repeated. The source of transistor M EN1 receives the power supply voltage VDD, the drain of transistor M EN1 is connected to the bias node d, and the gate of transistor M EN1 receives the enable signal EN. Of course, the band differential voltage generator 100 in Figure 1 can also be used in the band differential reference circuit 200 of the present invention.

[0026] When the enable signal EN is at a low logic level, it means that the enable signal EN is not activated. When the enable signal EN is not activated, transistor M EN1 is turned on, and the bias voltage (VD) of the bias node d is pulled up to the power supply voltage VDD, causing transistors M1, M2, and M3 to turn off, that is, the differential voltage generator 110 is disabled. Conversely, when the enable signal EN is at a high logic level, it means that the enable signal EN is activated. When the enable signal EN is activated, transistor M EN1 is turned off, and the bias voltage VD output by the operational amplifier 15 controls transistors M1, M2, and M3, causing the differential voltage generator 110 to operate normally and generate a differential voltage VBG.

[0027] The detector 210 includes a control circuit 212 and a response circuit 214. When the enable signal is not activated, the detector 210 is disabled. When the enable signal EN is activated, the detector 210 starts to operate.

[0028] Control circuit 212 receives enable signal EN. Control circuit 212 is connected to the bias node d of differential voltage generator 110 to detect changes in the bias voltage VD of bias node d and generate a sensing signal (S SEN) to response circuit 214. In addition, response circuit 214 is connected to the bias node d of differential voltage generator 110, and response circuit 214 appropriately adjusts the bias voltage VD of bias node d according to the sensing signal S SEN.

[0029] For example, when power supply noise or ground noise is high, the bias voltage VD at the output of the operational amplifier 15 in the band differential voltage generator 110 (i.e., bias node d) rises. Based on the change in bias voltage VD, the control circuit 212 selectively activates the sensing signal S SEN, causing the response circuit 214 to lower the bias voltage VD at bias node d. Several examples of the detector 210 applied in the band differential reference circuit 200 of the first embodiment are presented below.

[0030] Please refer to Figure 2B, which illustrates a first example of the detector 210 in the bandgap reference circuit 200 of the first embodiment. The detector 210 includes a control circuit 212a and a response circuit 214a. The control circuit 212a includes a P-type field-effect transistor MEN2 and a current control path 215a. The current control path 215a includes a P-type field-effect transistor MPA and a pull-down circuit 216a. The pull-down circuit 216a includes an N-type field-effect transistor MNA and a resistor RA.

[0031] The source of transistor M EN2 receives the power supply voltage V DD, the drain of transistor M EN2 is connected to the sensing node (s), and the gate of transistor M EN2 receives the enable signal EN. The voltage on the sensing node s is used as the sensing signal (S SEN).

[0032] In the current control path 215a, the source of transistor MPA receives the power supply voltage VDD, the drain of transistor MPA is connected to the sensing node s, and the gate of transistor MPA is connected to the bias node d in the differential voltage generator 110. Additionally, pull-down circuit 216a is connected between the sensing node s and the power supply voltage VSS. The first terminal of resistor RA is connected to the sensing node s. The drain of transistor MNA is connected to the second terminal of resistor RA, the source of transistor MNA receives the power supply voltage VSS, and the gate of transistor MNA receives the enable signal EN.

[0033] The reaction circuit 214a includes an inverter 218a and an N-type field-effect transistor MNB. The transistor MNB can be regarded as a switch transistor. The input terminal of the inverter 218a is connected to the sensing node s. The drain of the transistor MNB is connected to the bias node d, the source of the transistor MNB receives the power supply voltage VSS, and the gate of the transistor MNB is connected to the output terminal of the inverter 218a.

[0034] As shown in Figure 2B, when the enable signal EN is not activated (low logic level), transistor MEN2 is turned on, transistor MNA is turned off, the voltage level of the sensing signal SSEN is the power supply voltage VDD, and the control current ICTRL on the current control path 215a is zero. Inverter 218a outputs a low logic level to the gate of transistor MNB, causing transistor MNB to turn off. In other words, when the enable signal EN is not activated (low logic level), the sensing signal SSEN of sensing node s cannot change, indicating that detector 210 is disabled.

[0035] When the enable signal EN is activated (high logic level), the differential voltage generator 110 starts operating. In the control circuit 212a, transistor MEN2 is turned off, and transistor MNA is turned on. At this time, the bias voltage VD at the bias node d can control the control current ICTRL generated by transistor MPA. The change in the control current ICTRL can change the voltage level of the sensing signal SSEN.

[0036] When the differential voltage generator 110 is operating normally, the transistor MPA is turned on, making the voltage level of the sensing signal SSEN greater than the transition point of the inverter 218a, indicating that the sensing signal SSEN has not been activated. The voltage at the output of the inverter 218a is at a low logic level, causing the transistor MNB to turn off.

[0037] When power supply noise or ground noise is high, the voltage at the output of the operational amplifier 15 in the differential voltage generator 110 (i.e., the bias node d) rises, causing the control current ICTRL to decrease, which in turn causes the voltage level of the sensing signal SSEN to drop. When the voltage level of the sensing signal SSEN is lower than the transition point of the inverter 218a, it means that the sensing signal SSEN is activated, causing the output of the inverter 218a to change to a high logic level, and the transistor MNB turns on. At this time, the switching transistor MNB of the reaction circuit 214a connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 214a stops the bias voltage VD from rising further and controls the bias voltage VD to decrease, so that the differential voltage generator 110 returns to normal operation.

[0038] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M NB to turn off. The switching transistor M NB of the reaction circuit 214a disconnects the bias node d to the power supply voltage V SS.

[0039] Please refer to Figure 2C, which is a second example of the detector 210 in the bandgap reference circuit 200 of the first embodiment. The detector 210 includes a control circuit 212b and a response circuit 214b. The control circuit 212b includes a P-type field-effect transistor M EN2 and a current control path 215b. The current control path 215b includes a P-type field-effect transistor MPA and a pull-down circuit 216b. The pull-down circuit 216b includes an N-type field-effect transistor M NC.

[0040] In the current control path 215b, the source of transistor MPA receives the power supply voltage VDD, the drain of transistor MPA is connected to the sensing node s, and the gate of transistor MPA is connected to the bias node d in the differential voltage generator 110. Additionally, pull-down circuit 216b is connected between the sensing node s and the power supply voltage VSS. The drain of transistor MNC is connected to the sensing node s, the source of transistor MNC receives the power supply voltage VSS, and the gate of transistor MNC receives the enable signal EN. Essentially, transistor MNC is a weak N-type FET; the size of transistor MNC is smaller than that of transistor MPA, and the internal resistance of transistor MNC is greater than that of transistor MPA.

[0041] The reaction circuit 214b includes a P-type field-effect transistor M PB. The transistor M PB can be regarded as a switching transistor. The source of the transistor M PB is connected to the bias node d, the drain of the transistor M PB receives the power supply voltage V SS, and the gate of the transistor M PB is connected to the sensing node s.

[0042] As shown in Figure 2C, when the enable signal EN is not activated (low logic level), the detector 210 is disabled. Conversely, when the enable signal EN is activated (high logic level), transistor MEN2 is turned off, and transistor MNC is turned on. At this time, the bias voltage VD at the bias node d can control the control current ICTRL generated by transistor MPA. The change in the control current ICTRL alters the voltage level of the sensing signal SSEN.

[0043] When the differential voltage generator 110 is operating normally, the transistor MPA is turned on, so that the voltage difference between the voltage level of the sensing signal SSEN and the bias node d is greater than the threshold voltage of the transistor MPB, which means that the sensing signal SSEN has not been activated, and the transistor MPB is turned off.

[0044] When power supply noise or ground noise is high, the voltage at the output of the operational amplifier 15 in the differential voltage generator 110 (i.e., the bias node d) rises, causing the control current ICTRL to decrease and the voltage level of the sensing signal SSEN to decrease. When the voltage difference between the voltage level of the sensing signal SSEN and the bias node d is less than the threshold voltage of the transistor PB, it means that the sensing signal SSEN is activated and the transistor PB turns on. At this time, the switching transistor PB of the response circuit 214b connects the bias node d to the power supply voltage VSS. Therefore, the response circuit 214b stops the bias voltage VD from rising and controls the bias voltage VD to decrease, so that the differential voltage generator 110 returns to normal operation.

[0045] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M PB to turn off. The switching transistor M PB of the reaction circuit 214b disconnects the bias node d to the power supply voltage V SS.

[0046] In addition to the two detector 210 examples in Figures 2B and 2C, the detector 210 can be modified further. For example, connecting the control circuit 212a of Figure 2B to the response circuit 214b of Figure 2C can form a third example of the detector 210 in the first embodiment of the band difference reference circuit 200. Similarly, connecting the control circuit 212b of Figure 2C to the response circuit 214a of Figure 2B can form a fourth example of the detector 210 in the first embodiment of the band difference reference circuit 200. Of course, the pull-down circuits 216a and 216b in Figures 2B and 2C can also be interchanged to form other examples of the detector 210 in the first embodiment of the band difference reference circuit 200.

[0047] In the band difference reference circuit 200 of the first embodiment, the detector 210 detects whether the bias voltage VD at the output terminal of the operational amplifier 15 (i.e., bias node d) is abnormal, and dynamically adjusts the bias voltage VD of bias node d using the reaction circuit 214. Of course, in other embodiments, the voltages of other nodes can also be detected, and the bias voltage VD of bias node d can be dynamically adjusted.

[0048] Please refer to Figure 3A, which illustrates a band differential reference circuit according to a second embodiment of the present invention. The band differential reference circuit 300 includes a band differential voltage generator 110 and a detector 310. The structure of the band differential voltage generator 110 will not be described in detail here.

[0049] As shown in Figure 3A, the detector 310 includes a control circuit 312 and a response circuit 314. When the enable signal is not activated, the detector 310 is disabled. When the enable signal EN is activated, the detector 310 starts to operate.

[0050] Control circuit 312 receives enable signal EN. Control circuit 312 is connected to node c of differential voltage generator 110 to detect changes in differential voltage VBG and generate sensing signal SSEN to response circuit 314. Furthermore, response circuit 314 is connected to bias node d of differential voltage generator 110, and response circuit 314 appropriately adjusts the bias voltage VD of bias node d according to sensing signal SSEN.

[0051] For example, when power supply noise or ground noise is high, the band difference voltage VBG at node c decreases, and the bias voltage VD at bias node d increases. Therefore, based on the change in band difference voltage VBG, the control circuit 312 selectively activates the sensing signal SSEN, causing the response circuit 314 to lower the bias voltage VD at bias node d. Several examples of the detector 310 are presented below.

[0052] Please refer to Figure 3B, which illustrates a first example of the detector 310 in the bandgap reference circuit 300 of the second embodiment. The detector 310 includes a control circuit 312a and a response circuit 314a. The control circuit 312a includes a P-type field-effect transistor MEN3, an N-type field-effect transistor MND, a current mirror 316a, and current control paths 315a and 317a. The response circuit 314a includes a P-type field-effect transistor MPE and an inverter 318a. The transistor MPE can be considered as a switching transistor.

[0053] In the reaction circuit 314a, the input terminal of the inverter 318a is connected to the sensing node s. The source of the transistor MPE is connected to the bias node d, the drain of the transistor MPE receives the power supply voltage VSS, and the gate of the transistor MPE is connected to the output terminal of the inverter 318a.

[0054] In the control circuit 312a, the source of transistor MEN3 receives the power supply voltage VDD, the drain of transistor MEN3 is connected to node e, and the gate of transistor MEN3 receives the enable signal EN. The drain of transistor MND is connected to the sensing node s, the source of transistor MND receives the power supply voltage VSS, and the gate of transistor MND receives the inverted enable signal ZEN. The enable signal EN and the inverted enable signal ZEN are complementary. For example, inverter 319 receives the enable signal EN and generates the inverted enable signal ZEN.

[0055] The current mirror 316a includes a P-type field-effect transistor MPC and an MPD. The source of the transistor MPD receives the power supply voltage VDD, the drain of the transistor MPD is connected to node e, and the gate of the transistor MPD is connected to node e. Furthermore, the source of the transistor MPC receives the power supply voltage VDD, the drain of the transistor MPC is connected to the sensing node s, and the gate of the transistor MPC is connected to node e. Node e is the current input terminal of the current mirror 316a, and the sensing node s is the current mirroring terminal of the current mirror 316a.

[0056] The current control path 317a includes an N-type field-effect transistor M NG and a current source IX. The drain of the transistor M NG is connected to node e, and the gate of the transistor M NG receives the enable signal EN. The first terminal of the current source IX is connected to the source of the transistor M NG, and the second terminal of the current source IX receives the power supply voltage V SS. The current source IX can generate a constant current IX.

[0057] The current control path 315a includes an N-type field-effect transistor MNE and MNF. The drain of transistor MNE is connected to the sensing node s, and the gate of transistor MNE is connected to node c in the reference voltage generator 110. The drain of transistor MNF is connected to the source of transistor MNE, the gate of transistor MNF receives the enable signal EN, and the source of transistor MNF receives the power supply voltage VSS.

[0058] As shown in Figure 3B, when the enable signal EN is not activated (low logic level), the detector 310 is disabled. Conversely, when the enable signal EN is activated (high logic level), the inverting enable signal ZEN is at a low logic level, transistors MND and MEN3 are turned off, and transistors MNF and MNG are turned on. At this time, the band difference voltage VBG at node c can control the control current ICTRL generated by transistor MNE. The change in the control current ICTRL alters the voltage level of the sensing signal SSEN.

[0059] When the differential voltage generator 110 is operating normally, the differential voltage VBG controls the transistor MNE, making the control current ICTRL approximately equal to the current IX. At this time, the voltage level of the sensing signal SSEN is less than the transition point of the inverter 318a, indicating that the sensing signal SSEN is not activated. The voltage at the output of the inverter 318a is at a high logic level, causing the transistor MPE to turn off.

[0060] When power supply noise or ground noise is high, the differential voltage VBG decreases, causing the control current ICTRL to decrease, and the voltage level of the sensing signal SSEN increases. Therefore, when the voltage level of the sensing signal SSEN is greater than the transition point of the inverter 318a, it indicates that the sensing signal SSEN is activated, and the inverter 318a outputs a low logic level, causing the transistor MPE to turn on. At this time, the switching transistor MPE of the reaction circuit 314a connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 314a stops the bias voltage VD from continuing to rise, and controls the bias voltage VD to decrease, causing the differential voltage generator 110 to return to normal operation.

[0061] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M PE to turn off. The switching transistor M PE of the reaction circuit 314a disconnects the bias node d to the power supply voltage V SS.

[0062] Similar to the two reaction circuits 214a and 214b in Figures 2B and 2C, they can be interchanged. Please refer to Figure 3C, which shows another reaction circuit of the detector 310 in the band difference reference circuit 300 of the second embodiment. Combining the control circuit 312a of Figure 3B with the reaction circuit 314b of Figure 3C can form a second example of the detector 310 in the band difference reference circuit 300 of the second embodiment.

[0063] The reaction circuit 314b includes an N-type field-effect transistor MNH, the drain of the transistor MNH is connected to the bias node d, the source of the transistor MNH receives the power supply voltage VSS, and the gate of the transistor MNH is connected to the sensing node s.

[0064] When power supply noise or ground noise is high, the differential voltage VBG decreases, causing the control current ICTRL to decrease, and the voltage level of the sensing signal SSEN to rise. Therefore, when the voltage level of the sensing signal SSEN is greater than the threshold voltage of the transistor MNH, it means that the sensing signal SSEN is activated, and the transistor MNH turns on. At this time, the switching transistor MNH of the reaction circuit 314b connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 314b stops the bias voltage VD from rising further and controls the bias voltage VD to decrease, so that the differential voltage generator 110 returns to normal operation.

[0065] Please refer to Figure 3D, which illustrates a third example of the detector 310 in the band difference reference circuit 300 of the second embodiment. The detector 310 includes a control circuit 312c and a response circuit 314c.

[0066] The control circuit 312c includes a P-type field-effect transistor MEN4, a P-type field-effect transistor MPF, a current mirror 316c, and current control paths 315c and 317c. The reaction circuit 314c includes an N-type field-effect transistor MPI and an inverter 318c. The current control paths 315c and 317c are the same as the current control paths 315a and 317a in Figure 3A, and will not be described again here.

[0067] In the reaction circuit 314c, the input terminal of the inverter 318c is connected to the sensing node s. The drain of the transistor MNI is connected to the bias node d, the source of the transistor MNI receives the power supply voltage VSS, and the gate of the transistor MNI is connected to the output terminal of the inverter 318c. The transistor MNI can be regarded as a switch transistor.

[0068] In the control circuit 312c, the source of transistor MEN4 receives the power supply voltage VDD, the drain of transistor MEN4 is connected to node f, and the gate of transistor MEN4 receives the enable signal EN. The source of transistor MPF receives the power supply voltage VDD, the drain of transistor MPF is connected to sensing node s, and the gate of transistor MPF receives the enable signal EN.

[0069] The current mirror 316c includes P-type field-effect transistors MPG and MPH. The source of transistor MPG receives the power supply voltage VDD, the drain of transistor MPG is connected to node f, and the gate of transistor MPG is connected to node f. The source of transistor MPH receives the power supply voltage VDD, the drain of transistor MPH is connected to sensing node s, and the gate of transistor MPH is connected to node f. Node f is the current input terminal of the current mirror 316c, and sensing node s is the current mirror emitter of the current mirror 316c. Additionally, a current control path 315c is connected between node f and the power supply voltage VSS. A current control path 317c is connected between sensing node s and the power supply voltage VSS.

[0070] As shown in Figure 3D, when the enable signal EN is not activated (low logic level), the detector 310 is disabled. Conversely, when the enable signal EN is activated (high logic level), transistors MPF and MEN4 are turned off, while transistors MNF and MNG are turned on. At this time, the band difference voltage VBG at node c can control the control current ICTRL generated by transistor MNE. Changes in the control current ICTRL can alter the voltage level of the sensing signal SSEN.

[0071] When the differential voltage generator 110 is operating normally, the differential voltage VBG controls the transistor MNE, making the control current ICTRL approximately equal to the current IX. At this time, the voltage level of the sensing signal SSEN is greater than the transition point of the inverter 318c, indicating that the sensing signal SSEN is not activated. The voltage at the output of the inverter 318c is at a low logic level, causing the transistor MNI to turn off.

[0072] When power supply noise or ground noise is high, the differential voltage VBG drops, causing the control current ICTRL to drop, and the voltage level of the sensing signal SSEN to drop. Therefore, when the sensing signal SSEN is less than the switching point of the inverter 318c, it indicates that the sensing signal SSEN is activated.

[0073] Furthermore, the inverter 318c outputs a high logic level, causing the transistor MNI to turn on. At this time, the switching transistor MNI of the reaction circuit 314c connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 314c stops the bias voltage VD from rising further and controls the bias voltage VD to fall, causing the differential voltage generator 110 to resume normal operation.

[0074] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M NI to turn off. The switching transistor M NI of the reaction circuit 314c disconnects the bias node d to the power supply voltage V SS.

[0075] Similar to the two reaction circuits 214a and 214b in Figures 2B and 2C, they can be interchanged. Please refer to Figure 3E, which illustrates another reaction circuit of the detector 310 in the band difference reference circuit 300 of the second embodiment. Combining the control circuit 312c of Figure 3D with the reaction circuit 314d of Figure 3E can form a fourth example of the detector 310.

[0076] The reaction circuit 314d includes a P-type field-effect transistor MPI, the source of the transistor MPI is connected to the bias node d, the drain of the transistor MPI receives the power supply voltage VSS, and the gate of the transistor MPI is connected to the sensing node s.

[0077] When power supply noise or ground noise is high, the differential voltage VBG drops, causing the control current ICTRL to drop, and the sensing signal SSEN rises. Therefore, when the voltage difference between the sensing signal SSEN and the bias voltage VD is less than the threshold voltage of the transistor MPI, it means that the sensing signal SSEN is activated, and the transistor MPI turns on. At this time, the switching transistor MPI of the reaction circuit 314d connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 314d stops the bias voltage VD from rising further and controls the bias voltage VD to drop, so that the differential voltage generator 110 returns to normal operation.

[0078] In the band difference reference circuit 300 of the second embodiment, the detector 310 detects whether the band difference voltage VBG at node c in the band difference voltage generator 110 is abnormal, and dynamically adjusts the bias voltage VD at the bias node d using the reaction circuit 314. Of course, in other embodiments, the voltage difference between node c and bias node d can also be detected simultaneously, and the bias voltage VD at bias node d can be dynamically adjusted.

[0079] Please refer to Figure 4A, which illustrates a band differential reference circuit according to a third embodiment of the present invention. The band differential reference circuit 400 includes a band differential voltage generator 110 and a detector 410. The detector 410 includes a control circuit 412 and a response circuit 414. When the enable signal is not activated, the detector 410 is disabled. When the enable signal EN is activated, the detector 410 begins to operate.

[0080] Control circuit 412 receives enable signal EN. Control circuit 412 is connected to node c and bias node d of differential voltage generator 110 to detect the voltage difference change between differential voltage VBG and bias voltage VD, and generates sensing signal SSEN to response circuit 414. Furthermore, response circuit 414 is connected to bias node d of differential voltage generator 110. When sensing signal SSEN is activated, response circuit 414 appropriately adjusts the bias voltage VD of bias node d.

[0081] For example, when power supply noise or ground noise is high, the band difference voltage VBG at node c decreases while the bias voltage VD at bias node d increases. Therefore, based on the changes in bias voltage VD and band difference voltage VBG, control circuit 412 selectively activates the sensing signal SSEN, causing response circuit 414 to lower the bias voltage VD at bias node d. Several examples of detector 410 are presented below.

[0082] Please refer to Figure 4B, which illustrates a first example of the detector 410 in the band difference reference circuit 400 of the third embodiment. The detector 410 includes a control circuit 412a and a response circuit 414a. The control circuit 412a includes a current control path 415a and a comparator 416a. The current control path 415a includes a P-type field-effect transistor MPJ, an N-type field-effect transistor MNJ, and an N-type field-effect transistor MNK. The response circuit 414a includes an N-type field-effect transistor MNL and an inverter 418a.

[0083] In the reaction circuit 414a, the input terminal of the inverter 418a is connected to the sensing node s. The drain of the transistor MNL is connected to the bias node d, the source of the transistor MNL receives the power supply voltage VSS, and the gate of the transistor MNL is connected to the output terminal of the inverter 418a. The transistor MNL can be regarded as a switch transistor.

[0084] In the current control path 415a of the control circuit 412a, the source of transistor MPJ ​​receives the power supply voltage VDD, and the gate of transistor MPJ ​​receives the inverted enable signal ZEN. The drain of transistor MNJ is connected to the drain of transistor MPJ, the source of transistor MNJ is connected to node h, and the gate of transistor MNJ is connected to the bias node d. The drain of transistor NK is connected to node h, the source of transistor NK is connected to the power supply voltage VSS, and the gate of transistor MNJ receives the power supply voltage VDD. Furthermore, the positive input terminal of comparator 416a is connected to node c, the negative input terminal of comparator 416a is connected to node h, and the output terminal of comparator 416a is connected to sensing node s to generate a sensing signal SSEN. Among them, transistor M NK is a weak N-type FET. The size of transistor M NK is smaller than that of transistor M NJ, and the internal resistance of transistor M NK is greater than that of transistor M NJ.

[0085] As shown in Figure 4B, when the enable signal EN is not activated (low logic level), the detector 410 is disabled. Furthermore, when the enable signal EN is activated (high logic level), the inverting enable signal ZEN is at a low logic level, and the transistor MPJ ​​turns on. At this time, the bias voltage VD at the bias node d can control the control current ICTRL generated by the transistor MNJ. The change in the control current ICTRL can change the voltage VH at node h.

[0086] When the differential voltage generator 110 is operating normally, the voltage VH at node h is the bias voltage (VDVgs), where Vgs is the gate-source voltage of transistor MNJ, and the voltage VH at node h is less than the differential voltage VBG. At this time, the sensing signal SSEN at the output of comparator 416a is at a high logic level, indicating that the sensing signal SSEN is not activated, and the voltage at the output of inverter 418a is at a low logic level, causing transistor MNJ to turn off.

[0087] When power supply noise or ground noise is high, the band differential voltage VBG decreases, and the bias voltage VD increases. Due to the increase in bias voltage VD, the control current ICTRL increases, and the voltage VH at node h increases. Therefore, when the voltage VH at node h exceeds the band differential voltage VBG, the sensing signal SSEN at the output of comparator 416a is at a low logic level, indicating that the sensing signal SSEN is activated, and the voltage at the output of inverter 418a is at a high logic level, causing transistor MNL to turn on. At this time, the switching transistor MNL of the reaction circuit 414a connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 414a stops the bias voltage VD from continuing to rise and controls the bias voltage VD to decrease, causing the band differential voltage generator 110 to return to normal operation.

[0088] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M NL to turn off. The switching transistor M NL of the reaction circuit 414a disconnects the bias node d to the power supply voltage V SS.

[0089] Similar to the two reaction circuits 214a and 214b in Figures 2B and 2C, they can be interchanged. Please refer to Figure 4C, which shows another reaction circuit of the detector 410 in the band difference reference circuit 400 of the third embodiment. Combining the control circuit 412a of Figure 4B with the reaction circuit 414b of Figure 4C can form a second example of the detector 410 in the band difference reference circuit 400 of the third embodiment.

[0090] The reaction circuit 414b includes a P-type field-effect transistor MPK. The source of the transistor MPK is connected to the bias node d, the drain of the transistor MPK receives the power supply voltage VSS, and the gate of the transistor MPK is connected to the sensing node s. The transistor MPK can be regarded as a switch transistor.

[0091] When power supply noise or ground noise is high, the sensing signal S SEN output by comparator 416 is at a low logic level, indicating that the sensing signal S SEN is activated and the transistor MKP turns on. At this time, the switching transistor MKP of the reaction circuit 414a connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 414b stops the bias voltage VD from rising and controls the bias voltage VD to fall, so that the differential voltage generator 110 returns to normal operation.

[0092] Please refer to Figure 4D, which illustrates a third example of the detector 310 in the band difference reference circuit 400 of the third embodiment. The detector 410 includes a control circuit 412c and a response circuit 414a. The control circuit 412c includes a current control path 415c and a comparator 416a. Only the current control path 415c will be described below.

[0093] In the current control path 415c of the control circuit 412c, the source of transistor MPL is connected to the bias node d to receive the bias voltage VD, and the gate of transistor MPL receives the inverted enable signal ZEN. The source of transistor MPO is connected to the drain of transistor MPL, the drain of transistor MPO is connected to node i, and the gate of transistor MPO is connected to node i. Transistor MPO is diode connected. The drain of transistor MNN is connected to node i, the source of transistor MNN is connected to the power supply voltage VSS, and the gate of transistor MNN receives the power supply voltage VDD. Furthermore, the positive input terminal of comparator 416a is connected to node c, the negative input terminal of comparator 416a is connected to node i, and the output terminal of comparator 416a is connected to the sensing node s to generate the sensing signal SSEN. Among them, transistor MNN is a weak N-type FET.

[0094] As shown in Figure 4D, when the enable signal EN is not activated (low logic level), the detector 410 is disabled. When the enable signal EN is activated (high logic level), the inverting enable signal ZEN is at a low logic level, and the transistor MPL (turns on). At this time, the bias voltage VD of the bias node d can control the voltage VI of the node i.

[0095] When the differential voltage generator 110 is operating normally, the voltage VI at node i is the bias voltage (VDVT), where VT is the threshold voltage of transistor MNM, and the voltage VI at node i is less than the differential voltage VBG. At this time, the sensing signal SSEN at the output of comparator 416a is at a high logic level, indicating that the sensing signal SSEN is not activated, and the voltage at the output of inverter 418a is at a low logic level, causing transistor MNM to turn off.

[0096] When power supply noise or ground noise is high, the band differential voltage VBG decreases, and the bias voltage VD increases. Due to the increase in bias voltage VD, the control current ICTRL increases, and the voltage VI at node i increases. Therefore, when the voltage VI at node i exceeds the band differential voltage VBG, the sensing signal SSEN at the output of comparator 416a is at a low logic level, indicating that the sensing signal SSEN is activated, and the voltage at the output of inverter 418a is at a high logic level, causing transistor MNL to turn on. At this time, the switching transistor MNL of the reaction circuit 414a connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 414a stops the bias voltage VD from continuing to rise and controls the bias voltage VD to decrease, causing the band differential voltage generator 110 to return to normal operation.

[0097] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M NL to turn off. The switching transistor M NL of the reaction circuit 414a disconnects the bias node d to the power supply voltage V SS.

[0098] Similarly, the control circuit 412c in Figure 4D can be combined with the reaction circuit 414b in Figure 4C to become the fourth example of the detector 410 in the band difference reference circuit 400 of the third embodiment.

[0099] Please refer to Figure 4E, which illustrates the fifth example of the detector 410 in the band difference reference circuit 400 of the third embodiment. The detector 410 includes a control circuit 412d and a response circuit 414a. Only the control circuit 412d is described below. The control circuit 412d includes a current mirror 413d, a comparator 416a, and current control paths 415d and 417d.

[0100] The current mirror 413d includes N-type field-effect transistors MNP and MNQ. The source of transistor MNP receives the power supply voltage VSS, the drain of transistor MNP is connected to node k, and the gate of transistor MNP is connected to node k. The source of transistor MNQ receives the power supply voltage VSS, the drain of transistor MNQ is connected to node j, and the gate of transistor MNQ is connected to node k. Node k is the current input terminal of the current mirror 413d, and node j is the current mirror output terminal of the current mirror 413d.

[0101] The current control path 417d includes a current source IX, which is connected between the power supply voltage VDD and node k, and the current source IX can generate a certain current IX.

[0102] The current control path 415d includes a P-type field-effect transistor MPM and an N-type field-effect transistor MNQ. The source of transistor MPM receives the power supply voltage VDD, and the gate of transistor MPM receives the inverted enable signal ZEN. The drain of transistor MNQ is connected to the drain of transistor MPM, the gate of transistor MNQ is connected to the bias node d, and the source of transistor MNQ is connected to node j. Furthermore, the positive input of comparator 416a is connected to node c, the negative input of comparator 416a is connected to node j, and the output of comparator 416a is connected to sensing node s to generate a sensing signal SSEN.

[0103] As shown in Figure 4E, when the enable signal EN is not activated (low logic level), the detector 410 is disabled. When the enable signal EN is activated (high logic level), the inverting enable signal ZEN is at a low logic level, and the transistor MPM turns on. At this time, the bias voltage VD of the bias node d can control the voltage VJ of the node j.

[0104] When the differential voltage generator 110 is operating normally, the voltage VJ at node j is the bias voltage (VDVgs), where Vgs is the gate-source voltage of transistor MNNO, and the voltage VJ at node j is less than the differential voltage VBG. At this time, the sensing signal SSEN at the output of comparator 416a is at a high logic level, indicating that the sensing signal SSEN is not activated, and the voltage at the output of inverter 418a is at a low logic level, causing transistor MNNO to turn off.

[0105] When power supply noise or ground noise is high, the band differential voltage VBG decreases, and the bias voltage VD increases. Due to the increase in bias voltage VD, the control current ICTRL increases, and the voltage VJ at node j increases. Therefore, when the voltage VJ at node j exceeds the band differential voltage VBG, the sensing signal SSEN at the output of comparator 416a is at a low logic level, indicating that the sensing signal SSEN is activated, and the voltage at the output of inverter 418a is at a high logic level, causing transistor MNL to turn on. At this time, the switching transistor MNL of the reaction circuit 414a connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 414a stops the bias voltage VD from continuing to rise and controls the bias voltage VD to decrease, causing the band differential voltage generator 110 to return to normal operation.

[0106] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M NL to turn off. The switching transistor M NL of the reaction circuit 414a disconnects the bias node d to the power supply voltage V SS.

[0107] Similarly, the control circuit 412d in Figure 4E can be combined with the reaction circuit 414b in Figure 4C to become the sixth example of the detector 410 in the differential reference circuit 400 of the third embodiment.

[0108] Please refer to Figure 4F, which shows the seventh example of the detector 410 in the band difference reference circuit 400 of the third embodiment.

[0109] The detector 410 includes a control circuit 412e and a response circuit 414a. The control circuit 412e includes a current control path 415e and a comparator 416a. The current control path 415e includes a P-type field-effect transistor MPN, an N-type field-effect transistor MNR, and an N-type field-effect transistor MND. Only the current control path 415e will be described below; the others will not be elaborated upon.

[0110] In the current control path 415e of the control circuit 412e, the source of transistor MPN is connected to the bias node d to receive the bias voltage VD, the gate of transistor MPN is connected to node l, and the drain of transistor MPN is connected to node l. Transistor MPN is diode connected. The drain of transistor MNR is connected to node l, and the gate of transistor MNR receives the power supply voltage VDD. The drain of transistor MNS is connected to the source of transistor MNR, the source of transistor MNS receives the power supply voltage VSS, and the gate of transistor MNS receives the enable signal EN. Furthermore, the positive input terminal of comparator 416a is connected to node c, the negative input terminal of comparator 416a is connected to node l, and the output terminal of comparator 416a is connected to the sensing node s to generate the sensing signal SSEN. Among them, transistor MNR is a weak N-type FET.

[0111] As shown in Figure 4F, when the enable signal EN is not activated (low logic level), the sensing signal S_SEN of sensing node s cannot change, indicating that detector 410 is disabled. When the enable signal EN is activated (high logic level), transistor M_NS (turn on). At this time, the bias voltage VD of bias node d can control the voltage VL of node 1.

[0112] When the differential voltage generator 110 is operating normally, the voltage VL at node 1 is the bias voltage (VDVT), where VT is the threshold voltage of transistor MPN, and the voltage VL at node 1 is less than the differential voltage VBG. At this time, the sensing signal SSEN at the output of comparator 416a is at a high logic level, indicating that the sensing signal SSEN is not activated, and the voltage at the output of inverter 418a is at a low logic level, causing transistor MNL to turn off.

[0113] When power supply noise or ground noise is high, the band differential voltage VBG decreases, and the bias voltage VD increases. Due to the increase in bias voltage VD, the control current ICTRL increases, and the voltage VL at node 1 increases. Therefore, when the voltage VL at node 1 exceeds the band differential voltage VBG, the sensing signal SSEN at the output of comparator 416a is at a low logic level, indicating that the sensing signal SSEN is activated, and the voltage at the output of inverter 418a is at a high logic level, causing transistor MNL to turn on. At this time, the switching transistor MNL of the reaction circuit 414a connects the bias node d to the power supply voltage VSS. Therefore, the reaction circuit 414a stops the bias voltage VD from continuing to rise and controls the bias voltage VD to decrease, causing the band differential voltage generator 110 to return to normal operation.

[0114] When the differential voltage generator 110 resumes normal operation, the sensing signal S SEN does not activate, causing the transistor M NL to turn off. The switching transistor M NL of the reaction circuit 414a disconnects the bias node d to the power supply voltage V SS.

[0115] Similarly, the control circuit 412e in Figure 4F can be combined with the reaction circuit 414b in Figure 4C to become the eighth example of the detector 410 in the band difference reference circuit 400 of the third embodiment.

[0116] According to the above description, when the differential voltage generator 110 fails, the control circuits 212, 312, and 412 sense the action signal S SEN, causing the reaction circuits 214, 314, and 414 to connect the bias node d in the bias voltage generator 110 to the power supply voltage V SS, so as to force the differential voltage generator 110 to return to normal operation.

[0117] In fact, using the detector of the present invention, other nodes inside the differential voltage generator 110 can also be connected to the corresponding power supply voltage to force the differential voltage generator 110 to return to normal operation.

[0118] For example, when the differential voltage generator 110 fails, the voltage VB at node b will rise. At this time, designing a reaction circuit to connect node b to the power supply voltage VSS can also force the differential voltage generator 110 to return to normal operation. The following explanation uses the detector in Figure 5 as an example.

[0119] Please refer to Figure 5, which illustrates the detector 510 in the band difference reference circuit of the fourth embodiment of the present invention. The band difference reference circuit of the fourth embodiment includes a band difference voltage generator 110 and a detector 510. Compared with the detector 210 in Figure 2B, in the band difference reference circuit of the fourth embodiment, the drain of the switching transistor MNB in ​​the detector 510 is connected to node b. Apart from this, all other connections remain unchanged and will not be described further here.

[0120] When power supply noise or ground noise is high, the voltage at the output of operational amplifier 15 in differential voltage generator 110 (i.e., bias node d) rises, causing the control current ICTRL to decrease and the voltage level of sensing signal SSEN to drop. When the voltage level of sensing signal SSEN is lower than the transition point of inverter 218a, control circuit 212a activates sensing signal SSEN, causing the output of inverter 218a to change to a high logic level, and transistor MNB turns on. At this time, the switching transistor MNB of reaction circuit 514a connects node b to the power supply voltage VSS. Therefore, reaction circuit 514a stops the voltage VB of node b from rising further and controls the voltage VB of node b to drop, so that differential voltage generator 110 returns to normal operation.

[0121] Similarly, by modifying the detectors 210, 310, and 410 of the first, second, and third embodiments of the present invention, and connecting the reaction circuits 214a, 214b, 314a, 314b, 314c, 314d, 414a, and 414b to node b instead of to node d, the differential voltage generator 110 can be forced to return to normal operation.

[0122] Furthermore, when the differential voltage generator 110 fails, the voltage VA at node a will drop. At this time, designing a reaction circuit to connect node a to the power supply voltage VDD can also force the differential voltage generator 110 to return to normal operation. The following explanation uses the detector in Figure 6 as an example.

[0123] Please refer to Figure 6, which illustrates the detector 610 in the band difference reference circuit of the fifth embodiment of the present invention. The band difference reference circuit of the fifth embodiment includes a band difference voltage generator 110 and a detector 610.

[0124] Compared to the detector 210 in Figure 2B, in the detector 610 of the fifth embodiment with a differential reference circuit, the drain of the switching transistor MNB receives the power supply voltage VDD, and the source of the switching transistor MNB is connected to node a. Apart from this, all other connections remain unchanged and will not be described further here.

[0125] When power supply noise or ground noise is high, the voltage at the output of operational amplifier 15 in band differential voltage generator 110 (i.e., bias node d) rises, causing the control current ICTRL to decrease and the voltage level of sensing signal SSEN to drop. When the voltage level of sensing signal SSEN is lower than the transition point of inverter 218a, control circuit 212a activates sensing signal SSEN, causing the output of inverter 218a to change to a high logic level, and transistor MNB turns on. At this time, the switching transistor MNB of reaction circuit 614a connects node a to the power supply voltage VDD. Therefore, reaction circuit 614a stops the voltage VA of node a from continuing to drop and controls the voltage VA of node a to rise, so that band differential voltage generator 110 returns to normal operation.

[0126] Similarly, by modifying the detectors 210, 310, and 410 in the first, second, and third embodiments of the present invention, and connecting the switching transistors MNB, MPB, MPE, MNH, MNI, MPI, MNL, and MPK in the reaction circuits 214a, 214b, 314a, 314b, 314c, 314d, 414a, and 414b between node a and the power supply voltage VDD, the differential voltage generator 110 can be forced to return to normal operation.

[0127] As can be seen from the above description, the detector of the present invention includes a control circuit and a response circuit. The control circuit is connected to at least one of the bias node d and node c, and the control circuit can activate the sensing signal S SEN according to the change of the bias voltage VD of the bias node d or the band difference voltage VBG of the node c. Furthermore, when the sensing signal S SEN is activated, the response circuit connects the bias node d to the power supply voltage V SS, or connects node b to the power supply voltage V SS, or connects node a to the power supply voltage V DD. When the sensing signal S SEN is not activated, the response circuit disconnects the bias node d from the power supply voltage V SS, or disconnects node b from the power supply voltage V SS, or disconnects node a from the power supply voltage V DD.

[0128] Furthermore, the band differential reference circuit of the present invention is not limited to using band differential voltage generators 100 and 110. The band differential reference circuit of the present invention can also use band differential voltage generators with other configurations. For example, the band differential voltage generator includes only P-type field-effect transistors (P-type FETs) and does not include bijunction transistors (BJT transistors).

[0129] Please refer to Figure 7, which shows another differential voltage generator 700. The differential voltage generator 700 includes: a mirror circuit 12, an operational amplifier 15, an input circuit 22, and a load circuit 32. Only the input circuit 22 and the load circuit 32 will be described below; the others will not be described in detail.

[0130] Input circuit 22 is connected to nodes a and b. Input circuit 22 includes two P-type field-effect transistors M4 and M5. The aspect ratio (W / L) of transistor M5 is m times that of transistor M4. The gate and drain of transistor M4 receive the power supply voltage VSS, making transistor M4 form a diode connection. The gate and drain of transistor M5 receive the power supply voltage VSS, making transistor M5 form a diode connection. In addition, the source of transistor M4 is connected to node a, and the source of transistor M5 is connected to node b by a first resistor R1.

[0131] Load circuit 32 is connected to node c. Load circuit 32 includes a P-type field-effect transistor M6. A second resistor R2 is connected between the source of transistor M6 and node c. The gate and drain of transistor M6 receive the power supply voltage VSS, making transistor M6 form a diode connection. The voltage at node c is the differential voltage VBG.

[0132] In addition to the band differential reference circuit described above, other electronic components can be designed into the band differential voltage generator to prevent the band differential voltage generator from failing. Please refer to Figures 8A to 8C, which illustrate three other embodiments of the band differential reference circuit of the present invention.

[0133] As shown in Figure 8A, the band differential reference circuit 800 series incorporates two capacitors CA and CB in the band differential voltage generator. The first terminal of capacitor CA is connected to node a, and the second terminal of capacitor CA receives the power supply voltage VSS. The first terminal of capacitor CB is connected to node b, and the second terminal of capacitor CB receives the power supply voltage VSS.

[0134] When the power supply noise or ground noise is large, the power supply noise will be coupled to nodes a and b through capacitors CA and CB. Therefore, the power supply noise will not affect the relationship between the two input terminals of operational amplifier 15, so it will not affect the bias voltage VD at the output terminal of operational amplifier 15 and prevent the differential voltage generator from failing.

[0135] In other examples, a single capacitor CA can be provided inside the differential reference circuit 800 to prevent the differential voltage generator from failing. The capacitor CA is connected between node a and the power supply voltage VSS.

[0136] The band difference reference circuit 810 in Figure 8B incorporates two capacitors, CC and CD, in the band difference voltage generator. The first terminal of capacitor CC is connected to node a, and the second terminal of capacitor CC is connected to the emitter of transistor Q2. The first terminal of capacitor CD receives the power supply voltage VDD, and the second terminal of capacitor CD is connected to the emitter of transistor Q2.

[0137] When the power supply noise or ground noise is high, the ground noise received by the emitter of transistor Q2 is coupled to node a and the power supply voltage VDD via capacitors CC and CD. This also prevents the differential voltage generator from failing.

[0138] In other examples, a single capacitor CC or capacitor CD may be sufficient to prevent the differential voltage generator from failing. Alternatively, the differential reference circuit 810 may be designed with capacitors CA and CB as in the differential reference circuit 800 to couple power supply noise more quickly.

[0139] As shown in Figure 8C, the band differential reference circuit 820 incorporates a switching circuit 822 within the band differential voltage generator. The first terminal of the switching circuit 822 is connected to node a, the second terminal is connected to node b, and the control terminal of the switching circuit 822 receives a sensing pulse (P SEN). Furthermore, the band differential reference circuit 820 also incorporates a noise detecting circuit (not shown).

[0140] When power supply noise or ground noise is high, the noise detection circuit generates a sensing pulse (P SEN) to the control terminal of the switching circuit 822, causing the switching circuit 822 to temporarily become closed, temporarily connecting node a to node b. Therefore, power supply noise will not affect the relationship between the two input terminals of operational amplifier 15, and thus will not affect the bias voltage VD at the output terminal of operational amplifier 15, preventing the differential voltage generator from failing.

[0141] Of course, the present invention does not limit the detailed circuit of the noise detection circuit in Figure 8C. For example, the noise detection circuit can be implemented by the control circuit 212 in Figure 2A. When the sensing signal S SEN is activated, the noise detection circuit generates a sensing P SEN wave to the control terminal of the switching circuit 822. Similarly, the noise detector can also be implemented by other control circuits 312 and 412 in the present invention.

[0142] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0006] Figure 1 shows a differential voltage generator; Figure 2A shows a differential reference circuit according to a first embodiment of the present invention; Figure 2B shows a first example of a detector in the differential reference circuit of the first embodiment; Figure 2C shows a second example of a detector in the differential reference circuit of the first embodiment; Figure 3A shows a differential reference circuit according to a second embodiment of the present invention; Figure 3B shows a first example of a detector in the differential reference circuit of the second embodiment; Figure 3C shows another reaction circuit of the detector in the differential reference circuit of the second embodiment; Figure 3D shows a third example of a detector in the differential reference circuit of the second embodiment; Figure 3E shows yet another reaction circuit of the detector in the differential reference circuit of the second embodiment; Figure 4A shows a differential reference circuit according to a third embodiment of the present invention; Figure 4B shows a first example of a detector in the differential reference circuit of the third embodiment; Figure 4C shows another reaction circuit of the detector in the differential reference circuit of the third embodiment; Figure 4D shows a third example of a detector in the differential reference circuit of the third embodiment; Figure 4E shows a fifth example of the detector in the band differential reference circuit of the third embodiment; Figure 4F shows a seventh example of the detector in the band differential reference circuit of the third embodiment; Figure 5 shows a detector in the band differential reference circuit of the fourth embodiment of the present invention; Figure 6 shows a detector in the band differential reference circuit of the fifth embodiment of the present invention; Figure 7 shows another band differential voltage generator; and Figures 8A to 8C show three other embodiments of the band differential reference circuit of the present invention.

Claims

1. A band-difference reference circuit, comprising: A band differential voltage generator comprising: a mirror circuit, an operational amplifier, an input circuit and a load circuit where a negative input terminal of the operational amplifier is connected to a first node of the mirror circuit and a positive input terminal of the operational amplifier is connected to a second section of the mirror circuit point, an output of the operational amplifier is connected to a bias node of the mirror circuit, the load circuit is connected to a third node of the mirror circuit, the input circuit is connected to the first node and the second node of the mirror circuit, the voltage of the third node is a band differential voltage; a detector comprising: a control circuit and a reaction circuit; wherein the reacting circuit receives the sensing signal, when the sensing signal acts, the reacting circuit connects the first node to a first supply voltage, or connects the bias node to a second supply voltage, or connects the second node to the second supply voltage; wherein the first supply voltage is greater than the second supply voltage.

2. The band differential reference circuit as described in claim 1, wherein the control circuit includes: a first transistor, a source of the first transistor receives the first supply voltage, a drawer of the first transistor is connected to the sensing node, a gate of the first transistor receives a consistent energy signal; The current control path, comprising a second transistor and a pull-down circuit where a source pole of the second transistor receives the first supply voltage, a drawer pole of the second transistor is connected to the sensing node, a gate pole of the second transistor is connected to the biasing node, the pull-down circuit is connected between the sensing node and the second supply voltage.

3. The band-differential reference circuit as described in claim 2, wherein the reaction circuit comprises: an inverter and a third transistor, an input terminal of the inverter connected to the sensing node, a gate of the third transistor connected to an output terminal of the inverter; point with the second supply voltage, or such drawer and such source of the third transistor are connected to the second node and the second supply voltage, respectively, or 4. The band difference reference circuit as described in claim 2, wherein the reaction circuit includes: a third transistor where a source and a drawer of the third transistor are connected to the sensing node; 5. The differential reference circuit as described in claim 2, wherein the pull-down circuit includes: a resistor whose first end is connected to the sensing node; and a third transistor, a drawer of which is connected to a second terminal of the resistor, a source terminal of which receives the second supply voltage, and a gate terminal of the third transistor receives the energizing signal.

6. The differential reference circuit as described in claim 2, wherein the pull-down circuit includes: A third transistor is connected to the sensing node by a drawer pole of the third transistor, a source pole of the third transistor receives the second supply voltage, and a gate pole of the third transistor receives the energizing signal.

7. A band-difference reference circuit, comprising: A band differential voltage generator comprising: a mirror circuit, an operational amplifier, an input circuit and a load circuit where a negative input terminal of the operational amplifier is connected to a first node of the mirror circuit and a positive input terminal of the operational amplifier is connected to a second section of the mirror circuit point, an output of the operational amplifier is connected to a bias node of the mirror circuit, the load circuit is connected to a third node of the mirror circuit, the input circuit is connected to the first node and the second node of the mirror circuit, the voltage of the third node is a band differential voltage; a detector comprising: a control circuit and a reaction circuit; wherein the reacting circuit receives the sensing signal, when the sensing signal acts, the reacting circuit connects the first node to a first supply voltage, or connects the bias node to a second supply voltage, or connects the second node to the second supply voltage; wherein the first supply voltage is greater than the second supply voltage.

8. The band differential reference circuit as described in claim 7, wherein the control circuit includes: a first transistor, a source of the first transistor receives the first supply voltage, a drawer of the first transistor is connected to a fourth node, a gate of the first transistor receives a consistent energy signal; a current mirror with one current input end of the current mirror connected to such fourth node, one current mirroring end of which is connected to the sensing node; 9. The band differential reference circuit as described in claim 8, wherein the first current control path includes: a third and a fourth transistor; The second current control path includes: a fifth transistor and a current source; wherein, a drain of the third transistor is connected to the sensing node, a gate of the third transistor is connected to the third node, a drain of the fourth transistor is connected to a source of the third transistor, a source of the fourth transistor receives the second power supply voltage, and a gate of the fourth transistor receives the enable signal; wherein, a drain of the fifth transistor is connected to the fourth node, a gate of the fifth transistor receives the enable signal, and the current source is connected between a source of the fifth transistor and the second power supply voltage.

10. The band difference reference circuit as described in claim 8, wherein the reaction circuit includes: An inverter and a third transistor are provided. An input terminal of the inverter is connected to the sensing node, and a gate of the third transistor is connected to an output terminal of the inverter. A source and a drain of the third transistor are respectively connected to the bias node and the second power supply voltage, or the source and drain of the third transistor are respectively connected to the second node and the second power supply voltage, or the source and drain of the third transistor are respectively connected to the first power supply voltage and the first node.

11. The band difference reference circuit as described in claim 8, wherein the reaction circuit includes: A third transistor, wherein a gate of the third transistor is connected to the sensing node; wherein a drain and a source of the third transistor are respectively connected to the bias node and the second power supply voltage, or the drain and the source of the third transistor are respectively connected to the second node and the second power supply voltage, or the drain and the source of the third transistor are respectively connected to the first power supply voltage and the first node.

12. The differential reference circuit as described in claim 7, wherein the control circuit includes: A first transistor, the source of which receives the first power supply voltage, the drain of which is connected to a fourth node, and the gate of which receives an enable signal; a second transistor, the source of which receives the first power supply voltage, the drain of which is connected to the sensing node, and the gate of which receives the enable signal; a current mirror, the current input of which is connected to the fourth node, and the current mirror emitter of which is connected to the sensing node; a first current control path connected between the fourth node and the second power supply voltage; and a second current control path connected between the sensing node and the second power supply voltage.

13. The band differential reference circuit as described in claim 12, wherein the first current control path includes: A third transistor and a fourth transistor; The second current control path includes: a fifth transistor and a current source; wherein, a drain of the third transistor is connected to the fourth node, a gate of the third transistor is connected to the third node, a drain of the fourth transistor is connected to a source of the third transistor, a source of the fourth transistor receives the second power supply voltage, and a gate of the fourth transistor receives the enable signal; wherein, a drain of the fifth transistor is connected to the sensing node, a gate of the fifth transistor receives the enable signal, and the current source is connected between a source of the fifth transistor and the second power supply voltage.

14. The band difference reference circuit as described in claim 12, wherein the reaction circuit includes: an inverter and a third transistor, an input terminal of the inverter connected to the sensing node, a gate of the third transistor connected to an output terminal of the inverter; point with the second supply voltage, or such drawer and such source of the third transistor are connected to the second node and the second supply voltage, respectively, or 15. The band difference reference circuit as described in claim 12, wherein the reaction circuit includes: a third transistor where a source and a drawer of the third transistor are connected to the sensing node; 16. A band-difference reference circuit, comprising: A band differential voltage generator comprising: a mirror circuit, an operational amplifier, an input circuit and a load circuit where a negative input terminal of the operational amplifier is connected to a first node of the mirror circuit and a positive input terminal of the operational amplifier is connected to a second section of the mirror circuit point, an output of the operational amplifier is connected to a bias node of the mirror circuit, the load circuit is connected to a third node of the mirror circuit, the input circuit is connected to the first node and the second node of the mirror circuit, the voltage of the third node is a band differential voltage; a detector comprising: a control circuit and a reaction circuit; wherein the first current control path is connected to the bias node to receive a bias voltage, a first input of the comparator is connected to the first current control path, a second input of the comparator is connected to the third node to receive the band difference voltage, an output of the comparator is connected to the sensing node, and the control circuit selectively operates the sensing signal according to the change in the band difference voltage from the bias voltage; wherein the reacting circuit receives the sensing signal, when the sensing signal acts, the reacting circuit connects the first node to a first supply voltage, or connects the bias node to a second supply voltage, or connects the second node to the second supply voltage; wherein the first supply voltage is greater than the second supply voltage.

17. The band differential reference circuit as described in claim 16, wherein the control circuit includes: The first current control path includes a first transistor, a second transistor, and a third transistor. The source of the first transistor receives the first power supply voltage, and the gate of the first transistor receives an inverting enable signal. The drain of the second transistor is connected to the drain of the first transistor, and the gate of the second transistor is connected to the bias node. The source of the second transistor is connected to a fourth node, and the drain of the third transistor is connected to the fourth node. The gate of the third transistor receives the first power supply voltage, and the source of the third transistor receives the second power supply voltage. A comparator is also included. The first input of the comparator is connected to the fourth node, the second input of the comparator is connected to the third node to receive the differential voltage, and the output of the comparator is connected to the sensing node.

18. The band differential reference circuit as described in claim 16, wherein the control circuit includes: The first current control path includes a first transistor, a second transistor, and a third transistor. A source of the first transistor is connected to the bias node to receive the bias voltage, and a gate of the first transistor receives an inverting enable signal. A source of the second transistor is connected to a drain of the first transistor, and a gate of the second transistor is connected to a fourth node. A drain of the second transistor is connected to the fourth node, and a drain of the third transistor is connected to the fourth node. A gate of the third transistor receives the first power supply voltage, and a source of the third transistor receives the second power supply voltage. The path also includes a comparator, whose first input is connected to the fourth node, its second input is connected to the third node to receive the differential voltage, and its output is connected to the sensing node.

19. The band differential reference circuit as described in claim 16, wherein the control circuit includes: The first current control path includes a first transistor and a second transistor, wherein a source of the first transistor receives the first power supply voltage, a gate of the first transistor receives an inverting enable signal, a drain of the second transistor is connected to a drain of the first transistor, a source of the second transistor is connected to a fourth node, and a gate of the second transistor is connected to the bias node to receive the bias voltage; a second current control path includes a current source connected between the first power supply voltage and a fifth node; a current mirror, a current input terminal of the current mirror connected to the fifth node, a current mirror emitter terminal of the current mirror connected to the fourth node; and a comparator, a first input terminal of the comparator connected to the fourth node, a second input terminal of the comparator connected to a third node to receive the differential voltage, and an output terminal of the comparator connected to the sensing node.

20. The band differential reference circuit as described in claim 16, wherein the control circuit includes: The first current control path includes a first transistor, a second transistor, and a third transistor. A source of the first transistor is connected to the bias node to receive the bias voltage. A gate of the first transistor is connected to a fourth node. A drain of the first transistor is connected to the fourth node. A drain of the second transistor is connected to the fourth node. A gate of the second transistor receives the first power supply voltage. A drain of the third transistor is connected to a source of the second transistor. A source of the third transistor receives the second power supply voltage. A gate of the third transistor receives a signal. The path also includes a comparator. A first input of the comparator is connected to the fourth node. A second input of the comparator is connected to the third node to receive the differential voltage. The output of the comparator is connected to the sensing node.

21. The band difference reference circuit as described in claim 16, wherein the reaction circuit includes: An inverter and a first transistor, an input terminal of the inverter connected to the sensing node, a gate of the first transistor connected to an output terminal of the inverter; and a drain and a source of the first transistor respectively connected to the bias node and the second power supply voltage, or the drain and the source of the first transistor respectively connected to the second node and the second power supply voltage, or the drain and the source of the first transistor respectively connected to the first power supply voltage and the first node.

22. The band difference reference circuit as described in claim 16, wherein the reaction circuit includes: A first transistor, one gate of which is connected to the sensing node; Furthermore, the source and drain of the first transistor are respectively connected to the bias node and the second power supply voltage, or the source and drain of the first transistor are respectively connected to the second node and the second power supply voltage, or the source and drain of the first transistor are respectively connected to the first power supply voltage and the first node.

23. The band differential reference circuit as described in claim 16, wherein the band differential voltage generator comprises: The mirroring circuit includes a first transistor, a second transistor, and a third transistor. The source of the first transistor receives the first power supply voltage, its drain is connected to the first node, and its gate is connected to the bias node. The source of the second transistor receives the first power supply voltage, its drain is connected to the second node, and its gate is connected to the bias node. The source of the third transistor receives the first power supply voltage, its drain is connected to the third node, and its gate is connected to the bias node. A fourth transistor receives the first power supply voltage at its source, its drain is connected to the bias node, and its gate receives a signal. An operational amplifier has its negative input connected to the first node, its positive input connected to the second node, and its output connected to the bias node. The input circuit includes a fifth transistor, a sixth transistor, and a first resistor, wherein an emitter of the fifth transistor is connected to the first node, a base and a collector of the fifth transistor receive the second power supply voltage, a first terminal of the first resistor is connected to the second node, an emitter of the sixth transistor is connected to a second terminal of the first resistor, and a base and a collector of the sixth transistor receive the second power supply voltage; and the load circuit includes a seventh transistor and a second resistor, wherein a first terminal of the second resistor is connected to the third node, an emitter of the seventh transistor is connected to a second terminal of the second resistor, and a base and a collector of the seventh transistor receive the second power supply voltage.

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