Semiconductor structures and methods of formation

Abstract

The interconnect layer of a semiconductor device includes one or more trench capacitor structures. The process steps for forming the trench capacitor structure described herein can be integrated into the process steps for forming the interconnect layer. A plurality of columns of the bottom electrode structure of the trench capacitor structure described herein can be configured as a combination of rear-end conductive structures in the interconnect layer. A portion of the interlayer dielectric layer located between the columns of the bottom electrode structure in the interconnect layer is removed to form trenches for the trench capacitor structure, wherein the columns define the trenches. Subsequently, a conformal insulating layer can serve as a liner for the deep trenches, and the top electrode structure of the trench capacitor structure fills the deep trenches.

Description

Technical Field

[0001] none Prior Technology

[0002] A semiconductor device may include one or more capacitor structures in an interconnect layer above the device layer (e.g., a back end of line (BEOL) region or a back end region). The capacitor structures may perform and / or support one or more functions in the semiconductor device, such as memory (e.g., dynamic random access memory, DRAM), charge decoupling, analog-to-digital (A / D) conversion, and / or other functions. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates an example semiconductor device described herein. Figures 2A and 2B illustrate exemplary embodiments of the trench capacitor structure described herein. Figures 3A through 3D illustrate example embodiments of the semiconductor device described herein. Figures 4A through 4I illustrate example embodiments of the trench capacitor structure described herein. Figure 5 illustrates an example implementation of the trench capacitor structure described herein. Figure 6 illustrates an example implementation of the trench capacitor structure described herein. Figure 7 illustrates an example implementation of the trench capacitor structure described herein. Figure 8 illustrates an example implementation of the trench capacitor structure described herein. Figures 9A through 9D illustrate example embodiments of the trench capacitor structure described herein. Figure 10 illustrates an example embodiment of the trench capacitor structure described herein. Figures 11A through 11C illustrate exemplary embodiments of the trench capacitor structure described herein. Figures 12A and 12B illustrate example semiconductor devices described herein. Figures 13A through 13F illustrate a top view layout of an example embodiment of the sub-pixels of the display pixels and the associated trench capacitor structure of the semiconductor device described herein. Figure 14 illustrates an example semiconductor device described herein. Figure 15 illustrates an example semiconductor device described herein. Figure 16 illustrates an example process flow diagram related to the formation of the capacitor structure described in this article. Implementation

[0005] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, this document may use spatial relative terms such as "below," "under," "lower," "above," "upper," etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0007] Capacitor structures can include metal-insulator-metal (MIM) structures, where an insulating layer is sandwiched between two conductive electrode layers. The capacitance of a capacitor structure (e.g., the amount of charge it can store) depends directly on the geometry of the conductive electrode layers. The larger the area of ​​the conductive electrode layers, the larger the capacitance. Therefore, increasing the size of the metal electrode layers can increase the capacitance of the capacitor structure.

[0008] However, increasing the lateral dimensions of capacitor structures directly contradicts semiconductor design principles, which aim to reduce semiconductor device size to decrease power consumption, improve operational performance and efficiency, and / or enable semiconductor devices to be used in increasingly smaller form factors. Reducing the size of a semiconductor device may require proportionally reducing the size of the capacitor structure within it, potentially leading to reduced capacitance and / or degraded performance. Furthermore, reducing the size of the semiconductor device may increase the manufacturing difficulty of the capacitor structure, as smaller capacitor structures may reduce the tolerance for manufacturing errors, resulting in a higher defect rate for the capacitor structure within the semiconductor device. Among other examples, the increased defect rate in the capacitor structure of a semiconductor device may degrade the performance of the semiconductor device and / or increase the scraping rate of semiconductor devices including capacitor structures.

[0009] In some embodiments described herein, the interconnect layer of a semiconductor device includes one or more trench capacitor structures. The process steps for forming the trench capacitor structure described herein can be integrated into the process steps for forming the interconnect layer. As an example, a plurality of columns (or "fingers") of the bottom electrode structure of the trench capacitor structure described herein can be constructed as a combination of back-end conductive structures in the interconnect layer (e.g., interconnect structures and metallization structures). A portion of the interlayer dielectric (ILD) between the columns of the bottom electrode structure is removed to form trenches in the trench capacitor structure, wherein the columns define the trenches. In this manner, the columns of the bottom electrode structure have a self-aligned masking function for forming trenches in the structure and allow the trench capacitor structure to have a high aspect ratio. A conformal insulating layer can then serve as a liner for the deep trenches, and the top electrode structure of the trench capacitor structure can fill the deep trenches. Since the deep trenches and the columns of the bottom electrode structure alternate, the top electrode structure also includes columns (or "fingers") that alternate with the columns of the bottom electrode structure.

[0010] In this manner, the alternating arrangement of the columns of the bottom and top electrode structures increases the surface area of ​​both the top and bottom electrode structures (e.g., relative to a flat arrangement of top and bottom electrode layers). Therefore, the capacitance of the trench capacitor structure can be increased with minimal increase in the overall lateral footprint. Furthermore, this alternating arrangement of the columns of the bottom and top electrodes can reduce the size of the semiconductor device and / or increase the component density within the semiconductor device, achieving the same or greater capacitance as the trench capacitor structure included in the semiconductor device.

[0011] Figure 1 illustrates an example semiconductor device 100 described herein. Semiconductor device 100 may include system-on-chip (SoC) devices, logic devices such as central processing unit (CPU) or graphics processing unit (GPU), memory devices (e.g., high bandwidth memory (HBM) devices), image sensor devices (e.g., complementary metal-oxide-semiconductor (CMOS) image sensor devices), display devices (e.g., organic light-emitting diode (OLED) display devices), and / or other types of semiconductor devices.

[0012] As shown in Figure 1, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 arranged along the z-direction in the semiconductor device 100. For example, the interconnect layer 104 may be located above the device layer 102. As another example, the interconnect layer 104 may be located below the device layer 102.

[0013] Device layer 102 may also be referred to as the front end region or front end of line (FEOL) region of semiconductor device 100. Interconnect layer 104 may also be referred to as the back end region or back end of line (BEOL) region of semiconductor device 100, and may include conductive structures arranged to carry signals and / or provide energy distribution throughout semiconductor device 100. In some embodiments, semiconductor device 100 includes interconnect layers 104 above and below device layer 102. A first interconnect layer 104 located on a first side of device layer 102 may be used for signal propagation throughout semiconductor device 100, and a second interconnect layer 104 located on a opposite second side of device layer 102 may be used for energy distribution within semiconductor device 100.

[0014] Device layer 102 includes a substrate 106 of semiconductor device 100. Substrate 106 may correspond to a portion of a semiconductor wafer formed thereon in semiconductor device 100. Substrate 106 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of substrate. Substrate 106 may extend along the x-direction and / or y-direction of semiconductor device 100 such that the top and bottom surfaces of substrate 106 are approximately perpendicular to the z-direction of semiconductor device 100.

[0015] The semiconductor device 100 may include an integrated circuit device 108 in and / or on the substrate 106 of the device layer 102. The integrated circuit device 108 may include a front-end transistor structure (e.g., a front-end planar transistor structure, a front-end fin field-effect transistor (finFET) structure, a front-end gate all-around (GAA) transistor structure), a pixel sensor, a capacitor, a resistor, an inductor, a photosensor, a transceiver, a transmitter, a receiver, optical circuitry, and / or other types of front-end semiconductor devices.

[0016] The front-end transistor structure may include a plurality of source / drain regions separated by channel regions in substrate 106, wherein the source / drain regions may correspond to doped regions of substrate 106. In some embodiments, the source / drain regions are doped with a first type of dopant (e.g., p-type dopant such as boron (B) and / or gallium (Ga), n-type dopant such as phosphorus (P) and / or arsenic (As), and the channel regions are doped with a second type of dopant different from the first type of dopant). The front-end transistor structure may include a gate structure above and / or around the channel regions. A gate dielectric layer may be included between the gate structure of the front-end transistor structure and the channel regions. The gate structure may include a polysilicon gate, a metal gate having a high-k gate dielectric layer such as hafnium oxide (HfOx, e.g., HfO2), and / or other types of gate structures.

[0017] A dielectric layer 110 is included above the substrate 106. The dielectric layer 110 includes an interlayer dielectric layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric material included in the dielectric layer 110 allows for selective etching or etch-free etching of multiple portions of the substrate 106 and / or integrated circuit devices 108, and / or integrated circuit devices 108 in the electrical isolation layer 102. The dielectric layer 110 includes silicon nitride (SixNy), oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 110 may extend along the x-direction and / or y-direction of the semiconductor device 100. Contact structures 112 (e.g., source / drain contacts, gate contacts) may extend through the dielectric layer 110 and be located between the integrated circuit devices 108 and the interconnect layer 104. Contacts can electrically connect integrated circuit devices 108 to interconnect layers 104. Contact structures 112 may include vias, plugs, and / or other types of extended conductive structures. Contact structures 112 may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au), or other conductive materials not listed above.

[0018] Interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in a direction approximately perpendicular to the top surface of substrate 106 (e.g., the z-direction). The dielectric layers may include interlayer dielectric layers 114 and etch stop layers 116 arranged alternately in the z-direction. Interlayer dielectric layers 114 and etch stop layers 116 may extend in the x-direction and / or y-direction of semiconductor device 100.

[0019] The interlayer dielectric layer 114 may each comprise a low-k oxide material, such as silica (SiOx) or undoped silicate glass (USG). Alternatively and alternatively, the interlayer dielectric layer 114 may each comprise boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 114 comprises an extremely low dielectric constant (ELK) dielectric material having a dielectric constant below approximately 2.5. Examples of dielectric materials with extremely low dielectric constants include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), parylene, bis-benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE), silicon oxide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiOx), or other examples not listed above.

[0020] The etch stop layers 116 may each comprise silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 114 and the etch stop layers 116 comprise different dielectric materials to provide etch selectivity for forming multiple structures in the interconnect layer 104. For example, the interlayer dielectric layer 114 may each comprise a low-dielectric-constant dielectric material, such as undoped silicate glass, and the etch stop layers 116 may each comprise a high-dielectric-constant dielectric material, such as silicon nitride (SixNy) or silicon carbide (SiC). Additionally and / or alternatively, two or more etch stop layers 116 may comprise different materials. For example, one or more first etch stop layers 116 may comprise silicon nitride (SixNy), and one or more second etch stop layers 116 may comprise silicon carbide (SiC).

[0021] Interconnect layer 104 includes a plurality of back-end conductive structures arranged in a plurality of layers. The back-end conductive structures may be electrically coupled and / or physically coupled to one or more integrated circuit devices 108 in device layer 102. The back-end conductive structures provide electronic paths for the transfer of signals and / or energy to or from integrated circuit devices 108.

[0022] The multilayer of the back-end conductive structure may include a plurality of vertically arranged layers 118a to 118e, and the plurality of layers 118a to 118e and the plurality of layers 120a to 120d are alternately arranged along the z-direction (e.g., vertically alternate). Each of layers 118a to 118e includes a metallization structure 122, and each of layers 120a to 120d includes an interconnect structure 124.

[0023] Layers 118a to 118e of the metallization structure 122 may be referred to as M layers. For example, layer 118a of the metallization structure 122 (referred to as metal-0 layer (M0)) may be located at the bottom of the interconnect layer 104 and may be coupled to the device layer 102. Specifically, the metallization structure 122 in the M0 layer may be coupled to the contact structure 112 of the integrated circuit device 108 in the device layer 102 (e.g., a contact layer referred to as the "CO" layer). Layer 118b of the metallization structure 122 (referred to as metal-1 layer (M1)) may be located above layer 118a of the metallization structure 122 in the interconnect layer 104, layer 118c of the metallization structure 122 (referred to as metal-2 layer (M2)) may be located above layer 118b of the metallization structure 122, and so on.

[0024] A layer 120a (referred to as via-1 (V0)) of interconnect structure 124 may be included between layers M0 and M1 to interconnect layers M0 and M1, and a layer 120b (referred to as via-2 (V1)) of interconnect structure 124 may be included between layers M1 and M2 to interconnect layers M1 and M2, and so on.

[0025] Metallization structure 122 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. Interconnect structure 124 may include vias, interconnects, and / or combinations of other types of conductive structures. Metallization structure 122 and interconnect structure 124 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, or other examples of conductive materials not mentioned above. In some embodiments, one or more liner layers are included between interconnect layer 104 and the dielectric layer of metallization structure 122, and / or between interconnect layer 104 and the dielectric layer of interconnect structure 124. One or more liner layers may include barrier liners, adhesive liners, and / or other types of liners. Examples of materials for one or more liners include tantalum nitride (TaN) and / or titanium nitride (TiN), or other examples not mentioned above.

[0026] In some embodiments, the top layer of the back-end conductive structure (e.g., the top layer of metallization structure 122, the top layer of interconnect structure 124) may be coupled to a connection structure on top of the semiconductor device 100. The connection structure may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pins of a pin grid array (PGA)), under-bump metallization (UBM), microbumps, spheres of a ball grid array (BGA), controlled collapse chip connection (C4) bumps, and / or other types of connection structures. In some embodiments, the top layer of the back-end conductive structure (e.g., the top layer of metallization structure 122, the top layer of interconnect structure 124) may be coupled to a bonding structure, such as a bonding pad and / or a bonding via.

[0027] As further shown in Figure 1, the interconnect layer 104 of the semiconductor device 100 includes a trench capacitor structure 126. The trench capacitor structure 126 may extend through and / or may be included in one or more dielectric layers of the interconnect layer 104, such as one or more interlayer dielectric layers 114 and / or one or more etch stop layers 116. In some embodiments, integrated circuit devices 108 are electrically coupled to the trench capacitor structure 126 to form memory cells (e.g., dynamic random access memory (DRAM) cells or other types of capacitor-based memory cells) in the semiconductor device 100. In some embodiments, the trench capacitor structure 126 is configured to provide charge decoupling for one or more integrated circuit devices 108. In some embodiments, the trench capacitor structure 126 is configured to store charge (e.g., photocurrent) of the integrated circuit devices 108 (e.g., pixel sensors) in the semiconductor device 100 to increase the full well capacity (FWC) of the pixel sensors in the semiconductor device 100. In some embodiments, the trench capacitor structure 126 is configured to support the global shutter function of the semiconductor device 100. In some embodiments, the trench capacitor structure 126 is configured to provide charge smoothing to the organic light-emitting diode (OLED) display pixels of the semiconductor device 100, thereby enabling high uniformity of brightness in the OLED display pixels. In some embodiments, the trench capacitor structure 126 is configured to perform other functions of the semiconductor device 100.

[0028] The trench capacitor structure 126 may be electrically and / or physically coupled to a bottom contact structure 128 located at the bottom of the trench capacitor structure 126, and electrically and / or physically coupled to a top contact structure 130 located at the top of the trench capacitor structure 126. Alternatively, the trench capacitor structure 126 may be electrically and / or physically coupled to a plurality of top contact structures located at the top of the trench capacitor structure 126. In some embodiments, the bottom contact structure 128 includes contact structures 112 coupled to one or more integrated circuit devices 108 in the device layer 102. In some embodiments, the bottom contact structure 128 and / or the top contact structure 130 may each include one or more rear-end conductive structures in the interconnect layer 104, such as one or more metallized structures 122 and / or one or more interconnect structures 124, or other examples besides those described above.

[0029] As mentioned above, Figure 1 is provided as an example. Other examples may differ from those described with reference to Figure 1.

[0030] Figures 2A and 2B illustrate an example embodiment 200 of the trench capacitor structure 126 described herein. The trench capacitor structure 126 illustrated and described with reference to Figures 2A and 2B may be included in semiconductor device 100 (e.g., in interconnect layer 104), and / or may be included in other semiconductor devices described herein, such as semiconductor device 1200 illustrated and described with reference to Figures 12A and 12B, semiconductor device 1400 illustrated and described with reference to Figure 14, and / or semiconductor device 1500 illustrated and described with reference to Figure 15, or other examples besides those described above.

[0031] Figure 2A illustrates a cross-sectional view of trench capacitor structure 126. As shown in Figure 2A, trench capacitor structure 126 includes one or more trenches 202a to trench 202c above bottom contact structure 128. Bottom contact structure 128 may be included in the interlayer dielectric layer 114a of interconnect layer 104 of semiconductor device 100. The trenches 202 of trench capacitor structure 126 may extend through one or more dielectric layers in interconnect layer 104 of semiconductor device 100, including through etch stop layer 116a, interlayer dielectric layer 114b, etch stop layer 116b, interlayer dielectric layer 114c, etch stop layer 116c, interlayer dielectric layer 114d, etch stop layer 116d, interlayer dielectric layer 114e and / or etch stop layer 116e, or other examples besides those described above. In some embodiments, trench 202 may have a high aspect ratio, where the aspect ratio is the ratio of the depth (or height) of trench 202 to the lateral width (or critical dimension) of trench 202. Therefore, trench capacitor structure 126 may be referred to as a deep trench capacitor (DTC) structure. In some embodiments, the aspect ratio of trench 202 may be approximately 10:1 or greater. In some embodiments, trench 202 may have an aspect ratio ranging from approximately 20:1 to approximately 50:1. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0032] The vertically extending columns 204a to 204d of the bottom electrode structure 204 of the trench capacitor structure 126 define the sidewalls of trenches 202a to 202c. The number of trenches 202a to 202c and columns 204a to 204d illustrated in Figures 2A and 2B are merely examples, and other numbers are also within the scope of embodiments of this disclosure. Columns 204a to 204d extend along the z-direction (e.g., vertical direction) of the semiconductor device 100 and may be arranged along the x-direction (e.g., lateral direction) of the semiconductor device 100. In some embodiments, the ratio of the lateral (x-direction) width of a trench 202 (e.g., one of trenches 202a to 202c) to the lateral (x-direction) width of an extending column (e.g., one of columns 204a to 204d) may be approximately 1:1 to approximately 2:1. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0033] Each column 204a to column 204d includes a vertical (e.g., z-direction) configuration of a rear-end conductive structure, including a configuration of metallization structure 122 and interconnect structure 124. As shown in Figure 2A, the interconnect structure 124 included in columns 204a to column 204d may have tapered sidewalls such that the lateral width of the interconnect structure 124 decreases from the top of the interconnect structure 124 toward the bottom of the interconnect structure 124.

[0034] As further shown in Figure 2A, the bottom electrode structure 204 may further include a bottom conductive structure 204e below columns 204a to 204d. The bottom conductive structure 204e may include a horizontally extending conductive structure that extends laterally across columns 204a to 204d. The bottom conductive structure 204e electrically connects columns 204a to 204d together in parallel and electrically connects columns 204a to 204d to the bottom contact structure 128.

[0035] The laterally adjacent pairs of columns 204a to 204d and the bottom conductive structure 204e define one of the trenches 202a to 202c. Columns 204a and 204b define the sidewalls of trench 202a, and the bottom conductive structure 204e defines the bottom surface of trench 202a. Columns 204b and 204c define the sidewalls of trench 202b, and the bottom conductive structure 204e defines the bottom surface of trench 202b. Columns 204c and 204d define the sidewalls of trench 202c, and the bottom conductive structure 204e defines the bottom surface of trench 202c.

[0036] As further shown in Figure 2A, each column 204a to 204d may include metallization structures 122 and interconnect structures 124 arranged vertically alternately along the z-direction. For example, in column 204a, a first interconnect structure 124 may be included on the bottom conductive structure 204e, a first metallization structure 122 may be included on the first interconnect structure 124, a second interconnect structure 124 may be included on the first metallization structure 122, a third interconnect structure 124 may be included on the second interconnect structure 124, and so on. Columns 204b to 204d may include similar arrangements of metallization structures 122 and interconnect structures 124. Alternatively, one or more columns 204a to 204d may include other arrangements of metallization structures 122 and interconnect structures 124.

[0037] As further shown in Figure 2A, the trench capacitor structure 126 includes a top electrode structure 206 and an insulating layer 208 between the bottom electrode structure 204 and the top electrode structure 206. The bottom electrode structure 204, the insulating layer 208, and the top electrode structure 206 correspond to the MIM structure of the trench capacitor structure 126. Therefore, the trench capacitor structure 126 can also be referred to as an MIM capacitor structure. The trenches 202a to 202c may include the insulating layer 208, and the insulating layer 208 may conform to the contours of the trenches 202a to 202c, such that the insulating layer 208 conforms to the sidewalls of the columns 204a to 204d and the top surface of the bottom conductive structure 204e.

[0038] The top electrode structure 206 also includes a plurality of columns 206a to 206c (e.g., vertically extending columns or "fingers") extending into trenches 202a to 202c. Therefore, columns 206a to 206c of the top electrode structure 206 are inserted between columns 204a to 204d of the bottom electrode structure 204. Columns 206a to 206c of the top electrode structure 206 may extend along the z-direction between the top of columns 204a to 204d of the bottom electrode structure 204 and the bottom of columns 204a to 204d of the bottom electrode structure 204. The bottom conductive structure 204e of the bottom electrode structure 204 may include the bottom of columns 206a to 206c of the top electrode structure 206 on its top.

[0039] The top electrode structure 206 may further include a top conductive structure 206d above columns 206a to 206c. The top conductive structure 206d may include a horizontally extending conductive structure that extends laterally across columns 206a to 206c. The top conductive structure 206d is a merging section of the top electrode structure 206, wherein the merging section electrically connects columns 206a to 206c together in parallel and electrically connects columns 206a to 206c to the top contact structure 130.

[0040] The bottom electrode structure 204 (also referred to as capacitor bottom metal (CBM)) and the top electrode structure 206 (also referred to as capacitor top metal (CTM)) may each comprise one or more conductive metals, one or more materials containing conductive metals, one or more conductive ceramic materials, and / or other types of conductive materials. Examples include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN), or other examples not listed above. In some embodiments, the bottom electrode structure 204 and the top electrode structure 206 comprise the same material or the same material composition. In some embodiments, the bottom electrode structure 204 and the top electrode structure 206 comprise different materials or different material compositions.

[0041] The insulating layer 208 may include one or more electrically insulating materials. In some embodiments, the insulating layer 208 includes one or more low-dielectric-constant dielectric materials, such as silicon oxide (SiOx, e.g., SiO2). Additionally and / or alternatively, the insulating layer 208 may include one or more high-dielectric-constant dielectric materials, such as silicon oxynitride (SiON), zirconium oxide (ZrOx, e.g., ZrO2), aluminum oxide (AlxOy, e.g., Al2O3), silicon nitride (SixNy, e.g., Si3N4), yttrium oxide (YxOy, e.g., Y2O3), lanthanum oxide (LaxOy, e.g., La2O3), hafnium oxide (HfOx, e.g., HfO2), and / or one or more doped high-dielectric-constant dielectric materials, or other examples besides those described above.

[0042] In some embodiments, the thickness of the insulating layer 208 may range from about 1 nanometer to about 1 micrometer. However, other numerical ranges are also within the scope of embodiments of this disclosure. In some embodiments, the ratio of the lateral (x-direction) width of a trench 202 (e.g., one of trenches 202a to 202c) to the thickness of the insulating layer 208 may range from about 5:1 to about 10:1. In some embodiments, the ratio of the lateral (x-direction) width of an extended column of the bottom electrode structure 204 (e.g., one of columns 204a to 204d) to the thickness of the insulating layer 208 may range from about 5:1 to about 10:1. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0043] Figure 2B illustrates a top view of the trench capacitor structure 126, wherein the cross-sectional view of Figure 2A is positioned along line AA in Figure 2B. As shown in Figure 2B, trenches 202a to 202c (and the columns 206a to 206c of the top electrode structures 206 included in trenches 202a to 202c respectively) can extend along the y-direction of the semiconductor device 100 and can be arranged along the x-direction of the semiconductor device 100. Similarly, columns 204a to 204d of the bottom electrode structures 204 can extend along the y-direction of the semiconductor device 100 and can be arranged along the x-direction of the semiconductor device 100. The trenches 202a to 202c (and the columns 206a to 206c of the top electrode structure 206 included in the trenches 202a to 202c respectively) and the columns 204a to 204d of the bottom electrode structure 204 can be arranged alternately along the x direction of the semiconductor device 100.

[0044] The bottom conductive structure 204e of the bottom electrode structure 204 may extend laterally outward along the x and / or y directions beyond columns 204a to 204d. Similarly, the top conductive structure 206d of the top electrode structure 206 may extend laterally outward along the x and / or y directions beyond columns 206a to 206c. In some embodiments, the bottom conductive structure 204e may extend laterally outward (e.g., along the x direction) beyond the end of the top conductive structure 206d. In some embodiments, the ends of the bottom conductive structure 204e and the ends of the top conductive structure 206d may be substantially vertically aligned. In some embodiments, the top conductive structure 206d may extend laterally outward (e.g., along the x direction) beyond the end of the bottom conductive structure 204e.

[0045] As described above, Figures 2A and 2B are provided as an example. Other examples may differ from those described with reference to Figures 2A and 2B.

[0046] Figures 3A through 3D illustrate an example embodiment 300 of forming the semiconductor device 100 described herein. Additionally and / or alternatively, the techniques and / or steps described with reference to one or more of Figures 3A through 3D can be used to form other semiconductor devices described herein, such as semiconductor device 1200 illustrated and described with reference to Figures 12A and 12B, semiconductor device 1400 illustrated and described with reference to Figure 14, and / or semiconductor device 1500 illustrated and described with reference to Figure 15, or other examples besides those described above. In some embodiments, one or more semiconductor process tools can be used to perform one or more semiconductor process steps described with reference to Figures 3A through 3D, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor process tools.

[0047] As shown in Figure 3A, a substrate 106 is provided. The provided substrate 106 may be in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor workpieces. Semiconductor device 100 may be formed on a semiconductor wafer having other semiconductor devices.

[0048] As shown in Figure 3B, an integrated circuit device 108 may be formed in and / or on a substrate 106 in the device layer 102 of the semiconductor device 100. One or more semiconductor process tools may be used to form one or more portions of the integrated circuit device 108. For example, an ion implantation tool may be used to dope one or more regions in the substrate 106 with one or more types of dopant to form well regions, implantation regions, and / or other types of doped regions in the substrate 106 for the integrated circuit device 108. As another example, a deposition tool may be used to perform multiple deposition steps to deposit layers and / or structures of the integrated circuit device 108, and / or deposit a photoresist layer for etching the substrate 106 and / or portions of the deposited layers. As another example, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a development tool may be used to develop the pattern in the photoresist layer. As another example, an etching tool may be used to etch the substrate 106 and / or portions of the deposited layers to form the integrated circuit device 108. As another example, a planarization tool can be used to planarize portions of the integrated circuit device 108. As another example, an electroplating tool can be used to deposit the metal structure and / or layers of the integrated circuit device 108.

[0049] As further shown in Figure 3B, a deposition tool is used to deposit a dielectric layer 110 over and / or on the substrate 106 and over and / or on the integrated circuit device 108. The deposition tool may use physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques to deposit the dielectric layer 110. In some embodiments, a planarization tool may be used to perform a planarization step, such as chemical mechanical planarization (CMP), after the deposition of the dielectric layer 110 to planarize the dielectric layer 110.

[0050] As further shown in Figure 3B, contact structures 112 can be formed through the integrated circuit arrangement 108 of the dielectric layer 110. Contact structures 112 can be formed within grooves in the dielectric layer 110. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 110 to form grooves. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer 110. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer based on the pattern to form grooves. In some embodiments, the etching steps include dry etching steps (e.g., plasma-based etching steps, gas-based etching operations), wet chemical etching steps, and / or other types of etching steps. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the dielectric layer 110 to form grooves.

[0051] Contact structures 112 may be formed in grooves. In some embodiments, contact structures 112 (e.g., gate contacts) are formed on the gate structure of integrated circuit device 108. In some embodiments, contact structures 112 (e.g., source / drain contacts) are formed on the source / drain regions of integrated circuit device 108. Deposition tools may be used to deposit material of contact structures 112 in the grooves using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. Material of contact structures 112 may be deposited in one or more deposition steps. In some embodiments, a seed layer is deposited first, and material of contact structures 112 is deposited on the seed layer. In some embodiments, planarization tools are used to perform a planarization step (e.g., chemical mechanical planarization) after depositing contact structures 112 to planarize contact structures 112 such that the top of contact structures 112 is approximately coplanar with the top of dielectric layer 110.

[0052] As shown in Figure 3C, a first portion of the interconnect layer 104 of the semiconductor device 100 is formed over the dielectric layer 110. One or more deposition tools are used to deposit alternating layers of interlayer dielectric layer 114 and etch stop layer 116 in the first portion of the interconnect layer 104 of the semiconductor device 100. In this manner, the interlayer dielectric layer 114 and etch stop layer 116 can be aligned along the z-direction of the semiconductor device 100. One or more deposition tools can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the respective interlayer dielectric layer 114 and etch stop layer 116. In some embodiments, a planarization tool can be used to planarize the interlayer dielectric layer 114 and / or etch stop layer 116 after deposition.

[0053] As further shown in Figure 3C, deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools can be used to perform multiple steps to form the metallization structure 122 and interconnect structure 124 in the first portion of the interconnect layer 104 of the semiconductor device 100. The bottom contact structure 128 of the trench capacitor structure 126 can also be formed in the first portion of the interconnect layer 104.

[0054] In some embodiments, a first portion of interconnect layer 104 may be formed in a plurality of layers. For example, an interlayer dielectric layer 114 and an etch stop layer 116 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), a groove may be formed (e.g., using an exposure tool, development tool, and / or etching tool) in and / or through the interlayer dielectric layer 114 and the etch stop layer 116, and a layer 118a (e.g., an M0 layer) may be formed (e.g., using one or more deposition tools and / or one or more planarization tools) in the interlayer dielectric layer 114 and the etch stop layer 116. Another interlayer dielectric layer 114 and another etch stop layer 116 may be formed, and a layer 120a (e.g., a V0 layer) may be formed in the interlayer dielectric layer 114 and the etch stop layer 116 to form interconnect structure 124. Layers 118b, 118c, 120b, and 120c may be formed in a similar manner.

[0055] One or more deposition tools may be used to deposit the metallized structure 122, the interconnect structure 124, and / or the bottom contact structure 128 using physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electro-chemical plating), and / or other suitable deposition techniques. In some embodiments, a planarization tool may be used to planarize the metallized structure 122, the interconnect structure 124, and / or the bottom contact structure 128 after deposition.

[0056] As further shown in Figure 3C, the trench capacitor structure 126 can be formed in one or more dielectric layers of the interconnect layer 104. The trench capacitor structure 126 can be formed such that the columns 204a to 204d of the bottom electrode structure 204 and the bottom conductive structure 204e of the trench capacitor structure 126 are formed in the same manner as the combination of steps for the metallization structure 122 and the interconnect structure 124 in layers 118a, 120a, 118b, and / or layer 120c, or other examples besides those described above. The interlayer dielectric layer 114 and the etch stop layer 116 are removed from portions between columns 204a to 204d to form trenches 202a to 202c, and an insulating layer 208 and a top electrode structure 206 are formed in trenches 202a to 202c. A top contact structure 130 can be formed on the top electrode structure 206. The example process for forming the trench capacitor structure 126 is illustrated and described with reference to Figures 4A to 4I.

[0057] As shown in Figure 3D, a second portion of the interconnect layer 104 of the semiconductor device 100 is formed over the first portion of the interconnect layer 104 (including over the trench capacitor structure 126). The second portion of the interconnect layer 104 may be formed in a manner similar to that of the first portion of the interconnect layer 104 as described with reference to Figure 3C.

[0058] As described above, Figures 3A through 3D are provided as an example. Other examples may differ from those described with reference to Figures 3A through 3D.

[0059] Figures 4A through 4I illustrate an example embodiment 400 of forming the trench capacitor structure 126 described herein. Although Figures 4A through 4I illustrate an example of an example embodiment 200 of forming the trench capacitor structure 126 of Figures 2A and 2B, other embodiments may be performed with reference to the techniques and steps described in Figures 4A through 4I to form the trench capacitor structure 126 described herein, including those described with reference to Figures 5, 6, 7, 8, 10 and / or Figures 11A through 11C, or other examples not described above.

[0060] In some embodiments, one or more semiconductor process tools may be used to perform one or more semiconductor process steps as described in Figures 4A to 4I, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools, and / or other types of semiconductor process tools. In some embodiments, one or more semiconductor process steps as described in Figures 4A to 4I may be performed as part of the process for forming the semiconductor device 100 described in Figures 3A to 3D.

[0061] As shown in Figure 4A, the bottom contact structure 128 of the trench capacitor structure 126 can be formed in the dielectric layer 110. The bottom conductive structure 204e of the bottom electrode structure 204 can be formed in the interlayer dielectric layer 114a and can fall on the bottom contact structure 128. The etch stop layer 116a can be formed above and / or on the interlayer dielectric layer 114a and the bottom conductive structure 204e.

[0062] To form the bottom contact structure 128, a groove may be formed in the dielectric layer 110, and the bottom contact structure 128 may be deposited in the groove. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 110 to form the groove. In these embodiments, a deposition tool may be used to form the photoresist layer on the dielectric layer 110 (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the dielectric layer 110 based on the pattern to form the groove. In some embodiments, the etching steps include dry etching steps (e.g., plasma-based etching steps, gas-based etching steps), wet chemical etching steps, and / or other types of etching steps. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative to pattern-based etching of the dielectric layer 110.

[0063] The deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit the material of the bottom contact structure 128. The bottom contact structure 128 can be deposited in one or more deposition steps. In some embodiments, a seed layer is deposited first, and the bottom contact structure 128 is deposited on the seed layer. In some embodiments, a liner (e.g., a barrier liner, an adhesive liner) is deposited first, and the bottom contact structure 128 is deposited on the liner. In some embodiments, the bottom contact structure 128 is deposited on a metal silicate layer, such as a titanium silicate (TiSi) layer and / or a ruthenium silicate (RuSi) layer, or other examples of metal silicate materials besides those described above. In some embodiments, a planarization tool is used to perform a planarization step (e.g., a chemical mechanical planarization step) after the deposition of the bottom contact structure 128 to planarize the bottom contact structure 128.

[0064] Next, an interlayer dielectric layer 114a can be deposited. The deposition tools can utilize physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the interlayer dielectric layer 114a. The interlayer dielectric layer 114a can be deposited in one or more deposition steps. In some embodiments, a planarization tool can be used to perform a planarization step (e.g., a chemical mechanical planarization step) after the deposition of the interlayer dielectric layer 114a to planarize the interlayer dielectric layer 114a.

[0065] To form the bottom conductive structure 204e of the bottom electrode structure 204, a groove can be formed in the interlayer dielectric layer 114a, and the bottom conductive structure 204e can be deposited in the groove. The groove can be formed such that the top of the bottom contact structure 128 is exposed in the groove. This allows a portion of the bottom conductive structure 204e to fall onto the bottom contact structure 128, resulting in an electrical connection between the bottom contact structure 128 and the bottom conductive structure 204e.

[0066] In some embodiments, the pattern in the photoresist layer is used to etch the interlayer dielectric layer 114a to form grooves. In these embodiments, a deposition tool may be used to form the photoresist layer on the interlayer dielectric layer 114a (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the interlayer dielectric layer 114a based on the pattern to form grooves. In some embodiments, the etching steps include dry etching steps (e.g., plasma-based etching steps, gas-based etching steps), wet chemical etching steps, and / or other types of etching steps. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the interlayer dielectric layer 114a.

[0067] The deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit the material of the bottom conductive structure 204e. The bottom conductive structure 204e can be deposited in one or more deposition steps. In some embodiments, a seed layer is deposited first, and the bottom conductive structure 204e is deposited on the seed layer. In some embodiments, a liner (e.g., a barrier liner, an adhesive liner) is deposited first, and the bottom conductive structure 204e is deposited on the liner. In some embodiments, a planarization tool is used to perform a planarization step (e.g., a chemical mechanical planarization step) after the deposition of the bottom conductive structure 204e to planarize the bottom conductive structure 204e.

[0068] Next, an etch stop layer 116a can be deposited. The deposition tools can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the etch stop layer 116a. The etch stop layer 116a can be deposited in one or more deposition steps. In some embodiments, a planarization tool can be used to perform a planarization step (e.g., a chemical mechanical planarization step) after the deposition of the etch stop layer 116a to planarize the etch stop layer 116a.

[0069] As shown in Figure 4B, the interlayer dielectric layer 114b can be formed on the etch stop layer 116a. The first column interconnect structure 124 of the columns 204a to 204d of the bottom electrode structure 204 can be formed in the interlayer dielectric layer 114b, such that the first column interconnect structure 124 falls on the bottom conductive structure 204e of the bottom electrode structure 204. The first column metallization structure 122 of the columns 204a to 204d of the bottom electrode structure 204 can be formed in the interlayer dielectric layer 114b, such that the first column metallization structure 122 falls on the first column interconnect structure 124. The etch stop layer 116b can be formed on the interlayer dielectric layer 114b and the first column metallization structure 122.

[0070] The deposition tool can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the interlayer dielectric layer 114b. The interlayer dielectric layer 114b can be deposited in one or more deposition steps. In some embodiments, a planarization tool can be used to perform a planarization step (e.g., a chemical mechanical planarization step) after the deposition of the interlayer dielectric layer 114b to planarize the interlayer dielectric layer 114b.

[0071] In some embodiments, a first column of interconnect structures 124 is formed first, and a first column of metallized structures 122 is formed after the formation of the first column of interconnect structures 124. For example, a first portion of the interlayer dielectric layer 114b may be formed first, and the first portion of the interlayer dielectric layer 114b and the etch stop layer 116a and / or through the groove formed for the first column of interconnect structures 124 may be formed, such that the top surface of the bottom conductive structure 204e is exposed in the groove, and the first column of interconnect structures 124 may then be formed in the groove. Subsequently, a second portion of the interlayer dielectric layer 114b may be formed, and the second portion of the interlayer dielectric layer 114b and / or through the groove formed for the first column of metallized structures 122 may be formed, such that the top of the first column of interconnect structures 124 is exposed in the groove, and the first column of metallized structures 122 may then be formed in the groove on the first column of interconnect structures 124.

[0072] Alternatively, the grooves for the first column of metallized structures 122 and the grooves for the first column of interconnect structures 124 can be formed using a dual damascene method. For example, the groove for the first interconnect structure 124 of column 204a can correspond to the through-hole portion of the dual damascene groove, and the groove for the first metallized structure 122 of column 204a can correspond to the trench portion of the dual damascene groove. The dual damascene grooves for columns 204b to 204d can be formed in a similar manner. The dual damascene grooves can be formed using a through-hole technique first, wherein the through-hole of the dual damascene groove corresponding to the groove of the first column of interconnect structures 124 is formed first, and the trench of the dual damascene groove corresponding to the groove of the first column of metallized structures 122 is formed subsequently. Alternatively, the dual damascene grooves can be formed using a trench technique first, wherein the trench of the dual damascene groove corresponding to the groove of the first column of metallized structures 122 is formed first, and the through-hole of the dual damascene groove corresponding to the groove of the first column of interconnect structures 124 is formed subsequently. The first column of interconnect structure 124 and the first column of metallization structure 122 can be deposited together in the dual damascene grooves.

[0073] Next, an etch stop layer 116b can be deposited. The deposition tools can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the etch stop layer 116b. The etch stop layer 116b can be deposited in one or more deposition steps. In some embodiments, a planarization tool can be used to perform a planarization step (e.g., a chemical mechanical planarization step) after the deposition of the etch stop layer 116b to planarize the etch stop layer 116b.

[0074] As shown in Figures 4C to 4E, other columns of metallized structures 122 and other columns of interconnect structures 124 of the bottom electrode structure 204, which are in columns 204a to 204d, can be formed similarly to the method described with reference to Figure 4B. The multiple columns of metallized structures 122 and multiple columns of interconnect structures 124 can be stacked and arranged along the z-direction to form columns 204a to 204d of the bottom electrode structure 204.

[0075] The multi-column metallized structure 122 and the multi-column interconnect structure 124 of the columns 204a to 204d are laterally separated along the x-direction, such that the columns 204a to 204d of the bottom electrode structure 204 define the space between the columns 204a to 204d of the bottom electrode structure 204.

[0076] As shown in Figure 4F, the space between columns 204a to 204d of the bottom electrode structure 204 is etched to form trenches 202a to 202c. When etching portions of the interlayer dielectric layers 114b to 114e and portions of the etch stop layers 116a to 116e between columns 204a to 204d, the columns 204a to 204d of the bottom electrode structure 204 can have a self-aligning masking function. Etching tools can be used to etch portions of the interlayer dielectric layers 114b to 114e and portions of the etch stop layers 116a to 116e between columns 204a to 204d to form trenches 202a to 202c. In some embodiments, the etching steps include dry etching steps (e.g., plasma-based etching steps, gas-based etching steps), wet chemical etching steps, and / or other types of etching steps.

[0077] As shown in Figure 4G, an insulating layer 208 of the trench capacitor structure 126 is formed on the sidewalls and bottom surface of trenches 202a to 202c. The insulating layer 208 can be conformally deposited such that it conforms to the contours of trenches 202a to 202c. In other words, the insulating layer 208 can be conformally deposited such that it conforms to the sidewalls of trenches 202a to 202c and the top surface of the bottom conductive structure 204e of the bottom electrode structure 204. The insulating layer 208 can be continuously extended across trenches 202a to 202c, such that a single continuous insulating layer 208 is included within and between trenches 202a to 202c. The deposition tool can be used to deposit the insulating layer 208 using conformal deposition techniques, such as chemical vapor deposition and / or atomic layer deposition, or other examples besides those described above.

[0078] As shown in Figure 4H, the material of the top electrode structure 206 of the trench capacitor structure 126 can be filled in trenches 202a to 202c, such that columns 206a to 206c are formed on the insulating layer 208 in trenches 202a to 202c. The material of the top electrode structure 206 can also be deposited over trenches 202a to 202c, such that the material of the top electrode structure 206 is incorporated over trenches 202a to 202c to form the top conductive structure 206d of the top electrode structure 206. The deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit the top electrode structure 206. The top electrode structure 206 can be deposited in one or more deposition steps.

[0079] As shown in Figure 4I, an interlayer dielectric layer 114f can be formed on the trench capacitor structure 126. The top contact structure 130 of the trench capacitor structure 126 can be formed in the interlayer dielectric layer 114f, such that the top contact structure 130 rests on and is electrically connected to the top conductive structure 206d of the top electrode structure 206.

[0080] The deposition tool can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the interlayer dielectric layer 114f. The interlayer dielectric layer 114f can be deposited in one or more deposition steps. In some embodiments, a planarization tool can be used to perform a planarization step (e.g., a chemical mechanical planarization step) after the deposition of the interlayer dielectric layer 114f to planarize the interlayer dielectric layer 114f.

[0081] To form the top contact structure 130, a groove may be formed in the interlayer dielectric layer 114f, and the top contact structure 130 may be deposited in the groove. In some embodiments, a pattern in the photoresist layer is used to etch the interlayer dielectric layer 114f to form the groove. In these embodiments, a deposition tool may be used to form the photoresist layer on the interlayer dielectric layer 114f (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the interlayer dielectric layer 114f based on the pattern to form the groove. In some embodiments, the etching steps include dry etching steps (e.g., plasma-based etching steps, gas-based etching steps), wet chemical etching steps, and / or other types of etching steps. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative to the pattern-etched interlayer dielectric layer 114f.

[0082] The deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit material for the top contact structure 130. The top contact structure 130 can be deposited in one or more deposition steps. In some embodiments, a seed layer is deposited first, and the top contact structure 130 is deposited on the seed layer. In some embodiments, a liner (e.g., a barrier liner, an adhesive liner) is deposited first, and the top contact structure 130 is deposited on the liner. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., a chemical mechanical planarization step) after the deposition of the top contact structure 130 to planarize the top contact structure 130.

[0083] As described above, Figures 4A through 4I are provided as an example. Other examples may differ from those described with reference to Figures 4A through 4I.

[0084] Figure 5 illustrates an exemplary embodiment 500 of the trench capacitor structure 126 described herein. As shown in Figure 5, the exemplary embodiment 500 of the trench capacitor structure 126 illustrated in Figure 5 includes a combination and configuration of layers and structures similar to those of the exemplary embodiment 200 of the trench capacitor structure 126 illustrated in Figures 2A and 2B. However, in exemplary embodiment 500, the interconnect structures 124 in the columns 204a to 204d of the bottom electrode structure 204 of the trench capacitor structure 126 are substantially non-tapered, such that the sidewalls of the interconnect structures 124 are approximately parallel. Therefore, the trenches 202a to 202c have substantially flat and uniform sidewalls, as shown in Figure 5.

[0085] When forming the trenches for the interconnect structure 124, an interconnect structure 124 with non-tapered sidewalls in the columns 204a to 204d of the bottom electrode structure 204 of the trench capacitor structure 126 can be formed using a process technique such as anisotropic etching. In some embodiments, plasma-based etching techniques can be used to form the trenches for the interconnect structure 124 to achieve substantially vertical sidewalls in the trenches. In some embodiments, deep reactive ion etching (sometimes referred to as "Bosch" etching) is used to achieve substantially vertical sidewalls in the trenches.

[0086] As mentioned above, Figure 5 is provided as an example. Other examples may differ from those described with reference to Figure 5.

[0087] Figure 6 illustrates an exemplary embodiment 600 of the trench capacitor structure 126 described herein. As shown in Figure 6, the exemplary embodiment 600 of the trench capacitor structure 126 illustrated in Figure 6 includes a combination and configuration of layers and structures similar to those of the exemplary embodiment 200 of the trench capacitor structure 126 illustrated in Figures 2A and 2B. However, in the exemplary embodiment 600, the insulating layer 208 included in the trench capacitor structure 126 comprises a multilayer stack, wherein the multilayer stack includes a plurality of dielectric layers. The plurality of dielectric layers may include dielectric layer 208a on the sidewalls and bottom surfaces of trenches 202a to 202c (corresponding to the sidewalls of columns 204a to 204d and the top surface of the bottom conductive structure 204e), dielectric layer 208b on dielectric layer 208a, and dielectric layer 208c on dielectric layer 208b. However, the number and configuration of other dielectric layers of the insulating layer 208 are also within the scope of embodiments of this disclosure.

[0088] The insulating layer 208 includes a plurality of dielectric layers 208a to 208c, which can be tuned to give the trench capacitor structure 126 a specific performance. Additionally and / or alternatively, the insulating layer 208 may include a plurality of dielectric layers 208a to 208c to promote adhesion between the insulating layer 208 and the bottom electrode structure 204, and / or to promote adhesion between the insulating layer 208 and the top electrode structure 206.

[0089] In some embodiments, the multilayer stack of insulating layer 208 includes a stack of low-dielectric-constant layers / high-dielectric-constant layers / low-dielectric-constant layers. In these embodiments, dielectric layer 208a is a low-dielectric-constant dielectric layer, dielectric layer 208b is a high-dielectric-constant dielectric layer, and dielectric layer 208c is a low-dielectric-constant dielectric layer. For example, insulating layer 208 may include a stack of SiO2 / HfO2 / SiO2 layers. In some embodiments, the multilayer stack of insulating layer 208 includes a stack of high-dielectric-constant layers / high-dielectric-constant layers / high-dielectric-constant layers. In these embodiments, dielectric layer 208a is a first high-dielectric-constant dielectric layer, dielectric layer 208b is a second high-dielectric-constant dielectric layer, and dielectric layer 208c is a third high-dielectric-constant dielectric layer. For example, insulating layer 208 may include a stack of ZrO2 / Al2O3 / ZrO2 (ZAZ). In some embodiments, the multilayer stack of insulating layer 208 includes other combinations of high dielectric constant dielectric layers and / or low dielectric constant dielectric layers.

[0090] The exemplary embodiment 600 of the trench capacitor structure 126 illustrated in Figure 6 can be formed using techniques and processes similar to those illustrated and described with reference to Figures 4A to 4I. However, the steps for forming the insulating layer 208 described with reference to Figure 4G may include a multi-step deposition process to form a multilayer stack of the insulating layer 208 in the exemplary embodiment 600 of the trench capacitor structure 126 illustrated in Figure 6. For example, deposition tools may be used in a first deposition step to deposit a dielectric layer 208a using atomic layer deposition, chemical vapor deposition, and / or other suitable conformal deposition techniques. Deposition tools may be used in a second deposition step to deposit a dielectric layer 208b using atomic layer deposition, chemical vapor deposition, and / or other suitable conformal deposition techniques. Deposition tools may be used in a third deposition step to deposit a dielectric layer 208c using atomic layer deposition, chemical vapor deposition, and / or other suitable conformal deposition techniques. Dielectric layers 208a to 208c can be deposited as continuous layers and extend along the sidewalls of trenches 202a to 202c, along the bottom surface of trenches 202a to 202c, and between trenches 202a and 202c.

[0091] In some embodiments, the thickness of dielectric layer 208a ranges from about 1 nanometer to about 1 micrometer. In some embodiments, the thickness of dielectric layer 208b ranges from about 1 nanometer to about 1 micrometer. In some embodiments, the thickness of dielectric layer 208c ranges from about 1 nanometer to about 1 micrometer. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0092] In some embodiments, the ratio of the thickness of dielectric layer 208b to the thickness of dielectric layer 208a may be approximately 1:1 to approximately 2:1. In some embodiments, the ratio of the thickness of dielectric layer 208b to the thickness of dielectric layer 208c may be approximately 1:1 to approximately 2:1. In some embodiments, the ratio of the thickness of dielectric layer 208a to the thickness of dielectric layer 208c may be approximately 1:2 to approximately 2:1. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0093] As mentioned above, Figure 6 is provided as an example. Other examples may differ from those described with reference to Figure 6.

[0094] Figure 7 illustrates an exemplary embodiment 700 of the trench capacitor structure 126 described herein. As shown in Figure 7, the exemplary embodiment 700 of the trench capacitor structure 126 illustrated in Figure 7 includes a combination and configuration of layers and structures similar to the exemplary embodiment 600 of the trench capacitor structure 126 illustrated in Figure 6. However, in the exemplary embodiment 700, each of the columns 206a to 206c of the top electrode structure 206 of the trench capacitor structure 126 includes an air gap 702 extending into the trench 202. For example, column 206a includes an air gap 702 extending into the trench 202a, column 206b includes an air gap 702 extending into the trench 202b, and / or column 206c includes an air gap 702 extending into the trench 202c, or other examples besides those described above.

[0095] Air gaps 702 in the columns 206a of the top electrode structure 206 may extend between the top and bottom of the trench 202a. Therefore, air gaps 702 in the columns 206a vertically span the bottom electrode structure 204, defining a plurality of metallized structures 122 and a plurality of interconnect structures 124 in the columns 204a and 204b of the trench 202a. Similarly, air gaps 702 in the columns 206b of the top electrode structure 206 may extend between the top and bottom of the trench 202b, and air gaps 702 in the columns 206c of the top electrode structure 206 may extend between the top and bottom of the trench 202c. Air gaps 702 may be formed in the columns 206a to 206c of the top electrode structure 206 to relieve stress in the trench capacitor structure 126. Vibration and / or thermal expansion and contraction may cause stress to be applied to the trench capacitor structure 126, or other examples besides those described above. The air gap 702 can balance the stress in the trench capacitor structure 126, thereby reducing the possibility of cracking and delamination in the layers and / or structure of the trench capacitor structure 126.

[0096] During the step of forming the top electrode structure 206 as described with reference to Figure 4H, a deposition technique can be used to form the air gap 702. For example, the material of the top electrode structure 206 can be deposited in trenches 202a to 202c at a high deposition rate. The high deposition rate causes the accumulation rate of the material of the top electrode structure 206 at the top of trenches 202a to 202c to be faster than the accumulation rate in the middle of trenches 202a to 202c. Therefore, the material of the top electrode structure 206 merges at the top of trenches 202a to 202c before completely filling trenches 202a to 202c, thereby forming the air gap 702. In some embodiments, physical vapor deposition, chemical vapor deposition, and / or other deposition techniques that enable high deposition rates of the material of the top electrode structure 206 can be used to deposit the material of the top electrode structure 206.

[0097] As mentioned above, Figure 7 is provided as an example. Other examples may differ from those described with reference to Figure 7.

[0098] Figure 8 illustrates an exemplary embodiment 800 of the trench capacitor structure 126 described herein. As shown in Figure 8, the exemplary embodiment 800 of the trench capacitor structure 126 illustrated in Figure 8 includes a combination and configuration of layers and structures similar to the exemplary embodiment 600 of the trench capacitor structure 126 illustrated in Figure 6. However, in exemplary embodiment 800, the top conductive structure 206d of the top electrode structure 206 is omitted, and the columns 206a to 206c of the top electrode structure 206 are physically discontinuous. Therefore, the columns 206a to 206c are not directly electrically coupled, but rather electrically coupled through the top contact structure 130.

[0099] The top contact structure 130 includes a plurality of top contact structures 130a to 130c and a horizontally extending metallized structure 130d electrically coupled to the top contact structures 130a to 130c. Each column 206a to 206c can be physically coupled to one or more top contact structures 130a to 130c. For example, column 206a can be physically coupled to top contact structure 130a, column 206b can be physically coupled to top contact structure 130b, and column 206c can be physically coupled to top contact structure 130c. The horizontally extending metallized structure 130d electrically couples the top contact structures 130a to 130c together, such that the columns 206a to 206c are electrically coupled in parallel.

[0100] As further shown in Figure 8, the insulating layer 208 between trenches 202a and 202c is similarly discontinuous. Therefore, the insulating layer 208 comprises a plurality of discontinuous segments. A segment of the insulating layer 208 is included on the sidewalls and bottom surface of trench 202a, thus a segment of the insulating layer 208 is located between the columns 206a of the bottom electrode structure 204 and the top electrode structure 206. A segment of the insulating layer 208 is included on the sidewalls and bottom surface of trench 202b, thus a segment of the insulating layer 208 is located between the columns 206b of the bottom electrode structure 204 and the top electrode structure 206. A segment of the insulating layer 208 is included on the sidewalls and bottom surface of trench 202c, thus a segment of the insulating layer 208 is located between the columns 206c of the bottom electrode structure 204 and the top electrode structure 206.

[0101] As mentioned above, Figure 8 is provided as an example. Other examples may differ from those described with reference to Figure 8.

[0102] Figures 9A through 9D illustrate an example embodiment 900 of forming the trench capacitor structure 126 described herein. Although Figures 9A through 9D illustrate an example embodiment 800 of forming the trench capacitor structure 126 in Figure 8, other embodiments of forming the trench capacitor structure 126 described herein may be performed with reference to Figures 9A through 9D, including those described with reference to Figures 10 and / or 11A through 11C, or other examples not described above.

[0103] In some embodiments, one or more semiconductor process tools may be used to perform one or more semiconductor process steps as described in Figures 9A to 9D, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools, and / or other types of semiconductor process tools. In some embodiments, one or more semiconductor process steps as described in Figures 9A to 9D may be performed as part of the process for forming the semiconductor device 100 (or other semiconductor device) as described in Figures 3A to 3D.

[0104] As shown in Figure 9A, the steps illustrated and described in Figures 4A to 4H can be performed to form the bottom contact structure 128, the bottom electrode structure 204, the insulating layer 208, and the top electrode structure 206.

[0105] As shown in Figure 9B, before forming the interlayer dielectric layer 114f on the trench capacitor structure 126, a planarization step can be performed using a planarization tool, such as a chemical mechanical planarization operation or other types of planarization steps, to planarize the insulating layer 208 and the top electrode structure 206 of the trench capacitor structure 126. In the planarization step, the top conductive structure 206d of the top electrode structure 206 and the segment of the insulating layer 208 located on the etch stop layer 116e are removed. Therefore, the columns 206a to 206c of the top electrode structure 206 are discontinuous between trenches 202a and 202c, just like the discontinuous segments of the insulating layer 208. Furthermore, the end of a segment in trench 202a can be located at the top of trench 202a, the end of a segment in trench 202b can be located at the top of trench 202b, and the end of a segment in trench 202c can be located at the top of trench 202c.

[0106] The planarization step can stop at the etch stop layer 116e, so the etch stop layer 116e can serve as a stop layer for the planarization step. After the planarization step, the tops of columns 206a to 206c, the ends of the discontinuous sections of the insulating layer 208, and the top surface of the etch stop layer 116e can be approximately coplanar.

[0107] As shown in Figure 9C, after the planarization step, an interlayer dielectric layer 114f can be formed on the trench capacitor structure 126. Therefore, the interlayer dielectric layer 114f contacts the top of the columns 206a to 206c of the top electrode structure 206, and the interlayer dielectric layer 114f contacts the end of the discontinuous segment of the insulating layer 208.

[0108] As shown in Figure 9D, top contact structures 130a to 130c and horizontally extending metallized structures 130d are formed in the interlayer dielectric layer 114f. For example, grooves may be formed in the interlayer dielectric layer 114f above the respective trenches 202a to 202c and corresponding to the columns 206a to 206c of the top electrode structure 206. The conductive material of the top contact structures 130a to 130c may be formed in the grooves above the columns 206a to 206c, such that the top contact structures 130a to 130c fall on the columns 206a to 206c respectively. Grooves for the horizontally extending metallized structure 130d may be formed in the interlayer dielectric layer 114f, and the horizontally extending metallized structure 130d may be formed in the grooves.

[0109] In some embodiments, grooves for the top contact structures 130a to 130c and the horizontally extending metallized structure 130d can be formed using a dual-grooving method, wherein the through-holes of the dual-grooving grooves correspond to the grooves of the top contact structures 130a to 130c, and the grooves of the dual-grooving grooves correspond to the grooves of the horizontally extending metallized structure 130d. The dual-grooving grooves can be formed using a through-hole technique (e.g., first forming through-holes of the dual-grooving grooves corresponding to the grooves of the top contact structures 130a to 130c, and then subsequently forming grooves of the dual-grooving grooves corresponding to the grooves of the horizontally extending metallized structure 130d), or a trenching technique (e.g., first forming grooves of the dual-grooving grooves corresponding to the grooves of the horizontally extending metallized structure 130d, and then subsequently forming through-holes of the dual-grooving grooves corresponding to the grooves of the top contact structures 130a to 130c). In these embodiments, top contact structure 130a to top contact structure 130c and horizontally extended metallized structure 130d can be deposited together in the dual damascene grooves.

[0110] As described above, Figures 9A through 9D are provided as an example. Other examples may differ from those described with reference to Figures 9A through 9D.

[0111] Figure 10 illustrates an exemplary embodiment 1000 of the trench capacitor structure 126 described herein. As shown in Figure 10, the exemplary embodiment 1000 of the trench capacitor structure 126 illustrated in Figure 10 includes a combination and configuration of layers and structures similar to the exemplary embodiment 800 of the trench capacitor structure 126 illustrated in Figure 8. However, in the exemplary embodiment 1000, each of the columns 206a to 206c of the top electrode structure 206 of the trench capacitor structure 126 includes an air gap 702 extending into the trench 202, similar to the exemplary embodiment 700 of the trench capacitor structure 126 in Figure 7. For example, column 206a includes an air gap 702 extending into the trench 202a, column 206b includes an air gap 702 extending into the trench 202b, and / or column 206c includes an air gap 702 extending into the trench 202c, or other examples besides those described above.

[0112] Air gaps 702 in the columns 206a of the top electrode structure 206 may extend between the top and bottom of the trench 202a. Therefore, air gaps 702 in the columns 206a vertically span the plurality of metallized structures 122 and the plurality of interconnect structures 124 in the columns 204a and 204b defining the trench 202a of the bottom electrode structure 204. Similarly, air gaps 702 in the columns 206b of the top electrode structure 206 may extend between the top and bottom of the trench 202b, and air gaps 702 in the columns 206c of the top electrode structure 206 may extend between the top and bottom of the trench 202c. Air gaps 702 may be formed in the columns 206a to 206c of the top electrode structure 206 to release stress in the trench capacitor structure 126. Vibration and / or thermal expansion and contraction may cause stress to be applied to the trench capacitor structure 126, or other examples besides those described above. The air gap 702 can balance the stress in the trench capacitor structure 126, thereby reducing the possibility of cracking and delamination in the layers and / or structure of the trench capacitor structure 126.

[0113] During the step of forming the top electrode structure 206 as described with reference to Figure 4H, a deposition technique can be used to form the air gap 702. For example, the material of the top electrode structure 206 can be deposited in trenches 202a to 202c at a high deposition rate. The high deposition rate causes the accumulation rate of the material of the top electrode structure 206 at the top of trenches 202a to 202c to be faster than the accumulation rate in the middle of trenches 202a to 202c. Therefore, the material of the top electrode structure 206 merges at the top of trenches 202a to 202c before completely filling trenches 202a to 202c, thereby forming the air gap 702. In some embodiments, physical vapor deposition, chemical vapor deposition, and / or other deposition techniques that enable high deposition rates of the material of the top electrode structure 206 can be used to deposit the material of the top electrode structure 206.

[0114] As mentioned above, Figure 10 is provided as an example. Other examples may differ from those described with reference to Figure 10.

[0115] Figures 11A through 11C illustrate an exemplary embodiment 1100 of the trench capacitor structure 126 described herein. As shown in the cross-sectional view of the trench capacitor structure 126 in Figure 11A, the exemplary embodiment 1100 of the trench capacitor structure 126 includes a combination and configuration of layers and structures similar to the exemplary embodiment 800 of the trench capacitor structure 126 illustrated in Figure 8. For example, the top conductive structure 206d of the top electrode structure 206 is omitted, and the columns 206a to 206c of the top electrode structure 206 are physically discontinuous. The top contact structure 130 includes a plurality of top contact structures 130a to 130c, and horizontally extending metallized structures 130d electrically coupling the top contact structures 130a to 130c. Each column 206a to 206c is physically coupled to the interconnect structure of the top contact structure 130.

[0116] However, as shown in the cross-sectional view of the trench capacitor structure 126 in Figure 11B, the bottom electrode structure 204 also omits the bottom conductive structure 204e. Instead, the columns 204a to 204d of the bottom electrode structure 204 are electrically coupled via another top contact structure 1102. The top contact structure 1102 includes a plurality of top contact structures 1102a to 1102d, and a horizontally extending metallized structure 1102e electrically coupling the top contact structures 1102a to 1102d. Each column 204a to 204d may be physically coupled to one or more of the top contact structures 1102a to 1102d. For example, column 204a can be physically coupled to top contact structure 1102a, column 204b can be physically coupled to top contact structure 1102b, column 204c can be physically coupled to top contact structure 1102c, and column 204d can be physically coupled to top contact structure 1102d. The horizontally extending metallized structure 1102e electrically couples top contact structures 1102a to 1102d together, such that columns 204a to 204d are electrically coupled in parallel.

[0117] Top contact structures 1102a to 1102d may extend through the etch stop layer 116e and may physically contact columns 204a to 204d, respectively. In some embodiments, the outer columns (e.g., columns 204a and 204d) may include lateral extensions, wherein top contact structures 1102a and 1102d fall on the lateral extensions.

[0118] Figure 11C illustrates a top view of an exemplary embodiment 1100 of the trench capacitor structure 126, and shows the cross-sectional view along line BB in Figure 11A and along line CC in Figure 11B. As shown in Figure 11C, the top contact structures 1102a to 1102d and the horizontally extending metallized structure 1102e of the top contact structures 1102 may be located on the first side of the trenches 202a to 202c of the trench capacitor structure 126, while the top contact structures 206a to 206c and the top conductive structure 206d of the top electrode structures 206 may be located on the second side of the trenches 202a to 202c of the trench capacitor structure 126 relative to the first side. However, other locations of the top contact structures 1102a to 1102d of the top contact structure 1102 and the horizontally extended metallized structure 1102e and / or the top contact structures 206a to 206c and the top conductive structure 206d of the top electrode structure 206 along the trench 202a to 202c are also within the scope of the embodiments of this disclosure.

[0119] As described above, Figures 11A through 11C are provided as an example. Other examples may differ from those described with reference to Figures 11A through 11C.

[0120] Figures 12A and 12B illustrate examples of the semiconductor device 1200 described herein. Figure 12A illustrates a top view of the semiconductor device 1200. As shown in Figure 12A, the semiconductor device 1200 may include a display device, wherein the display device includes a display pixel array 1202. The display pixel array 1202 includes a plurality of display pixels 1204, wherein the display pixels 1204 are configured to collectively generate images and / or videos. In some embodiments, the display pixels 1204 are arranged in a grid, as shown in the example in Figure 12A. However, other configurations of the display pixels 1204 of the display pixel array 1202 are also within the scope of embodiments of this disclosure. In some embodiments, the display pixels 1204 include organic light-emitting diode (OLED) display pixels, and the display pixel array 1202 includes an OLED display. However, other types of display pixels and display pixel arrays are also within the scope of embodiments of this disclosure.

[0121] As further shown in Figure 12A, a display pixel 1204 may include a plurality of subpixels 1206. For example, display pixel 1204 may include a subpixel 1206a configured to emit a first color of light (e.g., red light), a subpixel 1206b configured to emit a second color of light (e.g., green light), and a subpixel 1206c configured to emit a third color of light (e.g., blue light). However, other configurations and combinations of subpixels 1206 of display pixel 1204 are also within the scope of embodiments of this disclosure. Two or more subpixels 1206 of display pixel 1204 may be of the same size and / or shape, two or more subpixels 1206 of display pixel 1204 may be of different sizes and / or different shapes, or combinations thereof.

[0122] Figure 12B illustrates an example cross-sectional view of pixel 1204 along lines DD and EE in Figure 12A. The cross-sectional view in Figure 12B illustrates an example structural configuration of sub-pixels 1206a to 1206c of pixel 1204. As shown in Figure 12B, semiconductor device 1200 may include a microdisplay device, wherein sub-pixels 1206a to 1206c of display pixel array 1202 are included on circuit layer 1208 of semiconductor device 1200. Therefore, semiconductor device 1200 may include an organic light-emitting diode-on-silicon (OLED) device, a display-on-silicon (display-on-silicon) device, and / or other types of microdisplay devices, wherein display pixel array 1202 is integrated on semiconductor device 1200 having CMOS integrated circuitry.

[0123] As shown in Figure 12B, the circuit layer 1208 of the semiconductor device 1200 includes a device layer 1210 and an interconnect layer 1212. The device layer 1210 may include a semiconductor layer 1214, which corresponds to a portion of a semiconductor wafer on which the semiconductor device 1200 is formed. The semiconductor layer 1214 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator substrate, or other types of semiconductor substrates.

[0124] Device layer 1210 includes integrated circuitry 1216 in and / or on semiconductor layer 1214. Integrated circuitry 1216 may include driving circuitry components included in the sub-pixel circuits of sub-pixels 1206a to 1206c. For example, integrated circuitry 1216 may include switching transistors, driving transistors, and / or other driving circuitry components. The transistors of the driving circuits (e.g., switching transistors, driving transistors) may be planar transistors, fin field-effect transistors, nanostructured transistors (e.g., gate-all-around transistors, nanosheet transistors, nanowire transistors), and / or other types of transistors in and / or on semiconductor layer 1214.

[0125] Interconnect layer 1212 includes conductive structures of integrated circuit devices 1216 interconnecting driving circuits and electrically connects integrated circuit devices 1216 of driving circuits to sub-pixels 1206a to 1206c. Interconnect layer 1212 includes one or more dielectric layers 1218 arranged in a direction approximately perpendicular to semiconductor layer 1214 (e.g., the z-direction). Dielectric layers 1218 may each include back-end dielectric layers (e.g., interlayer dielectric layers, intermetallic dielectric (IMD)) and etch stop layers alternately arranged in interconnect layer 1212. The dielectric layer 1218 may include, respectively, oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), undoped silicate glass, borosilicate glass, fluorinated silicate glass, dielectric materials with extremely low dielectric constants below about 2.5, silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON) and / or other suitable dielectric materials.

[0126] The conductive structures in the dielectric layer 1218 of the interconnect layer 1212 may include metallized structures 1220 (e.g., trenches, wires) interconnected via interconnect structures 1222 (e.g., vias). The metallized structures 1220 and interconnect structures 1222 may each include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, or other examples of conductive materials not mentioned above.

[0127] As further shown in Figure 12B, the interconnect layer 1212 of the semiconductor device 1200 may include one or more exemplary embodiments of the trench capacitor structure 126 illustrated and described herein. The trench capacitor structure 126 may be configured as a storage capacitor for the driving circuitry of sub-pixels 1206a to 1206c. The device may include the trench capacitor structure 126 to stabilize the driving signal and the brightness of the corresponding sub-pixels 1206a to 1206c (thereby increasing the brightness uniformity of the display pixel array 1202), and / or reduce and / or minimize the flicker of the sub-pixels 1206a to 1206c.

[0128] The bottom electrode structure 204 of a trench capacitor structure 126 included in the interconnect layer 1212 of the semiconductor device 1200 may include a plurality of columns 204a to 204d, each of which includes vertically alternating metallization structures 1220 and interconnect structures 1222. Columns 204a to 204d define trenches of the trench capacitor structure 126, and an insulating layer 208 may be formed on the sidewalls of the trenches (corresponding to the sidewalls of columns 204a to 204d).

[0129] The device layer 1210 and interconnect layer 1212 of semiconductor device 1200 can be formed in a manner similar to that of device layer 102 and interconnect layer 104 of semiconductor device 100, as described with reference to Figures 3A to 3D. In some embodiments, the display pixel array 1202 can be formed separately from the device layer 1210 and interconnect layer 1212 of semiconductor device 1200 (e.g., in a display panel manufacturing process), and can be bonded to the interconnect layer 1212 of semiconductor device 1200 after the display pixel array 1202 has been manufactured. In some embodiments, the display pixel array 1202 is formed on the interconnect layer 1212 of semiconductor device 1200.

[0130] As described above, Figures 12A and 12B are provided as an example. Other examples may differ from those described with reference to Figures 12A and 12B.

[0131] Figures 13A to 13F illustrate a top view layout of an exemplary embodiment of the display pixel 1204 of the semiconductor device 1200 described herein, including sub-pixels 1206a to 1206c and the associated trench capacitor structure 126.

[0132] Figures 13A and 13B illustrate an example embodiment 1300, wherein sub-pixels 1206a and 1206b are laterally adjacent in the y-direction, and sub-pixel 1206c is laterally adjacent to sub-pixels 1206a and 1206b in the x-direction. Sub-pixels 1206a and 1206b may each have an approximately square shape in a top view, and sub-pixel 1206c may have an approximately rectangular shape in a top view. Each of sub-pixels 1206a to 1206c may be associated with a trench capacitor structure. For example, sub-pixel 1206a may be electrically coupled to trench capacitor structure 126a, sub-pixel 1206b may be electrically coupled to trench capacitor structure 126b, and sub-pixel 1206c may be electrically coupled to trench capacitor structure 126c. Trench capacitor structures 126a to 126c may be located below sub-pixels 1206a to 1206c and may be arranged laterally in the x-direction. The trench capacitor structures 126a to 126c may have an approximately rectangular shape in a top view, and the trenches 202 of each trench capacitor structure 126a to 126c may extend in the y-direction and may be arranged along the x-direction. In some embodiments, trench capacitor structures 126a to 126c include the same number of trenches 202. In some embodiments, two or more of the trench capacitor structures 126a to 126c include different numbers of trenches 202. In some embodiments, trench capacitor structures 126a to 126c include trenches 202 of the same size and / or the same shape. In some embodiments, two or more of the trench capacitor structures 126a to 126c include trenches 202 of different sizes and / or different shapes. For example, the trench 202 of the trench capacitor structure 126a may be larger in size (e.g., length, width, and / or depth) than the trench 202 of the trench capacitor structure 126b.

[0133] Figures 13C and 13D illustrate example embodiment 1302, wherein all sub-pixels 1206a to 1206c are laterally adjacent to each other and each has a generally hexagonal shape in the top view. Trench capacitor structures 126b and 126c are laterally adjacent in the x-direction, and trench capacitor structure 126a is laterally adjacent to trench capacitor structures 126b and 126c in the y-direction. Trench capacitor structures 126b and 126c may each have an approximately square shape in the top view, and trench capacitor structure 126a may have an approximately rectangular shape in the top view. The trenches 202 of trench capacitor structures 126b and 126c may extend in the y-direction and may be arranged in the x-direction. The trenches 202 of trench capacitor structure 126a may extend in the x-direction and may be arranged in the y-direction.

[0134] Figures 13E and 13F illustrate example embodiment 1304, wherein each of the sub-pixels 1206a to 1206d included in display pixel 1204 has a generally square shape in a top view. Sub-pixels 1206a and 1206b are laterally adjacent in the x-direction. Sub-pixels 1206a and 1206c are laterally adjacent in the y-direction. Sub-pixels 1206b and 1206d are laterally adjacent in the y-direction. Sub-pixels 1206c and 1206d are laterally adjacent in the x-direction.

[0135] Sub-pixels 1206a to 1206d are associated with trench capacitor structures 126a to 126d, respectively. Each of the trench capacitor structures 126a to 126d has a generally square shape in a top view. Trench capacitor structures 126a and 126b are laterally adjacent in the x-direction. Trench capacitor structures 126a and 126c are laterally adjacent in the y-direction. Trench capacitor structures 126b and 126d are laterally adjacent in the y-direction. Trench capacitor structures 126c and 126d are laterally adjacent in the x-direction. The trenches 202 of trench capacitor structures 126a and 126d can extend in the x-direction and can be arranged in the y-direction. The trenches 202 of trench capacitor structures 126b and 126c can extend in the y-direction and can be arranged in the x-direction.

[0136] As described above, Figures 13A through 13F are provided as an example. Other examples may differ from those described with reference to Figures 13A through 13F.

[0137] Figure 14 illustrates an example semiconductor device 1400 described herein. Semiconductor device 1400 may include an example three-dimensional image sensor (e.g., a three-dimensional CMOS image sensor (CIS)). Semiconductor device 1400 can be applied to various implementations, such as digital cameras, video recorders, night vision cameras, automatic sensors and cameras, and / or other types of light-sensing implementations.

[0138] As shown in Figure 14, the semiconductor device 1400 may include a plurality of semiconductor dies, including a first semiconductor die 1402a and a second semiconductor die 1402b. The first semiconductor die 1402a and the second semiconductor die 1402b may be directly bonded together at a bonding interface 1404, such that the first semiconductor die 1402a and the second semiconductor die 1402b are stacked and vertically arranged along the z-direction in the semiconductor device 1400. The first semiconductor die 1402a may be referred to as an image sensor die and may include a pixel sensor array 1406. The first semiconductor die 1402a may further include a black level correction (BLC) region 1408, a bonding pad region 1410, and / or a sealing ring region 1412, or other examples besides those described above.

[0139] The pixel sensor array 1406 may include a plurality of pixel sensors 1414 arranged in an array. Each pixel sensor 1414 may be configured to sense incident light and convert photons of the incident light into a photocurrent. The pixel sensors 1414 may be included in a device layer 1416 of a first semiconductor die 1402a. Each pixel sensor 1414 may include a photodiode 1418, wherein the photodiode 1418 is configured to generate a photocurrent based on photoelectrons of the incident light. Each pixel sensor 1414 may further include a floating diffusion node 1420 in the device layer 1416 configured to temporarily store the photocurrent generated by the pixel sensor 1414, and may each include a transfer gate 1422 configured to control the flow of photocurrent from the photodiode 1418 to the floating diffusion node 1420. The pixel sensor 1414 can be formed using one or more semiconductor process tools with multiple semiconductor process technologies, such as photolithography, etching, deposition, chemical mechanical planarization and / or ion implantation, or other examples besides those described above.

[0140] The black level correction region 1408 includes a metal mask layer above a portion of the device layer 1416, thus allowing for the performance of current baseline measurements in the device layer 1416 within the black level correction region 1408 to define the dark current of the pixel sensor array 1406 (e.g., current in the device layer 1416 generated by sources other than incident light, such as heat), thereby adjusting the black level of the pixel sensor array 1406 to compensate for the dark current. The bonding pad region 1410 may include one or more conductive bonding pads (or exposed pads (e-pads)) and / or metallization layers, wherein the bonding pad region 1410 establishes electronic connections between the semiconductor device 1400 and external devices and / or external packages. The sealing ring region 1412 may include a configuration of metallization and interconnect structures to provide structural rigidity to the semiconductor device 1400 and protect it from moisture and other contaminants.

[0141] As further shown in Figure 14, the first semiconductor die 1402a may include an interconnect layer 1424 below and / or beneath the device layer 1416. The interconnect layer 1424 may include a dielectric region 1426 having one or more dielectric layers (e.g., interlayer dielectric layers, etch stop layers) and a configuration of a metallization structure 1428 in the dielectric region 1426 with the interconnect structure 1430.

[0142] As further shown in Figure 14, the second semiconductor die 1402b of the semiconductor device 1400 may include a device layer 1432, one or more integrated circuit devices 1434 included in the device layer 1432, and an interconnect layer 1436 above the device layer 1432. The interconnect layer 1436 may include a dielectric region 1438 having one or more dielectric layers (e.g., interlayer dielectric layers, etch stop layers), and the configuration of metallization structures 1440 and interconnect structures 1442 in the dielectric region 1438 of the interconnect layer 1436 of the second semiconductor die 1402b.

[0143] The bonding of the first semiconductor die 1402a and the second semiconductor die 1402b at the bonding interface 1404 can be achieved through dielectric-to-dielectric bonding between the dielectric region 1426 of the first semiconductor die 1402a and the dielectric region 1438 of the second semiconductor die 1402b. Furthermore, the bonding of the first semiconductor die 1402a and the second semiconductor die 1402b at the bonding interface 1404 can be achieved through metal-to-metal bonding between the bonding pads 1444 included in the interconnect layer 1424 of the first semiconductor die 1402a and the bonding pads 1446 included in the interconnect layer 1436 of the second semiconductor die 1402b. Bonding pad 1444 can be electrically connected to metallization structure 1428 and interconnect structure 1430 in interconnect layer 1424 through bonding via 1448, and bonding pad 1446 can be electrically connected to metallization structure 1440 and interconnect structure 1442 in interconnect layer 1436 through bonding via 1450.

[0144] As further shown in Figure 14, the semiconductor device 1400 includes one or more trench capacitor structures 126. The one or more trench capacitor structures 126 may be included in the dielectric region 1426 of the interconnect layer 1424 of the first semiconductor die 1402a. The bottom electrode structure 204 of the trench capacitor structure 126 included in the interconnect layer 1424 of the first semiconductor die 1402a may include a plurality of columns 204a to 204d, each of columns 204a to 204d including vertically alternating metallization structures 1428 and interconnect structures 1430. Columns 204a to 204d define trenches of the trench capacitor structure 126, and an insulating layer 208 may be formed on the sidewalls of the trenches (corresponding to the sidewalls of columns 204a to 204d).

[0145] One or more trench capacitor structures 126 may be configured to store photocurrents associated with a plurality of pixel sensors 1414 of the pixel sensor array 1406. In some embodiments, one or more trench capacitor structures 126 are configured to store photocurrent overflowing from the floating diffusion node 1420 of the pixel sensor 1414 to increase the potential well capacity of the pixel sensor 1414. One or more trench capacitor structures 126 may be referred to as lateral overflow integration (LOFIC) capacitors, and the semiconductor device 1400 may be referred to as a LOFIC CMOS image sensor. One or more trench capacitor structures 126 increase the potential well capacity of the pixel sensor 1414, wherein the photocurrent of the floating diffusion node 1420 of the pixel sensor 1414 can be transferred to one or more trench capacitor structures 126, thus allowing additional photocurrent of the photodiode 1418 to be transferred to the floating diffusion node 1420 during and / or after exposure operations of the pixel sensor array 1406. This can effectively increase the amount of photons that the photodiode 1418 can absorb before saturation, thereby enabling the pixel sensor array 1406 to achieve a high dynamic range (HDR).

[0146] In some embodiments, the device may include one or more trench capacitor structures 126, allowing the semiconductor device 1400 to implement a global shutter function. Progressive exposure of the pixel sensors 1414 in the pixel sensor array 1406 to incident light can achieve another type of shutter effect known as a rolling shutter. At the start of the exposure operation, the integrated circuit device 1434 scans the pixel sensors 1414 in the pixel sensor array 1406 for exposure column by column until all pixel sensors 1414 have been exposed. All actions are completed in a short time, and the exposure times for different columns of pixel sensors 1414 are different. Therefore, when using such progressive exposure to capture a fast-moving target, the exposure operation may produce incomplete images and / or distortions. This can cause distorted images due to output time differences. One or more trench capacitor structures 126 can implement a global shutter function, in which all pixel sensors 1414 in the pixel sensor array 1406 are exposed simultaneously. At the start of the global shutter exposure operation, each pixel sensor 1414 simultaneously begins to collect charge and generate photocurrent, and this can be performed throughout the exposure time of the global shutter exposure operation. Each pixel sensor 1414 transfers the photocurrent to one or more trench capacitor structures 126 for simultaneous accumulation. At the end of the global shutter exposure operation, one or more trench capacitor structures 126 transfer the photocurrent to the integrated circuit device 1434.

[0147] As mentioned above, Figure 14 is provided as an example. Other examples may differ from those described with reference to Figure 14.

[0148] Figure 15 illustrates an example semiconductor device 1500 described herein. Semiconductor device 1500 may include an example three-dimensional image sensor (e.g., a three-dimensional CIS). Semiconductor device 1500 can be applied to a variety of implementations, such as digital cameras, video recorders, night vision cameras, automatic sensors and cameras, and / or other types of light-sensitive implementations.

[0149] As shown in Figure 15, semiconductor device 1500 includes a structure and / or layer combination similar to semiconductor device 1400. For example, semiconductor device 1500 may include one or more embodiments of a first semiconductor die 1402a to a bonding via 1450 and the trench capacitor structure 126 illustrated and described herein.

[0150] However, as shown in Figure 15, the trench capacitor structure 126 in the semiconductor device 1500 is included in the second semiconductor die 1402b (e.g., an application-specific integrated circuit (ASIC) die) rather than (or additionally located) in the first semiconductor die 1402a (e.g., a sensor die). Including one or more trench capacitor structures 126 on the second semiconductor die 1402b instead of the first semiconductor die 1402a allows more area in the first semiconductor die 1402a to be used for the photodiode 1418 (thus providing increased potential well capacity for the photodiode 1418) and / or for control circuitry of the pixel sensor 1414 (e.g., transfer gate 1422, reset gate, source follower gate), thus improving the performance of the semiconductor device 1500.

[0151] One or more trench capacitor structures 126 may be included in the dielectric region 1438 of the interconnect layer 1436 of the second semiconductor die 1402b. The bottom electrode structure 204 of the trench capacitor structure 126 included in the interconnect layer 1436 of the second semiconductor die 1402b may include a plurality of columns 204a to 204d, each of columns 204a to 204d including vertically alternating metallization structures 1440 and interconnect structures 1442. Columns 204a to 204d define trenches of the trench capacitor structure 126, and an insulating layer 208 may be formed on the sidewalls of the trenches (corresponding to the sidewalls of columns 204a to 204d).

[0152] As mentioned above, Figure 15 is provided as an example. Other examples may differ from those described with reference to Figure 15.

[0153] Figure 16 illustrates a flowchart of an example process 1600 relating to the formation of the capacitor structure described herein. In some embodiments, one or more process steps of Figure 16 are performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0154] As shown in Figure 16, process 1600 may include forming a plurality of dielectric layers of an interconnect layer of a semiconductor device over a device layer of the semiconductor device (step 1610). For example, one or more semiconductor process tools may be used to form a plurality of dielectric layers (e.g., interlayer dielectric layers 114a to 114e, etch stop layers 116a to 116e) of an interconnect layer (e.g., interconnect layer 104) of a semiconductor device (e.g., semiconductor device 100) over a device layer (e.g., device layer 102), as described herein.

[0155] As further shown in Figure 16, process 1600 may include forming a plurality of first back-end conductive structures and a plurality of second back-end conductive structures in a plurality of dielectric layers (step 1620). For example, one or more semiconductor process tools may be used to form a plurality of first back-end conductive structures (e.g., metallization structure 122, interconnect structure 124) and a plurality of second back-end conductive structures (e.g., metallization structure 122, interconnect structure 124) in a plurality of dielectric layers, as described herein. In some embodiments, the second back-end conductive structures are arranged in a plurality of vertically extending columns (e.g., columns 204a to 204d), wherein the columns correspond to the bottom electrode structure (e.g., bottom electrode structure 204) of a trench capacitor structure (e.g., trench capacitor structure 126).

[0156] As further shown in Figure 16, process 1600 may include etching a plurality of dielectric layers between adjacent pairs within a plurality of vertically extending columns of a trench capacitor structure to form a plurality of trenches in the trench capacitor structure (step 1630). For example, one or more semiconductor process tools may be used to etch a plurality of dielectric layers between adjacent pairs within a plurality of vertically extending columns of a trench capacitor structure to form a plurality of trenches in the trench capacitor structure (e.g., trenches 202a to 202c), as described herein. In some embodiments, the plurality of vertically extending columns define the sidewalls of the plurality of trenches.

[0157] As further shown in Figure 16, process 1600 may include forming an insulating layer of a trench capacitor structure on the sidewalls of a plurality of trenches (step 1640). For example, one or more semiconductor process tools may be used to form an insulating layer of a trench capacitor structure (e.g., insulating layer 208) on the sidewalls of a plurality of trenches, as described herein.

[0158] As further shown in Figure 16, process 1600 may include forming a top electrode structure of a trench capacitor structure on an insulating layer in a trench (step 1650). For example, one or more semiconductor process tools may be used to form a top electrode structure of a trench capacitor structure on an insulating layer in a plurality of trenches (e.g., top electrode structure 206), as described herein.

[0159] Process 1600 may include additional implementations, such as any single implementation or any combination of implementations described below and / or one or more other processes described elsewhere herein.

[0160] In the first embodiment, the plurality of second rear-end conductive structures further include a bottom conductive structure (e.g., bottom conductive structure 204e), and forming the plurality of second rear-end conductive structures includes forming a plurality of vertically extending columns on the bottom conductive structure.

[0161] In the second embodiment, either alone or in combination with the first embodiment, forming a top electrode structure includes filling a plurality of trenches with the material of the top electrode structure, such that voids are formed in the top electrode structure within the plurality of trenches.

[0162] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 1600 includes planarizing the insulating layer and the top electrode structure after forming the top electrode structure, such that the insulating layer between the plurality of trenches is discontinuous.

[0163] In the fourth embodiment, forming an insulating layer, either alone or in combination with one or more of the first and third embodiments, includes forming a first low dielectric constant dielectric layer (e.g., dielectric layer 208a), forming a high dielectric constant dielectric layer (e.g., dielectric layer 208b) on the first low dielectric constant dielectric layer, and forming a second low dielectric constant dielectric layer (e.g., dielectric layer 208c) on the high dielectric constant dielectric layer.

[0164] In the fifth embodiment, alone or in combination with one or more of the first and fourth embodiments, process 1600 includes forming a plurality of top contact structures (e.g., top interconnect structures 130a to 130c) on the top electrode structure, wherein each of the plurality of top contact structures is formed directly above one of the plurality of trenches.

[0165] Although Figure 16 illustrates example steps of process 1600, in some embodiments, process 1600 may include more steps, fewer steps, different steps, or steps in a different order than those in Figure 16. Alternatively, two or more steps of process 1600 may be performed simultaneously.

[0166] In this manner, the interconnect layer of the semiconductor device includes one or more trench capacitor structures. The process steps for forming the trench capacitor structure described herein can be integrated into the process steps for forming the interconnect layer. As an example, a plurality of columns (or "fingers") of the bottom electrode structure of the trench capacitor structure described herein can be constructed as a combination of back-end conductive structures (e.g., interconnect structures and metallization structures) in the interconnect layer. The interlayer dielectric layer of the portion of the interconnect layer between the columns of the bottom electrode structure is removed to form trenches of the trench capacitor structure, wherein the columns define the trenches. In this manner, the columns of the bottom electrode structure have a self-aligned masking function for forming the trenches of the structure and allow the trench capacitor structure to have a high aspect ratio. Subsequently, the deep trenches can have a conformal insulating layer as a liner and fill the top electrode structure of the trench capacitor structure.

[0167] As further detailed above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a bottom electrode structure, wherein the bottom electrode structure includes a plurality of rows of rear-end conductive structures in an interconnect layer of a semiconductor device, wherein the plurality of rows of rear-end conductive structures define a plurality of trenches in the semiconductor structure. The semiconductor structure includes an insulating layer located on the sidewalls and bottom surface of the plurality of trenches. The semiconductor structure includes a top electrode structure located on the insulating layer in the plurality of trenches.

[0168] As further detailed above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a bottom electrode structure comprising a plurality of rows of back-end conductive structures in an interconnect layer of a semiconductor device, wherein the plurality of rows of back-end conductive structures defines a plurality of trenches in the semiconductor structure, and wherein each row of back-end conductive structures includes alternately arranged vias and metallization structures. The semiconductor structure includes an insulating layer located on the sidewalls and bottom surface of the plurality of trenches. The semiconductor structure includes a top electrode structure located on the insulating layer in the plurality of trenches, wherein the top electrode structure includes air gaps extending into the plurality of trenches.

[0169] As further detailed above, some embodiments described herein provide a method. The method includes forming a plurality of dielectric layers of an interconnect layer of a semiconductor device over a device layer of a semiconductor device. The method includes forming a plurality of first rear-end conductive structures and a plurality of second rear-end conductive structures in the plurality of dielectric layers, wherein the plurality of second rear-end conductive structures are arranged in a plurality of vertically extending columns corresponding to a bottom electrode structure of a trench capacitor structure. The method includes etching through a plurality of dielectric layers adjacent to pairs within the plurality of vertically extending columns of the trench capacitor structure to form a plurality of trenches of the trench capacitor structure, wherein the plurality of vertically extending columns define sidewalls of the plurality of trenches. The method includes forming an insulating layer of the trench capacitor structure on the sidewalls of the plurality of trenches. The method includes forming a top electrode structure of the trench capacitor structure on the insulating layer in the plurality of trenches.

[0170] The terms "approximately" and "substantially" can refer to a value that varies within 5% of a given value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are illustrative only and are not intended to be limiting. It should be understood that the terms "approximately" and "substantially" can represent a percentage of a given value in an embodiment of this disclosure.

[0171] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0172] 100: Semiconductor devices 102: Device Layer 104: Interconnection Layer 106:Substrate 108: Integrated circuit devices 110: Dielectric layer 112: Contact structure 114, 114a, 114b, 114c, 114d, 114e, 114f: Interlayer dielectric layers 116, 116a, 116b, 116c, 116d, 116e: Etching stop layers 118a, 118b, 118c, 118d, 118e: Layers 120a, 120b, 120c, 120d: Layers 122: Metallized structure 124: Interconnection Structure 126, 126a, 126b, 126c, 126d: Trench capacitor structure 128: Bottom contact structure 130, 130a, 130b, 130c: Top contact structure 130d: Horizontally Extended Metallized Structure 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1300, 1302, 1304: Example Implementation Methods 202, 202a, 202b, 202c: Trench 204: Bottom Electrode Structure 204a, 204b, 204c, 204d: Columns 204e: Bottom conductive structure 206: Top electrode structure 206a, 206b, 206c: Columnar / top contact structure 206d: Top conductive structure 208: Insulating layer 208a, 208b, 208c: Dielectric layers 702: Air gap 1102, 1102a, 1102b, 1102c, 1102d: Top contact structure 1102e: Horizontally Extended Metallized Structure 1200: Semiconductor Device 1202: Display pixel array 1204: Display pixels 1206, 1206a, 1206b, 1206c, 1206d: Subpixels 1208: Circuit Layer 1210: Device Layer 1212: Interconnect layer 1214: Semiconductor layer 1216: Integrated circuit device 1218: Dielectric layer 1220: Metallized structure 1222: Interconnection Structure 1400, 1500: Semiconductor devices 1402a: First semiconductor die 1402b: Second semiconductor die 1404: Joint Interface 1406: Pixel sensor array 1408: Black Level Correction Area 1410: Jointing Pad Area 1412: Sealing ring area 1414: Pixel Sensor 1416: Device Layer 1418: Photodiode 1420: Floating Diffusion Node 1422: Transfer Gate 1424: Interconnection Layer 1426: Dielectric region 1428: Metallized Structure 1430: Interconnection Structure 1432: Device Layer 1434: Integrated circuit device 1436: Interconnection Layer 1438: Dielectric region 1440: Metallized structure 1442: Interconnection Structure 1444, 1446: Joint gaskets 1448, 1450: Connecting through holes 1600: Process 1610, 1620, 1630, 1640, 1650: Steps AA, BB, CC, DD, EE: lines x, y, z: Direction

[0173] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor structure, comprising: A bottom electrode structure includes a plurality of rows of back-end conductive structures in an interconnect layer of a semiconductor device, wherein the rows of back-end conductive structures define a plurality of trenches in the semiconductor structure; an insulating layer located on the sidewalls and bottom surface of the trenches, including a plurality of discontinuous segments, wherein each of the discontinuous segments is included in a corresponding one of the trenches; and a top electrode structure located on the insulating layer in the trenches.

2. The semiconductor structure as described in claim 1, wherein the bottom electrode structure further comprises: A horizontally extending conductive structure is located below the rows of rear conductive structures and below the trenches, wherein the horizontally extending conductive structure laterally spans the rows of rear conductive structures and the trenches.

3. The semiconductor structure as claimed in claim 1, wherein the insulating layer extends continuously between the trenches.

4. The semiconductor structure as claimed in claim 2, further comprising: a bottom contact structure located below the horizontally extending conductive structure, wherein the bottom contact structure is coupled to the horizontally extending conductive structure, and wherein the bottom contact structure is coupled to a transistor structure in a device layer below the interconnect layer of the semiconductor device.

5. The semiconductor structure as claimed in claim 1, wherein the top electrode structure includes a merged section located above the trenches, and wherein the merged section is coupled to a top contact structure of the semiconductor structure.

6. The semiconductor structure as claimed in claim 1, wherein the top electrode structure includes a plurality of discontinuous columns, wherein each of the discontinuous columns is included in a corresponding one of the trenches; and wherein each of the discontinuous columns is coupled to a separate top contact structure of the semiconductor structure.

7. A semiconductor structure comprising: A bottom electrode structure includes a plurality of rows of back-end conductive structures in an interconnect layer of a semiconductor device, wherein the rows of back-end conductive structures define a plurality of trenches in the semiconductor structure, and wherein each of the rows of back-end conductive structures includes an alternating arrangement of a plurality of vias and a plurality of metallization structures; an insulating layer is located on the sidewalls and bottom surface of the trenches; and a top electrode structure is located on the insulating layer in the trenches, wherein the top electrode structure includes a plurality of air gaps extending into the trenches.

8. The semiconductor structure as described in claim 7, wherein the insulating layer comprises a multilayer stack, and the multilayer stack comprises: A first low dielectric constant dielectric layer; A high dielectric constant dielectric layer is located on the first low dielectric constant dielectric layer; And a second low dielectric constant dielectric layer, located on the high dielectric constant dielectric layer.

9. The semiconductor structure as described in claim 7, wherein the bottom electrode structure further comprises: A first horizontally extending conductive structure is located below the rows of rear-end conductive structures and below the trenches, wherein the first horizontally extending conductive structure laterally spans the rows of rear-end conductive structures and the trenches; and wherein the semiconductor structure further includes: a bottom contact structure located below the first horizontally extending conductive structure, wherein the bottom contact structure is coupled to the first horizontally extending conductive structure; a plurality of second separate contact structures coupled to the top electrode structure in each of the trenches; and a second horizontally extending conductive structure located above the second separate contact structures and coupled to each of the second separate contact structures.

10. A method for forming a semiconductor structure, comprising: A plurality of dielectric layers are formed above a device layer of a semiconductor device, comprising an interconnect layer of the semiconductor device; a plurality of first rear-end conductive structures are formed in the dielectric layers; and a plurality of second rear-end conductive structures are formed, wherein the second rear-end conductive structures are arranged in a plurality of vertically extending columns, and the vertically extending columns correspond to a bottom electrode structure of a trench capacitor structure; the dielectric layers are etched through the vertically extending columns of the trench capacitor structure between adjacent pairs to form a plurality of trenches of the trench capacitor structure, wherein the vertically extending columns define a plurality of sidewalls of the trenches; an insulating layer of the trench capacitor structure is formed on the sidewalls of the trenches; and a top electrode structure of the trench capacitor structure is formed on the insulating layer in the trenches.

Images