Semiconductor device structure and methods of forming the same

Abstract

This disclosure provides a semiconductor device structure and a method for forming the same. The semiconductor device structure includes a first source / drain region, a second source / drain region, and a contact etch stop layer disposed adjacent to the first source / drain region. A first top surface of the first source / drain region is covered by the contact etch stop layer. The structure further includes a first conductive component disposed below the first and second source / drain regions, and the first conductive component is electrically connected to the first and second source / drain regions.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and in particular to the structure of semiconductor devices and methods for their fabrication. Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each with smaller and more complex circuits than previous generations. During the evolution of ICs, functional density (i.e., the number of interconnects per unit chip area) typically increases while geometric dimensions (i.e., the smallest components (or lines) that can be manufactured using a process) decrease. This miniaturization process usually benefits production efficiency and reduces associated costs. However, this size reduction also increases the complexity of manufacturing ICs.

[0003] Therefore, it is necessary to improve the fabrication and manufacturing process of integrated circuits. Summary of the Invention

[0004] In one embodiment, this disclosure provides a semiconductor device structure. The semiconductor device structure includes: a first source / drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer being different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region being different from the width of the first source / drain region; a second source / drain region disposed adjacent to the first source / drain region; a contact etch stop layer disposed above the first source / drain region, wherein a first top surface of the first source / drain region is covered by the contact etch stop layer; a first interlayer dielectric layer disposed above the contact etch stop layer; an etch stop layer disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and a first conductive component disposed below the first and second source / drain regions, wherein the first conductive component is electrically connected to the first and second source / drain regions.

[0005] In another embodiment, this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first source / drain region, including a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; a second source / drain region is disposed adjacent to the first source / drain region; a contact etch stop layer is disposed above the first source / drain region; a first interlayer dielectric layer is disposed above the contact etch stop layer; an etch stop layer is disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and a first conductive component is disposed below the first and second source / drain regions, wherein the first conductive component includes a first portion, a plurality of second portions extending from a plurality of edges of the first portion, and a third portion extending from the center of the first portion.

[0006] In yet another embodiment, this disclosure provides a method for forming a semiconductor device structure. The method includes: forming a first source / drain region, wherein the first source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; forming a second source / drain region adjacent to the first source / drain region; depositing a contact etch stop layer over the first and second source / drain regions; depositing a first interlayer dielectric layer over the contact etch stop layer; depositing an etch stop layer over the first interlayer dielectric layer and the contact etch stop layer; depositing a second interlayer dielectric layer over the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; flipping a semiconductor device structure; and forming a first conductive component over the first and second source / drain regions, wherein the first conductive component includes a first portion, a plurality of second portions extending from a plurality of edges of the first portion, and a third portion extending from the center of the first portion. Simple Explanation of the Diagram

[0007] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention. Figures 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 are perspective views illustrating various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 13, 14, 15, 16 and 17 are schematic cross-sectional views illustrating various stages of manufacturing a semiconductor device structure according to some embodiments. Figure 18 is a top view illustrating the structure of a semiconductor device according to some embodiments. Figures 19A and 19B are cross-sectional side views of a semiconductor device structure drawn along line AA of Figure 18, according to some embodiments. Figure 20 is a cross-sectional side view of a semiconductor device structure drawn along line BB of Figure 18 according to some embodiments. Figures 21A and 21B are cross-sectional side views of a semiconductor device structure drawn along the CC line of Figure 18 according to some embodiments. Figure 22 is a top view illustrating the structure of a semiconductor device according to an alternative embodiment. Figures 23A and 23B are cross-sectional side views of a semiconductor device structure drawn along line DD of Figure 22 according to some embodiments. Figures 24, 25, 26 and 27 are top views illustrating the structure of a semiconductor device according to an alternative embodiment. Implementation

[0008] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] While the embodiments described in this disclosure relate to nanostructured channel field-effect transistors (FETs), such as horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and other suitable devices, some of the embodiments described herein can be used in other processes and / or other devices, such as FinFETs, planar FETs, and other suitable devices. Those skilled in the art will readily understand that other modifications can be conceived within the scope of this disclosure. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the structure. Generally, dual-patterning or multi-patterning processes combine lithography with self-alignment processes to create, for example, patterns with smaller pitch than those obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a GAA structure.

[0011] Figures 1 through 17 illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to various embodiments of the present disclosure. It should be understood that, for additional embodiments of the method, additional steps may be provided before, during, and after the processes shown in Figures 1 through 17, and some steps described below may be replaced or omitted. The order of steps / processes is not limited and can be interchanged.

[0012] Figures 1 to 12 are perspective views illustrating various stages of fabricating a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0013] The substrate 101 may include regions that are doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus in n-type field-effect transistors (NFETs) and boron in p-type field-effect transistors (PFETs).

[0014] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices, such as nanostructure channel FETs. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 includes alternating first and second semiconductor layers 106, 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or different oxidation rates. For example, the first semiconductor layer 106 may be made of silicon, and the second semiconductor layer 108 may be made of silicon-germanium. In some examples, the first semiconductor layer 106 may be made of silicon-germanium, and the second semiconductor layer 108 may be made of silicon. Alternatively, in some embodiments, any of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0015] The first and second semiconductor layers 106 and 108 are formed by any suitable deposition process, such as epitaxy. As an example, the epitaxial growth of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0016] The first semiconductor layer 106 or the aforementioned portion may form nanostructure channels of the semiconductor device structure 100 in subsequent manufacturing stages. As used herein, the term "nanostructure" refers to any material portion having a nanometer or even micrometer scale and an elongated shape, regardless of its cross-sectional shape. Thus, the term refers to circular and substantially circular elongated material portions, as well as beam or bar-shaped material portions having, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MCB) transistors, or any transistor having gate electrodes surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0017] Each first semiconductor layer 106 has a thickness ranging from about 3 nm to about 30 nm, for example from about 3 nm to about 10 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. The three first semiconductor layers 106 and the three second semiconductor layers 108 are arranged alternately as shown in FIG1, which is for illustrative purposes only and is not intended to limit the scope beyond that expressly stated in the claims. It is understood that any number of first and second semiconductor layers 106, 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. As shown in FIG1, an oxide layer 110 is formed on top of the first semiconductor layer 106, and a nitride layer 111 is formed on top of the oxide layer 110. The oxide layer 110 may be silicon oxide and may have a different etch selectivity relative to the nitride layer 111. The nitride layer 111 may comprise any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 may be a masking structure.

[0018] In Figure 2, fin structures 112 are formed from semiconductor layer stacks 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. Fin structures 112 can be formed by patterning a hard mask layer, such as an oxide layer 110 and a nitride layer 111, on the semiconductor layer stack 104 using multiple patterning operations including optical lithography and etching processes. Etching processes can include dry etching, wet etching, reactive-ion etching (RIE), and / or other suitable processes. Optical lithography processes can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element containing the photoresist layer. In some embodiments, an electron beam lithography process can be performed to pattern the photoresist layer to form the mask element. The etching process passes through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in the unprotected area to form trenches 114, thereby leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, or a combination of the foregoing.

[0019] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation is performed, such as chemical mechanical polishing (CMP) and / or etch-back, to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0020] In Figure 4, insulating material 118 is etched to form isolation region 120. The grooves in insulating material 118 expose portions of fin structure 112, such as semiconductor layer stack 104. Isolation region 120 can be formed by suitable processes, such as dry etching, wet etching, or a combination thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed by substrate 101. In some embodiments, isolation region 120 is a shallow trench isolation (STI) region. In some embodiments, oxide layer 110 and nitride layer 111 are also removed during the etching of insulating material 118.

[0021] In Figure 5, one or more sacrificial gate structures 130 are formed over a semiconductor device structure 100. The sacrificial gate structure 130 is formed over a first portion of the fin structure 112 and a first portion of the isolation region 120, while a second portion of the fin structure 112 and a second portion of the isolation region 120 are exposed. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. In some embodiments, the masking layer 136 is a multilayer structure. For example, the masking layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning those layers into the sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. Multiple portions of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serve as channel regions of the semiconductor device structure 100.

[0022] In Figure 6, a gate spacer layer 138 is formed to cover the second portion of the sacrificial gate structure 130, the fin structure 112, and the second portion of the isolation region 120. The gate spacer layer 138 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. In some embodiments, the gate spacer layer 138 is formed through a compliant process, such as atomic layer deposition (ALD).

[0023] In Figure 7, an anisotropic etching process is performed to remove the horizontal portion of the gate spacer layer 138. The anisotropic etching process can be a selective etching process, which essentially does not affect the nitride layer 137, the first semiconductor layer 106, and the isolation region 120. As a result, the second portion of the fin structure 112 is exposed.

[0024] In Figure 8, one or more etching processes are performed to etch the second portion of the fin structure 112 not covered by the sacrificial gate structure 130 (and a portion of the gate spacer layer 138 formed on the sidewall of the sacrificial gate structure 130) and remove a portion of the gate spacer layer 138. The portion of the gate spacer layer 138 formed on the sidewall of the mask layer 136 may also be etched. One or more etching processes may include dry etching, such as reactive ion etching, neutral beam etching (NBE), and / or wet etching, such as using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH). The aforementioned etching processes form a gate spacer 140, which includes a first portion 140a formed on the sidewall of the sacrificial gate electrode layer 134 and a second portion 140b formed on the second portion of the isolation region 120. In some embodiments, the aforementioned etching processes also remove some portions of the second portion of the isolation region 120, as shown in Figure 8. In this way, the top surface 120t of the second part of the isolation region 120 is located at a level substantially lower than the top surface 116t of the substrate portion 116.

[0025] As shown in Figure 9, the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. Removing the edge portions of the second semiconductor layer 108 creates cavities. In some embodiments, the edge portions of the second semiconductor layer 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0026] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144, as shown in FIG10. The dielectric spacers 144 may be made of a low dielectric constant dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. A compliant dielectric layer may be formed first using a compliant deposition process, such as ALD, followed by anisotropic etching to remove portions of the compliant dielectric layer except for the dielectric spacers 144, thereby forming the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layers 108 are capped along the X direction between the dielectric spacers 144.

[0027] As shown in Figure 11, the source / drain (S / D) region 146 is formed from the substrate portion 116. In some embodiments, the source / drain region 146 may be grown vertically and horizontally to form facets, which may correspond to crystal planes of the material used for the substrate portion 116. In this disclosure, the terms source region and drain region are used interchangeably, and the structures described above are substantially the same. Furthermore, source / drain region may refer to source or drain individually or collectively, depending on the context. In some embodiments, the source / drain region 146 is an n-type source / drain epitaxial component and may be made of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. In some embodiments, the source / drain region 146 is a p-type epitaxial component and may be made of one or more layers of Si, SiGe, and Ge for a p-channel FET. For a p-channel FET, the source / drain region 146 may also include a p-type dopant, such as boron (B). The source / drain region 146 can be formed by epitaxial growth methods such as chemical vapor deposition (CVD), atomic layer deposition, or molecular beam epitaxy. In some embodiments, the thickness of the source / drain region 146 along the Z direction is different from the width of the source / drain region 146 along the Y direction.

[0028] In some embodiments, a semiconductor layer 202 (FIG. 13) is first formed on a substrate portion 116, a dielectric layer 204 (FIG. 13) is formed on the semiconductor layer 202, and a source / drain region 146 is formed from the first semiconductor layer 106. The semiconductor layer 202 may be undoped silicon, while the dielectric layer 204 may be a nitride layer, such as a SiN layer.

[0029] After forming the source / drain region 146, a contact etch stop layer (CESL) 162 is compliantly formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the first portion 140a of the gate spacer 140 and is disposed on the second portion 140b of the gate spacer 140 and the source / drain region 146. CESL 162 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbonitride, silicon oxide, silicon oxycarbide, or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on CESL 162. The material of the interlayer dielectric layer 163 may include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (such as polymers) may also be used for the interlayer dielectric layer 163. The interlayer dielectric layer 163 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the interlayer dielectric layer 163 is formed, the semiconductor device structure 100 may undergo heat treatment to anneal the interlayer dielectric layer 163.

[0030] A planarization process is performed to expose the sacrificial gate electrode layer 134, as shown in Figure 11. The planarization process can be any suitable process, such as CMP. The planarization process removes portions of the interlayer dielectric layer 163 and CESL 162 disposed on the sacrificial gate structure 130. The planarization process may also remove the masking layer 136.

[0031] As shown in Figure 12, the sacrificial gate electrode layer 134, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed to expose a portion of the first semiconductor layer 106, and a gate dielectric layer 170 and a gate electrode layer 172 are formed to surround the exposed portion of the first semiconductor. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 can be removed, which can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as tetramethylammonium hydroxide solution, can be used to selectively remove the sacrificial gate electrode layer 134, but not the spacer 140, the interlayer dielectric layer 163, and CESL 162.

[0032] The second semiconductor layer 108 can be removed using a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe without materially affecting the Si, the dielectric material of the spacer 140, the interlayer dielectric layer 163, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant, such as a fluorine-based (e.g., F2) or chlorine-based (e.g., Cl2) gas, or any suitable isotropic etchant.

[0033] As shown in Figure 12, the gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. The interface layer 168 may include oxides, such as silicon oxide, and may be formed as a result of a cleaning process. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed using CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may contain one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed using CVD, ALD, electroplating, or other suitable deposition techniques. The gate dielectric layer 170 and the gate electrode layer 172 may also be deposited on the interlayer dielectric layer 163. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed on the interlayer dielectric layer 163 are removed using, for example, CMP, until the top surface of the interlayer dielectric layer 163 is exposed.

[0034] As shown in FIG13, another etch stop layer 206 is deposited on the interlayer dielectric layer 163, and another interlayer dielectric layer 208 is deposited on the etch stop layer 206. The etch stop layer 206 may comprise the same material as CESL 162, and the interlayer dielectric layer 208 may comprise the same material as interlayer dielectric layer 163. In some embodiments, the thickness of interlayer dielectric layer 163 is greater than the thickness of interlayer dielectric layer 208. In some embodiments, openings (not shown) are formed in interlayer dielectric layer 208, etch stop layer 206, interlayer dielectric layer 163, and CESL 162 to expose source / drain region 146, and conductive members (not shown) are formed in the openings, which are electrically connected to source / drain region 146 through a silicon layer (not shown). The conductive members provide power or signals from the front side of semiconductor device structure 100 to source / drain region 146. In some embodiments, power is supplied to certain source / drain regions 146 from the back side of the semiconductor device structure 100, and conductive components are not formed over the source / drain regions 146 on the front side of the semiconductor device structure 100. In some embodiments, conductive components are formed over some source / drain regions 146, while other source / drain regions 146 do not have conductive components on the front side. Conductive components (not shown) may be formed in the interlayer dielectric layer 208 and the etch stop layer 206 to electrically connect to the gate structure 174.

[0035] Next, an interconnect structure 200 is formed over the interlayer dielectric layer 208. The interconnect structure 200 includes a plurality of intermetallic dielectric (IMD) layers 201 and conductive components 203, such as wires and vias, formed in the intermetallic dielectric layers 201. The interconnect structure 200 may further include a passivation layer, an adhesive layer, and / or other layers formed on the front side of the semiconductor device structure 100. Next, a carrier substrate (not shown) is attached to the front side of the semiconductor device structure 100, and the semiconductor device structure 100 is flipped over for back-side processing, as shown in FIG13. In some embodiments, the substrate 101 is thinned until the insulating material 118 is exposed, as shown in FIG13. The thinning process may include a mechanical polishing process and / or a chemical thinning process. In the mechanical polishing process, a large amount of substrate material may be removed from the substrate 101 first. Subsequently, the chemical thinning process may apply etching chemicals to the back side of the substrate 101 to further thin the substrate 101.

[0036] As shown in Figure 13, a hard mask layer 210 is deposited on the back side of the semiconductor device structure 100, and a three-layer impedance layer 212 is formed on the hard mask layer 210. The hard mask layer 210 may include oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiOxNy), etc. In a further embodiment, the hard mask layer 210 is a high-temperature oxide (HTO) (e.g., SiO2 formed by a high-temperature deposition / growth process). In some embodiments, the process for forming the hard mask layer 210 includes depositing a dielectric material on the back side of the semiconductor device structure 100 through, for example, chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition, sputtering, some other deposition processes, or combinations thereof.

[0037] The three-layer impedance layer 212 includes a bottom layer 214 above the hard mask layer 210, an intermediate layer 216 above the bottom layer 214, and an upper layer 218 above the intermediate layer 216. The bottom layer 214 may be a bottom anti-reflective coating (BAC). The bottom layer 214 may include an organic material. The intermediate layer 216 may be formed of or include an inorganic material, such as a nitride (e.g., silicon nitride), an oxide nitride (e.g., silicon oxynitride), or an oxide (e.g., silicon oxide). The upper layer 218 is a photosensitive material. In some embodiments, the impedance layer formed above the hard mask layer 210 may be another type of photoresist, such as a single-layer photoresist, a double-layer photoresist, etc. The upper layer 218 is patterned using any suitable optical lithography technique to form trench openings 220 therein.

[0038] As shown in FIG. 14, the trench opening 220 extends to the hard mask layer 210 and selectively etches the substrate portion 116 to form a back via 222. The pattern of the upper layer 218 is transferred to the intermediate layer 216 using an appropriate etching process. Next, an appropriate etching process is performed to transfer the pattern of the intermediate layer 216 to the bottom layer 214, thereby causing the trench opening 220 to extend through the bottom layer 214. Further, the pattern of the bottom layer 214 is transferred to the intermediate layer 216 using an appropriate etching process. In one embodiment, an etching process for etching the bottom layer 214 continues to etch the hard mask layer 210. During the etching process, the upper layer 218, the intermediate layer 216, and the bottom layer 214 may be consumed. In some embodiments, an ashing process may be performed to remove any remaining residue from the bottom layer 214. After the pattern of the hard mask layer 210 exposes the back side of the semiconductor device structure 100, the etching process is adjusted and performed to be selective for the material of the substrate portion 116. In this embodiment, the etching process also etches the semiconductor layer 202. The dielectric layer 204 can serve as an etch stop layer to protect the source / drain region 146 from etching. The etching process can be dry etching, wet etching, reactive ion etching, and / or other suitable etching methods.

[0039] In some embodiments, the etching process for removing substrate portions 116 also removes horizontal portions of insulating material 118 located between adjacent substrate portions 116, as shown in FIG14. In some embodiments, portions of CESL 162 and portions of interlayer dielectric layer 163 located below the horizontal portions of insulating material 118 may also be removed, as shown in FIG14. In some embodiments, openings in interlayer dielectric layer 163 have a width that decreases along the Y direction, as shown in FIG14. In some embodiments, openings in interlayer dielectric layer 163 have a width that remains substantially constant along the Y direction.

[0040] As shown in Figure 15, a dielectric liner 230 is formed on the sidewall of the trench opening 220 (including the back via 222). The dielectric liner 230 further protects the gate structure 174 from metal element diffusion when conductive components are subsequently formed in the trench opening 220. In some embodiments, the dielectric liner 230 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable materials. The dielectric liner 230 may be deposited using ALD, CVD, or other suitable methods. Subsequently, an anisotropic etching process is performed to remove the horizontal portion of the dielectric liner 230. This serves as an etch stop layer exposed in the back via 222. In the illustrated embodiment, as a result of the anisotropic etching process, a portion of the dielectric liner 230 remains on the sidewall of the insulating material 118. The dielectric liner 230 may also contact the second portion 140b of the gate spacer 140. After the anisotropic etching process, the dielectric layer 204, which serves as an etch stop layer, is exposed in the back via 222. Subsequently, an etching process is applied to remove the exposed portion of the dielectric layer 204. The etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. After the etching process, the back via 222 exposes the bottom surface of the source / drain region 146 from the back. A portion of the dielectric layer 204 may remain between the source / drain region 146 and the dielectric liner 230.

[0041] As shown in Figure 15, conductive components 232 are formed in the trench opening 220 and the back via 222. The conductive components 232 may comprise any suitable conductive material, such as tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed using CVD, ALD, electroplating, or other suitable deposition techniques. In some embodiments, a silicon layer 234 is formed between the conductive components 232 and the source / drain region 146. The silicon layer 234 reduces the contact resistance between the source / drain region 146 and the conductive components 232. The silica layer 234 can be formed by depositing one or more metals into the back via 222, performing an annealing process to allow the one or more metals to react with the source / drain region 146, removing unreacted portions of the one or more metals, and leaving the silica layer 234 in the back via 222. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Jr), erbium (Er), cobalt (Co), or combinations thereof (e.g., alloys of two or more metals), and can be deposited using CVD, PVD, ALD, or other suitable methods. The silicate layer 234 may include titanium silicate (TiSi), nickel silicate (NiSi), tungsten silicate (WSi), nickel platinum silicate (NiPtSi), nickel platinum germanium silicate (NiPtGeSi), nickel germanium silicate (NiGeSi), ytterbium silicate (YbSi), platinum silicate (PtSi), iridium silicate (IrSi), erbium silicate (ErSi), cobalt silicate (CoSi), combinations thereof, or other suitable compounds. Alternatively, the conductive component 232 may directly contact the two source / drain regions 146.

[0042] As shown in Figure 16, a planarization process, such as a CMP process, is performed to remove portions of the conductive component 232 formed on the hard mask layer 210. In some embodiments, the top surface of the conductive component 232 and the top surface of the hard mask layer 210 are substantially coplanar. The conductive component 232 has a first portion 232a and a second portion 232b extending from the edge of the first portion 232a, as shown in Figure 16. The conductive component 232 may also include a third portion 232c extending from the center of the first portion 232a. The conductive component 232 is monolithic, and the first, second, and third portions 232a, 232b, and 232c are defined by an imaginary line L, as shown in Figure 16. The first portion 232a has a height H1, the second portion 232b has a height H2, and the third portion 232c has a height H3. The imaginary line L can be drawn at a position such that the height H1 remains constant. In some embodiments, the height H1 is less than the height H2, and the height H3 is less than the height H1, as shown in Figure 16. In some embodiments, height H1 is greater than height H2. The third part 232c provides a larger volume for the conductive component 232. This reduces resistance.

[0043] As shown in Figure 17, a back-side interconnect structure 250 is formed on a hard mask layer 210 and a conductive component 232. The back-side interconnect structure 250 includes one or more inter-metal dielectric layers 252 and conductive components 254 formed in the inter-metal dielectric layers 252.

[0044] In some embodiments, the semiconductor device structure 100 includes a logic device. For the logic device, a higher voltage is applied to the source / drain regions and a lower voltage is applied to the gate. If the conductive portion of the source / drain region 146 of the logic device is located on the front side of the semiconductor element structure 100 of the adjacent gate structure 174, a high capacitance (Cgd) will exist between the conductive portion of the source / drain region 146 and the adjacent gate structure 174. To reduce Cgd, the conductive portion 232 of the source / drain region 146 is moved to the back side of the semiconductor device structure 100, as shown in FIG17. In some embodiments, the conductive portion 232 is electrically connected to both source regions 146, as shown in FIG17. A larger conductive portion 232 reduces resistance.

[0045] Figure 18 is a top view illustrating the fabrication of a semiconductor device structure 100 according to some embodiments. As shown in Figure 18, a gate electrode layer 172 extends along the Y direction, source regions 146s are disposed on one side of the gate electrode layer 172, and drain regions 146d are disposed on the other side of the gate electrode layer 172. The gate electrode layer 172 can be separated by a dielectric layer 260 through a cut metal gate (CMG) process. Conductive components 262 can be disposed on the gate electrode layer 172, for example, through the interlayer dielectric layer 208 and the etch stop layer 206 (Figure 17), to serve as gate contacts. Conductive components 232 are electrically connected to the two source regions 146s. In some embodiments, a conductive component 256 corresponding to one of the two source regions 146s, the drain region 146d, is formed on the front side of the semiconductor device structure 100. In some embodiments, the conductive member 256 extends across and is electrically connected to both drain regions 146d, as shown in FIG18. In some embodiments, the width of the conductive member 232 along the X direction is substantially the same as the width of the conductive member 256 along the X direction, as shown in FIG18. A conductive member 258 may be formed on the conductive member 256.

[0046] Figures 19A and 19B are cross-sectional side views of a semiconductor device structure 100 fabricated according to some embodiments, drawn along line AA of Figure 18. In some embodiments, as shown in Figure 19A, the conductive component 232 includes a first portion 232a having a height H1 and a second portion 232b having a height H2 less than the height H1. Because the first portion 232a has a larger height H1, the volume of the conductive component 232 increases compared to the conductive component 232 shown in Figure 16. As a result, the resistance of the conductive component 232 decreases. The height H1 can be controlled by controlling the etching process to form the trench opening 220 and the back via 222. If the etching chemical in the etching process has low selectivity, more interlayer dielectric layer 163 will be removed, and the height H1 will increase. If the etching chemical reaction is more selective, less interlayer dielectric layer 163 will be removed, and the height H1 will decrease.

[0047] In some embodiments, as shown in FIG19B, the conductive component 232 includes a third portion 232c. Due to the third portion 232c, the resistance of the conductive component 232 is further reduced.

[0048] Figure 20 is a cross-sectional side view of a semiconductor device structure 100 fabricated according to some embodiments, drawn along line BB of Figure 18. As shown in Figure 20, in some embodiments, the source region 146s of the transistor is electrically connected to a conductive component 232 located below the source region 146s, and the drain region 146d of the transistor is electrically connected to a conductive component 256 located above the drain region 146d. By placing the conductive components 232 and 256 on opposite sides of the semiconductor device structure 100, Cgd is reduced. In some embodiments, the drain region 146d is electrically connected to the conductive component 158 ​​through a silicon layer 268. The silicon layer 268 may comprise the same material as the silicon layer 234 and may be formed through the same process as the silicon layer 234. In some embodiments, a dielectric liner 270 is disposed along the sidewall of the conductive component 256. The dielectric liner 270 may include the same material as the dielectric liner 230 and may be formed by the same process as the dielectric liner 230.

[0049] In some embodiments, both the source region 146s and the drain region 146d include a first epitaxial layer 290 and a second epitaxial layer 292. In some embodiments, both the first and second epitaxial layers 290 and 292 are doped with a dopant, such as a p-type dopant or an n-type dopant. The dopant concentration in the first epitaxial layer 290 is different from the dopant concentration in the second epitaxial layer 292.

[0050] Figures 21A and 21B are cross-sectional side views of a semiconductor device structure 100 fabricated according to some embodiments, drawn along line CC of Figure 18. As shown in Figure 21A, in some embodiments, the conductive component 232 may extend through the hard mask layer 210, the insulating material 118, CESL 162, and into the interlayer dielectric layer 163, serving as an etch stop layer. In some embodiments, as shown in Figure 21B, the conductive component 232 does not extend into CESL 162. The etch chemicals of CESL 162 may be used, and CESL 162 may serve as an etch stop layer. CESL 162 may serve as an etch stop layer when forming trench openings 220 and back vias 222. The extension of the conductive component 232 through or stopping at CESL 162 can be controlled by controlling the etching process to form trench openings 220 and back via openings 222. CESL 162 may serve as an etch stop layer by using etch chemicals that do not affect CESL 162. On the other hand, by using etching chemicals that also etch CESL 162, trench openings 220 also extend through CESL 162 and into interlayer dielectric layer 163.

[0051] Figure 22 is a top view illustrating the fabrication of a semiconductor device structure 100 according to an alternative embodiment. In some embodiments, conductive components 256 are also located on the back side of the semiconductor device structure 100, as shown in Figure 22. As described above, the voltage applied to the source region 146s and drain region 146d of the logic device is relatively high compared to the voltage applied to the gate electrode layer 172. Therefore, by placing the conductive components 232 and 256 of the source region 146s and drain region 146d on the back side of the semiconductor device structure 100, respectively, the conductive components 232 and 256 have a smaller overlap area with the gate electrode layer 172, and Cgd is further reduced.

[0052] Figures 23A and 23B are cross-sectional side views of a semiconductor device structure 100 fabricated according to some embodiments, drawn along line DD of Figure 22. In some embodiments, as shown in Figure 23A, a conductive member 256 extends through a hard mask layer 210, a substrate portion 116, a semiconductor layer 202, and a dielectric layer 204, and is electrically connected to a drain region 146d through a silicon layer 268. A dielectric liner 270 is located along the sidewall of the conductive member 256, as shown in Figure 23A.

[0053] In some embodiments, as shown in FIG23B, the dielectric liner 270 is replaced by an air gap 280 to further reduce capacitance. The air gap 280 may be formed by forming a liner on the sidewalls of the substrate 116 and hard mask layer 210 in the opening before forming the conductive element 256 in the opening. The liner may comprise a material different from the hard mask layer 210 and the conductive element 256. In some embodiments, the liner is made of amorphous silicon. Next, the conductive element 256 is formed in the opening adjacent to the liner. The liner is then removed to form the air gap 280. The liner may be removed by a selective etching process that does not materially affect the hard mask layer 210 and the conductive element 256. The air gap 280 may be formed around the conductive element 256 and / or the conductive element 232.

[0054] Figures 24, 25, 26, and 27 are top views illustrating the fabrication of a semiconductor device structure 100 according to an alternative embodiment. In some embodiments, as shown in Figure 24, conductive members 256 are formed on the front side of the semiconductor device structure 100, while conductive members 232 are formed on the back side of the semiconductor device structure 100. Since the conductive members on the back side of the semiconductor device structure 100 are less crowded, the size of conductive member 232 may be larger than the size of conductive member 256. In some embodiments, the width of conductive member 232 along the X direction is greater than the width of conductive member 256 along the X direction. Due to the larger width, the resistance of conductive member 232 is reduced.

[0055] In some embodiments, as shown in FIG25, conductive components 232 and 256 are located on the back side of the semiconductor device structure 100. Conductive component 232 is electrically connected to a first source region 146s1 and a second source region 146s2, while conductive component 256 is electrically connected to a first drain region 146d1 and a second drain region 146d2, with the second drain region 146d2 corresponding to the second source region 146s2. In some embodiments, the size of the portion of conductive component 232 electrically connected to the first source region 146s1 is larger than the size of the portion of conductive component 232 electrically connected to the second source region 146s2, as shown in FIG25. The size of the portion of conductive component 232 electrically connected to the second source region 146s2 is reduced to reduce parasitic capacitance. In other words, because the size of the portion of conductive component 232 is reduced, the distance between the portion of conductive component 232 electrically connected to the second source region 146s2 and conductive component 256 increases, thereby reducing parasitic capacitance.

[0056] In some embodiments, as shown in FIG25, the conductive component 232 includes a first portion 232d located below the source region 146s1 and a second portion 232e located below the source region 146s2. The width of the first portion 232d along the X direction is greater than the width of the second portion 232e along the X direction. In some embodiments, the side of the first portion 232d and the side of the second portion 232e form an angle A, and the angle A can range from about 80 degrees to about 180 degrees. As shown in FIG25, in some embodiments, the angle A can be a right angle. The angle A can be determined by an optical lithography process to form an opening in the conductive component 232. In some embodiments, the optical lithography process can form an opening including two rectangular openings, and the two rectangular openings have different sizes. FIG25 illustrates the conductive component 232 deposited in such an opening.

[0057] In some embodiments, as shown in FIG26, the first portion 232d and the second portion 232e are connected via a connecting portion 232f having a trapezoidal shape. The first, second, and connecting portions 232d, 232e, and 232f are monolithic and defined by imaginary lines L1 and L2. In some embodiments, the connecting portion 232f has curved side surfaces, as shown in FIG26. In some embodiments, the connecting portion 232f has flat side surfaces.

[0058] In some embodiments, as shown in FIG27, the conductive component 232 has a trapezoidal shape, with its larger end located below the source region 146s1 and its smaller end located below the source region 146s2. Using the conductive component 232 in the various embodiments shown in FIGS. 24 to 27, the resistance of the conductive component 232 is reduced, while parasitic capacitance is minimized.

[0059] The embodiments disclosed herein provide a semiconductor device structure 100 having a conductive component 232 located on the back side of the semiconductor device structure 100. In some embodiments, the conductive component 232 is electrically connected to two source / drain regions 146. Some embodiments may achieve advantages. For example, by positioning the conductive component 232 on the back side of the semiconductor device structure 100, Cgd is reduced.

[0060] In one embodiment, this disclosure provides a semiconductor device structure. The semiconductor device structure includes: a first source / drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer being different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region being different from the width of the first source / drain region; a second source / drain region disposed adjacent to the first source / drain region; a contact etch stop layer disposed above the first source / drain region, wherein a first top surface of the first source / drain region is covered by the contact etch stop layer; a first interlayer dielectric layer disposed above the contact etch stop layer; an etch stop layer disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and a first conductive component disposed below the first and second source / drain regions, wherein the first conductive component is electrically connected to the first and second source / drain regions. In one or more of the foregoing or following embodiments, the first conductive member includes a first portion located below a first source / drain region and a second portion located below a second source / drain region, wherein the width of the first portion is greater than the width of the second portion. In one or more of the foregoing or following embodiments, the side surface of the first portion of the first conductive member forms an angle with the side surface of the second portion of the first conductive member, and the angle ranges from about 80 degrees to about 180 degrees. In one or more of the foregoing or following embodiments, the angle is a right angle. In one or more of the foregoing or following embodiments, the first conductive member extends through a contact etch stop layer and enters a first interlayer dielectric layer disposed between the first and second source / drain regions. In one or more of the foregoing or following embodiments, it further includes: a second conductive member electrically connected to the second source / drain region. In one or more of the foregoing or following embodiments, the second conductive member is disposed above the second source / drain region and extends through the first interlayer dielectric layer and the contact etch stop layer. In one or more of the foregoing or following embodiments, the second conductive member is disposed below the second source / drain region. In one or more of the foregoing or following embodiments, it further includes: an air gap surrounding the second conductive member.

[0061] In another embodiment, this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first source / drain region, including a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; a second source / drain region is disposed adjacent to the first source / drain region; a contact etch stop layer is disposed above the first source / drain region; a first interlayer dielectric layer is disposed above the contact etch stop layer; an etch stop layer is disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and a first conductive component is disposed below the first and second source / drain regions, wherein the first conductive component includes a first portion, a plurality of second portions extending from a plurality of edges of the first portion, and a third portion extending from the center of the first portion. In one or more of the foregoing or following embodiments, the first part, the second part, and the third part are single-unit structures. In one or more of the foregoing or following embodiments, the first part has a first height, the second part has a second height different from the first height, and the third part has a third height different from the second height. In one or more of the foregoing or following embodiments, the first height is greater than the second height, and the second height is greater than the third height. In one or more of the foregoing or following embodiments, the second height is greater than the first height, and the first height is greater than the third height. In one or more of the foregoing or following embodiments, it further includes: a gate electrode layer, a third source / drain region, a fourth source / drain region, and a fifth source / drain region, wherein the second and fourth source / drain regions are disposed on opposite sides of the gate electrode layer, and the third and fifth source / drain regions are disposed on opposite sides of the gate electrode layer. In one or more of the foregoing or following embodiments, it further includes: a second conductive member electrically connected to the fourth and fifth source / drain regions.

[0062] In yet another embodiment, this disclosure provides a method for forming a semiconductor device structure. The method includes: forming a first source / drain region, wherein the first source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; forming a second source / drain region adjacent to the first source / drain region; depositing a contact etch stop layer over the first and second source / drain regions; depositing a first interlayer dielectric layer over the contact etch stop layer; depositing an etch stop layer over the first interlayer dielectric layer and the contact etch stop layer; depositing a second interlayer dielectric layer over the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; flipping a semiconductor device structure; and forming a first conductive component over the first and second source / drain regions, wherein the first conductive component includes a first portion, a plurality of second portions extending from a plurality of edges of the first portion, and a third portion extending from the center of the first portion. In one or more of the foregoing or following embodiments, forming the first conductive component includes: thinning the substrate to expose the insulating material; depositing a hard mask layer on the insulating material; and forming an opening in the hard mask layer and the insulating material. In one or more of the foregoing or following embodiments, forming the opening includes: removing a first substrate portion disposed over a first source / drain region and removing a second substrate portion disposed over a second source / drain region. In one or more of the foregoing or following embodiments, forming the opening includes: removing a first semiconductor layer and a first dielectric layer disposed over the first source / drain region, and removing a second semiconductor layer and a second dielectric layer disposed over the second source / drain region.

[0063] 100: Semiconductor Device Structure 101,116:Substrate 104: Semiconductor layer stacking 106, 108, 150, 202: Semiconductor layers 110, 135: Oxide layer 111,137: Nitride layer 112: Fin structure 114: Trench 116: Substrate portion 116t: Top surface of the substrate portion 118: Insulating materials 120: Isolation Zone 120t: Top surface of the second part of the isolation zone 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 136: Masking layer 138: Gate spacer layer 140, 140a, 140b: Gate spacers 144: Dielectric spacer 146: Source / Drain Region 146s, 146s1, 146s2: Source pole region 146d, 146d1, 146d2: Drain region 158,203,232,232a,232b,232c,232d,232e,232f,254,256,258,262: Conductive components 162: Contact Etching Stop Layer (CESL) 163, 164: Interlayer Dielectric (ILD) Layer 168: Interface Layer 170: Gate dielectric layer 172: Gate electrode layer 174: Gate Structure 200: Interconnection Structure 201,252: Intermetallic dielectric layer 204, 260: Dielectric layer 206: Etching Stop Layer 208: Interlayer dielectric layer 210: Masking layer 212: Three-layer impedance layer 214: Bottom Layer 216: Intermediate Layer 218: Upper Level 220: Groove opening 222: Backside through hole 230, 270: Dielectric sheath 234, 268: Silicon layer 250: Backside interconnect structure 280: Air gap 290, 292: Epitaxial layers AA, BB, CC, DD: lines H1, H2, H3: Height L1, L2: Imaginary lines X, Y, Z: Direction

Claims

1. A semiconductor device structure, comprising: A first source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, the concentration of the dopant in the first epitaxial layer being different from the concentration of the dopant in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; a second source / drain region is disposed adjacent to the first source / drain region; a contact etch stop layer is disposed on the first source / drain region, wherein a first top surface of the first source / drain region is covered by the contact etch stop layer; a first interlayer dielectric layer is disposed on the contact etch stop layer; an etch stop layer is disposed on a top surface of the contact etch stop layer and a top surface of the first interlayer dielectric layer; A second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and a first conductive component is disposed below the first and second source / drain regions, wherein the first conductive component is electrically connected to the first and second source / drain regions.

2. The semiconductor device structure as claimed in claim 1, wherein the first conductive component includes a first portion located below the first source / drain region and a second portion located below the second source / drain region, wherein the width of the first portion is greater than the width of the second portion.

3. The semiconductor device structure as claimed in claim 2, wherein a side of the first portion of the first conductive member forms an angle with a side of the second portion of the first conductive member, and the angle ranges from about 80 degrees to about 180 degrees.

4. The semiconductor device structure as described in claim 1 or 2, wherein the first conductive member extends through the contact etch stop layer and into the first interlayer dielectric layer disposed between the first and second source / drain regions.

5. The semiconductor device structure as described in claim 1, further comprising: A second conductive component is electrically connected to the second source / drain region.

6. The semiconductor device structure as claimed in claim 5, wherein the second conductive component is disposed above the second source / drain region and extends through the first interlayer dielectric layer and the contact etch stop layer.

7. The semiconductor device structure as described in claim 5, wherein the second conductive component is disposed below the second source / drain region.

8. A semiconductor device structure, comprising: A first source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, the concentration of the dopant in the first epitaxial layer being different from the concentration of the dopant in the second epitaxial layer, and in a cross-sectional view, the thickness and width of the first source / drain region are different; a second source / drain region is disposed adjacent to the first source / drain region; a contact etch stop layer is disposed above the first source / drain region; a first interlayer dielectric layer is disposed above the contact etch stop layer; an etch stop layer is disposed above a top surface of the contact etch stop layer and a top surface of the first interlayer dielectric layer; A second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; and a first conductive component is disposed below the first and second source / drain regions, wherein the first conductive component includes a first portion, a plurality of second portions extending from a plurality of edges of the first portion, and a third portion extending from a center of the first portion.

9. The semiconductor device structure as described in claim 8, wherein the first part, the second part, and the third part are monolithic.

10. The semiconductor device structure as claimed in claim 8, wherein the first portion has a first height, the second portion has a second height different from the first height, and the third portion has a third height different from the second height.

11. The semiconductor device structure as described in claim 8, further comprising: The gate electrode layer, a third source / drain region, a fourth source / drain region, and a fifth source / drain region are provided, wherein the second and fourth source / drain regions are disposed on opposite sides of the gate electrode layer, and the third and fifth source / drain regions are disposed on opposite sides of the gate electrode layer.

12. The semiconductor device structure as described in claim 11, further comprising: A second conductive component is electrically connected to the fourth and fifth source / drain regions.

13. A method for forming a semiconductor device structure, comprising: A first source / drain region is formed, comprising a first epitaxial layer and a second epitaxial layer, wherein the first and second epitaxial layers are doped with a dopant, the concentration of the dopant in the first epitaxial layer being different from the concentration of the dopant in the second epitaxial layer, and in a cross-sectional view, the thickness and width of the first source / drain region are different; a second source / drain region is formed adjacent to the first source / drain region; a contact etch stop layer is deposited over the first and second source / drain regions; a first interlayer dielectric layer is deposited over the contact etch stop layer; an etch stop layer is deposited over the first interlayer dielectric layer and the contact etch stop layer; a second interlayer dielectric layer is deposited over the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; The semiconductor device structure is flipped; and a first conductive component is formed on the first and second source / drain regions, wherein the first conductive component includes a first portion, a plurality of second portions extending from a plurality of edges of the first portion, and a third portion extending from a center of the first portion.

14. A method for forming a semiconductor device structure as described in claim 13, wherein forming the first conductive component comprises: Thin a substrate to expose an insulating material; A hard masking layer is deposited on the insulating material; And to form an opening in the hard shielding layer and the insulating material.

15. A method for forming a semiconductor device structure as described in claim 14, wherein forming the opening comprises: Remove a first substrate portion disposed on the first source / drain region and remove a second substrate portion located on the second source / drain region.

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