Non-line-of-sight junction formation

Abstract

This invention provides improved low thermal budget target region doping for semiconductor processing methods and semiconductor structures. The method includes providing a semiconductor structure having one or more undoped off-line target regions on a substrate within a semiconductor processing chamber, wherein one or more low thermal budget features are formed on the semiconductor structure. The method includes performing a pre-cleaning operation on the one or more undoped target regions to remove at least a portion of any oxides present on the one or more undoped target regions. The method includes epitaxially depositing a first junction layer on the substrate, the first junction layer having a first doping concentration of less than 1 x 10²⁰ dopant atoms / cm³. The method includes epitaxially depositing a second junction layer on the first junction layer, the second junction layer having a second doping concentration of more than 1 x 10¹⁹ dopant atoms / cm³.

Description

[Technical Field]

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 657,458, filed May 7, 2024, entitled “NON-LINE-OF-SIGHT JUNCTION FORMATION”, the entire contents of which are incorporated herein by reference.

[0002] This technology relates to deposition and removal processes and chambers. More specifically, this technology relates to systems and methods for forming interfaces in non-line-of-sight locations, including high aspect ratio structures. [Previous Technology]

[0003] The realization of integrated circuits relies on a process of creating complex patterned material layers on the surface of a substrate. Creating patterned materials on a substrate requires controlled material formation and removal methods. Material properties can affect how components operate and how films are removed. Deposition processes produce films with specific properties. Many formed films require additional processing to adjust or enhance their material properties to provide suitable performance.

[0004] Therefore, there is an urgent need for improved systems and methods for producing high-quality components and structures. This technology addresses these and other needs. [Summary of the Invention]

[0005] This technology generally relates to semiconductor processing methods and systems. The method includes providing a semiconductor structure having one or more undoped, out-of-line-of-sight target regions on a substrate within a semiconductor processing chamber, wherein one or more low thermal budget features are formed on the semiconductor structure. The method includes performing a pre-cleaning operation on the one or more undoped target regions to remove at least a portion of any oxides present on the one or more undoped target regions. The method includes epitaxially depositing a first junction layer over the substrate, the junction layer having a first dopant concentration of less than 1 x 10²⁰ dopant atoms / cm³. The method includes epitaxially depositing a second junction layer over the first junction layer, the junction layer having a second dopant concentration of greater than 1 x 10¹⁹ dopant atoms / cm³. The method includes maintaining a temperature within the semiconductor processing chamber at below or about 800°C.

[0006] In an embodiment, the temperature within the semiconductor processing chamber is maintained at or below 750°C. Furthermore, in an embodiment, the method further includes hydrogen baking of one or more target regions prior to epitaxial deposition of the first junction layer, wherein the hydrogen baking is performed at a temperature below or below 750°C. In a further embodiment, one or more target regions are disposed in recesses within the semiconductor structure. Additionally, or alternatively, in an embodiment, one or more target regions are disposed within features with a width of 10 nm or less. The embodiments include maintaining the semiconductor structure in an oxygen-free environment during a pre-cleaning operation, during epitaxial deposition of the first junction layer, during epitaxial deposition of the second junction layer, or a combination thereof. In more embodiments, the pre-cleaning operation is integrated into the semiconductor processing chamber. In an embodiment, the method further includes annealing the semiconductor structure after epitaxial deposition of the second junction layer, wherein the annealing is performed at a temperature below or below 1100°C. In embodiments, annealing is performed over a period of time and / or at a certain temperature to form a linear or logarithmic dopant gradient extending from the outer surface of the second junction layer to the substrate. Embodiments include one or more low thermal budget features comprising bit line contacts.

[0007] This technology is also generally directed to semiconductor processing systems. The system includes a first processing chamber, a second processing chamber, a third processing chamber, and a system controller. The system includes: the controller is configured to remove at least a portion of any oxide present on one or more undoped target regions of a semiconductor structure in the first processing chamber. The system includes: one or more undoped target regions comprising one or more non-line-of-sight target regions on a substrate of a semiconductor structure located within the semiconductor processing chamber, and forming one or more low thermal budget features on the semiconductor structure. The system includes: the controller is configured to epitaxially deposit a first junction layer having a first doping concentration of less than 1 x 10²⁰ dopant atoms / cm³ over a substrate in the second processing chamber, and to epitaxially deposit a second junction layer having a second doping concentration of more than 1 x 10¹⁹ dopant atoms / cm³ over the first junction layer in the third processing chamber.

[0008] In an embodiment, the semiconductor processing system includes clustering tools. Furthermore, in an embodiment, the semiconductor processing system maintains an oxygen-free environment during oxide removal, during epitaxial deposition of the first junction layer, during epitaxial deposition of the second junction layer, between oxide removal and epitaxial deposition of the first junction layer, between epitaxial deposition of the first junction layer and epitaxial deposition of the second junction layer, or combinations thereof. In further embodiments, the semiconductor processing system maintains a temperature below or about 750°C. In an embodiment, the controller is further configured to perform hydrogen baking on one or more target regions prior to epitaxial deposition of the first junction layer, wherein the hydrogen baking is performed at a temperature below or about 750°C. In further embodiments, the controller is further configured to anneal the semiconductor structure after epitaxial deposition of the second junction layer, wherein the annealing is performed at a temperature below or about 1100°C.

[0009] This technology is also generally directed to semiconductor processing systems. The system includes a system controller configured to remove at least a portion of any oxide present on one or more undoped target regions of a semiconductor structure, the one or more undoped target regions comprising one or more off-line target regions on a semiconductor structure substrate located within a semiconductor processing chamber, wherein one or more low thermal budget features are formed on the semiconductor structure. The system includes a system controller configured to epitaxially deposit a first junction layer over a substrate having a first doping concentration of less than 1 x 10²⁰ dopant atoms / cm³, and to epitaxially deposit a second junction layer over the first junction layer having a second doping concentration of more than 1 x 10¹⁹ dopant atoms / cm³. The system includes maintaining a temperature within the semiconductor processing chamber at less than or about 800°C.

[0010] In one embodiment, the semiconductor structure includes a 3D DRAM element. Furthermore, in another embodiment, the semiconductor structure includes a 4F2 element, wherein one or more undoped target regions are disposed within or adjacent to a feature with a width less than or about 10 nm. In more embodiments, the length of the one or more undoped target regions from the exposed surface to the inner end is greater than or about 40 nm.

[0011] This technology may offer many advantages over conventional processing methods. For example, the doping described herein can be used for doping in non-line-of-sight locations, including high aspect ratio junctions and groove structures. Furthermore, the doping processes and methods described herein can provide precisely tailored dopant levels, including higher doping levels achievable using solid-state doping in high aspect ratio or groove structures. The processes and methods described herein can also achieve such doping levels without requiring additional thermal budgets, thereby reducing process steps and preventing damage to high aspect ratio features. These and other embodiments, along with their many advantages and features, will be further described in detail below and in the accompanying drawings.

Implementation Method

[0019] As the DRAM industry shifts from planar 6F2 solutions to 4F2 vertical channel transistor solutions or 3D DRAM, the process requirements for complex transistor solutions continue to increase significantly. Evolving transistor solutions have developed devices with one or more recesses extending from the main channel, leading to evolution of features in non-line-of-sight areas and increasingly higher aspect ratios. For example, during 3D DRAM processing, silicon channels are formed when other materials, including silicon nitride and silicon oxide, form high aspect ratio features around the silicon substrate material. In subsequent processing, source and drain junction regions are formed by doping the substrate material at the distal ends of the high aspect ratio features. Subsequent processing may form contacts on the source and drain regions, for example, through siliconization processes.

[0020] Conventional doping of silicon-containing materials in high aspect ratio structures is typically accomplished through plasma implantation or solid-state doping processes, such as conformal deposition of doped films followed by driven annealing, and then removal of the doped film. Depending on the specific device design, silicon may be doped as p-type or n-type silicon. A portion of the dopant in the silicon doping or implantation may enter the underlying silicon-containing material, thereby doping the underlying silicon-containing material. However, with increasing device complexity and aspect ratio, coupled with the growing demand for high-quality structures, these conventional techniques may not provide sufficient doping depth, concentration, and / or gradient, especially at low temperatures, because conventional techniques rely on annealing processes to transfer the doping concentration to the underlying material.

[0021] Furthermore, conventional techniques deposit byproduct materials elsewhere in the structure, which can hinder subsequent processing, require intermediate processing to remove the byproduct materials, or reduce the functionality of the final device. Specifically, when using solid-phase doping, it can be difficult to remove some or all of the doped film after driven annealing, especially without damaging the underlying channels. In other words, removing the deposited material without removing the now-doped silicon has proven challenging. Therefore, current processes present problems, especially for thin channels, such as channels with widths less than 10 nm and other high aspect ratio channels, because these processes often result in channel damage, thereby reducing electrical properties.

[0022] Furthermore, existing plasma processes require a line of sight from the plasma source to the target doping region. This is problematic for structures with corners or ramps separating channels from central vias (e.g., recessed elements). For example, 3D DRAM structures have vertically extending vias and multiple horizontally recessed channels from the vertically extending vias. Therefore, existing plasma techniques cannot dope regions within horizontal channels due to the lack of a linear path to the plasma source. Attempts have been made to utilize vapor-phase doping to overcome the problems associated with solid-phase doping and / or plasma processes. However, vapor-phase doping requires sufficiently high temperatures to drive the dopant into the substrate material of the channel. This can be problematic because many structures may have a limited thermal budget when vapor-phase doping occurs or is desired. For example, in 3D DRAM structures, bitline contacts may have been formed before the junctions were formed. As is known in the art, such contacts may comprise one or more silicon compounds, which limits the subsequent thermal budget. In addition, or as an alternative, as is known in the art, subsequent high-temperature steps may also alter the already formed mating profile, causing discrepancies between the planned mating surfaces.

[0023] This technology has surprisingly discovered that, through precise control of integration, low-temperature doping processes can be provided at off-line locations. Furthermore, this technology has discovered that controlled dopant gradients can be provided even at low temperatures, enabling junctions to be formed in devices with low thermal budgets. Moreover, this technology has surprisingly discovered that, through precise control of junction doping as described herein, a complete doping gradient or spectrum can be provided for off-line locations of the target. That is, the processes and systems described herein also solve previous problems associated with unwanted residual doping, such as unwanted residual doping resulting from attempts to provide low-doping concentration materials on highly doped materials.

[0024] While the following disclosure will conventionally specify particular deposition and etching processes utilizing the disclosed techniques, it will be readily apparent that these systems and methods are equally applicable to other deposition and etching chambers, and processes that may occur within the described chambers. Therefore, the techniques should not be considered limited to these specific deposition processes or chambers. This disclosure will discuss systems and chambers that can be used to perform deposition processes according to embodiments of the present technology before describing additional details of embodiments according to the present technology.

[0025] FIG1 shows a top view of a multi-chamber processing system 100, which may be specifically configured to implement patterns or operations according to certain embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on a single substrate (such as any number of semiconductor substrates) for forming semiconductor devices. The multi-chamber processing system 100 may include a transfer chamber 106, a buffer chamber 108, single-wafer loading gates 110 and 112 (although dual loading gates may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. Single-wafer loading gates 110 and 112 may include a heating element 113 and may be connected to the buffer chamber 108. Processing chambers 114, 116, 118, and 120 may be connected to the transfer chamber 106. Processing chambers 122 and 124 may be connected to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be disposed between transfer chamber 106 and buffer chamber 108, facilitating transfer between robots 126 and 128. These platforms 102 and 104 may be open to both the transfer chamber and the buffer chamber, or selectively isolated or sealed from the chambers to maintain different operating pressures between the transfer chamber 106 and the buffer chamber 108. Each of the transfer platforms 102 and 104 may include one or more tools 105, for example, for orientation or measurement operations.

[0026] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to perform the operations described below. Therefore, the computer system 130 may be a controller or controller array, and / or a general-purpose computer configured with software stored on a non-transitory computer-readable medium, which, when executed, performs the operations described for the methods according to embodiments of the present technology. Each processing chamber 114, 116, 118, 120, 122, and 124 may be configured to perform one or more process steps in semiconductor structure fabrication. More specifically, processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a variety of substrate processing operations, including dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0027] To transport substrates between chambers, transfer chamber 106 and / or buffer chamber 108 may include robotic transport mechanisms 126, 128. These transport mechanisms 126, 128 may have a pair of substrate transport blades connected to the distal end of a telescopic arm, as well as other transport arms known in the art. These blades and / or arms can be used to transport individual substrates in and out of the processing chambers. In operation, one of the substrate transporters may remove substrate W from one of the loading gate chambers (e.g., loading gates 110, 112) and transport substrate W to a first stage of processing, such as the processing steps described below performed in one or more of the processing chambers 114, 116, 118, 120, 122, and 124. These chambers may be included to perform individual or combined operations of the techniques described above. For example, while one or more chambers may be configured to perform deposition or etching operations, one or more other chambers may be configured to perform pre-processing operations and / or one or more post-processing operations. This technology covers any number of configurations that may also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0028] If a chamber is occupied, the robot may wait until processing is complete, then remove the processed substrate from the chamber and may subsequently insert a new substrate using one or more second arms. Once the substrate has been processed, it can be moved to the second stage of processing. For each move, transport mechanisms 126, 128 typically have one blade transporting the substrate while the other blade is empty to perform substrate exchange. Transport mechanisms 126, 128 may wait in each chamber until an exchange can be completed. Once processing within the processing chamber is complete, transport mechanisms 126, 128 may move the substrate W from the last processing chamber to the second processing chamber and / or transport the substrate W to a cassette within loading gate chambers 110, 112.

[0029] Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more process steps in the fabrication of a semiconductor structure, and any number of processing chambers and combinations thereof may be used on the multi-chamber processing system 100. For example, any processing chamber may be configured to perform a variety of substrate processing operations, including any number of deposition processes, such as cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, including etching, pre-cleaning, pretreatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that may be performed in any chamber or any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. Any other processes may also be similarly performed in specific chambers incorporated into the multi-chamber processing system 100, including any of the processes described below, as will be readily understood by those skilled in the art.

[0030] FIG2 shows a schematic cross-sectional view of an exemplary processing chamber 200, which is suitable for patterning, depositing one or more material layers and / or providing one or more doped layers on a substrate 302 as described herein within the processing chamber 100. The processing chamber 200 can be used to process one or more substrates therein, including processes such as depositing material on the element side 250 of the substrate 202, heating the substrate 202, etching the substrate 202, or combinations thereof. The processing chamber 200 may include chamber walls 248 and an array of radiant heating lamps 204 for heating components such as the substrate 202 disposed within the processing chamber 200, including a substrate support 206 and / or the substrate 202 thereon. As shown in FIG2, the array of radiant heating lamps 204 may be disposed below the substrate support 206 (i.e., facing the non-element side). As shown in FIG2, the array of radiant heating lamps 204 may be disposed below and / or above the substrate support 206. The substrate support 206 may be a disc-shaped substrate support as shown in the figure, or it may include an annular substrate support (not shown) that supports the substrate 202 from the edge of the substrate so that the back side of the substrate 202 is directly exposed to the heat from the radiant heating lamp 204. In an embodiment, the substrate support 206 may be made of silicon carbide or graphite coated with silicon carbide to absorb the radiant energy from the lamp 204 and conduct the radiant energy to the substrate 202, thereby heating the substrate 202.

[0031] The substrate support 206 may be located between the first energy transfer member 208 (which may be a dome) and the second energy transfer member 210 (which may also be a dome or a dome alone) in the processing chamber 200. The first energy transfer member 208 and the second energy transfer member 210, and the body 212 which may be disposed between the first energy transfer member 208 and the second energy transfer member 210, may generally define the internal region 211 of the processing chamber 200. The first energy transfer member 208 and / or the second energy transfer member 210 may be convex and / or concave. In an embodiment, the first energy transfer member 208 and / or the second energy transfer member 210 may be optically transparent to high-energy radiation (transmitting at least 95% of the high-energy radiation). In one embodiment, the first energy transfer member 208 and the second energy transfer member 210 are made of quartz. In one embodiment, an array of radiant heating lamps 204 may be disposed on the first energy transfer member 208, for example, in the region 239 defined between the first energy transfer member 208 and the reflector 254 (discussed in detail later). In another embodiment, the array of radiant heating lamps 204 may be disposed adjacent to and below the second energy transfer member 210. The radiant heating lamps 204 can be independently controlled in different regions to control the temperature of each region of the substrate 202 when processing gases or vapors pass over the surface of the substrate 202, thereby promoting the deposition or doping of materials on the element side 250 of the substrate 202. In embodiments, the deposited material may include elemental semiconductor materials such as silicon, doped silicon, germanium, and doped germanium; semiconductor alloys such as silicon-germanium and doped silicon-germanium; and compound semiconductor materials, including III-V materials, examples of which include nitrides, phosphides, and arsenides of aluminum, gallium, indium, and thallium, and mixtures thereof; and II-VI materials, examples of which include sulfides, selenides, and tellurides of zinc, cadmium, and mixtures thereof.

[0032] The radiant heating lamp 204 can provide a total lamp power between about 10 kW and about 60 kW and is configured to heat the substrate 202, for example, to a temperature in the range of about 200°C to about 1600°C, and / or according to any one or more process condition temperatures discussed in detail below. Each lamp 204 can be coupled to a power distribution board such as a printed circuit board (PCB) 252, thereby supplying power to each lamp 204. In one embodiment, the radiant heating lamp 204 is positioned within a housing 245 configured to be cooled during or after processing, for example, using cooling fluid introduced into channels 249 located between the radiant heating lamps 204. However, in the embodiments, it should be understood that other heating methods and devices can be used alone or in combination with the heating lamp 204. For example, in the embodiments, a heated or cooled substrate support 206 is used.

[0033] The substrate 202 is transferred to the processing chamber 200 and positioned on the substrate support 206 through the loading port formed in the main body 212 (see detailed discussion in FIG1). The main body 212 is provided with a processing gas inlet 214 and a gas outlet 216.

[0034] In an embodiment, the substrate support 206 may include a shaft or rod 218 coupled to the motion assembly 220. The motion assembly 220 may include one or more actuators and / or adjustment devices that provide positional movement and / or adjustment of the rod 218 and / or the substrate support 206 within the interior region 211. For example, the motion assembly 220 may include a rotary actuator 222, which, as an example, rotates the rod 218, thereby causing the substrate support 206 to rotate about a longitudinal axis A of the processing chamber 200, which is perpendicular to the XY plane of the processing chamber 200. The motion assembly 220 may also include a vertical actuator 224 to move the rod 218 within the processing chamber 200 in the Z direction (e.g., vertical direction), thereby moving the substrate support 206 in the Z direction. In an embodiment, the motion assembly 220 may optionally include a tilt adjustment device 226 for adjusting the planar orientation of the substrate support 206 in the interior region 211. The motion assembly 220 may also optionally include a lateral adjustment device 228 for positioning the adjustment rod 218 and / or the substrate support 206 in the xy plane within the internal region 211 of the processing chamber 200. In an embodiment, the motion assembly 220 may include a pivot mechanism 230.

[0035] The substrate support 206 is illustrated in a raised processing position, but can be vertically raised and lowered by the motion assembly 220 as described above. For example, the substrate support 206 can be lowered to a transfer position (below the processing position) so that the lifting pin 232 contacts the support 234 on or above the second energy transfer member 210. These supports provide one or more surfaces parallel to the XY plane of the processing chamber 200 and help prevent the lifting pin 232 from becoming stuck, as this could occur if its end contacts the curved surface of the second energy transfer member 210. The support 234 is made of an optically transparent material, such as quartz, in the embodiment to allow energy from the lamp 204 to pass through it. The lifting pin 232 may be suspended in a hole 207 in the substrate support 206, and as the substrate support 206 is lowered, the bottom of the lifting pin 232 engages with the support 234. Therefore, in this embodiment, further descent of the substrate support 206 may cause the lifting pin 232 to engage the substrate 202 and hold it in a stationary state as the substrate support 206 is further lowered, thereby supporting the substrate in a position away from the substrate support 206 for transfer from the processing chamber 200. A robot (discussed in more detail in FIG1) then enters the processing chamber 200 to engage at least the lower side of the substrate 202 and remove it through a loading port. The robot can then load a new substrate 202 onto the lifting pin 232, and the substrate support 206 can be driven to a processing position, placing the substrate 202 in the processing position with its element side 250 facing upwards. In the processing position, the lifting pin 232 may include an enlarged head, allowing the lifting pin 232 to suspend in an opening in the substrate support 206. When the substrate support 206 is in the processing position, it may divide the internal volume of the processing chamber 200 into a processing area 236 above the substrate support 206 and a purification area 238 below the substrate support 206. During processing, the substrate support 206 may be rotated, for example, by a rotary actuator 222, to minimize spatial anomalous effects of heat and processing gas flow within the processing chamber 200, thereby promoting uniform processing of the substrate 202. In embodiments, the rotational speed of the substrate support 206 is between about 5 RPM and about 100 RPM, for example, between about 10 RPM and about 50 RPM, for example, from about 15 RPM to about 45 RPM.

[0036] The temperature of the substrate can be measured by sensors configured to measure temperature at one or more locations on the substrate or at the bottom of the substrate support 206. These sensors may be pyrometers (not shown) disposed in ports formed in the housing 245. Alternatively, one or more sensors 253, such as pyrometers, may be used to measure the temperature of the element side 250 of the substrate 202. For example, a reflector 254 may be selectively placed outside the first energy transfer member 208 to reflect infrared light emitted from the substrate 202 and redirect energy back to the substrate 202. The reflector 254 may be secured to the first energy transfer member 208 using a clamp 256. The reflector 254 may be made of aluminum, stainless steel, or other materials known in the art. Sensors 253 may be mounted through the reflector 254 to receive radiation from the element side 250 of the substrate 202.

[0037] Processing gas supplied by processing gas supply source 251 can be introduced into processing region 236 through processing gas inlet 214 formed in the sidewall of body 212. Processing gas inlet 214 can guide processing gas in a generally radial inward direction (e.g., toward axis A of processing chamber 200). Therefore, in an embodiment, processing gas inlet 214 can be a side gas injector. The side gas injector can be positioned to guide processing gas to the entire surface of substrate support 206 and / or substrate 202. In a film formation process for forming a film layer on substrate 202, substrate support 206 can be located in a processing position, with substrate 202 disposed in processing region 236, thereby allowing processing gas to flow generally along flow path 273 across the entire upper surface of substrate support 206 and / or substrate 202. Processing gas can be discharged from processing region 236 (e.g., along flow path 275) through gas outlet 216 located on the opposite side of processing gas inlet 214 in processing chamber 200. The removal of process gas through gas outlet 216 is facilitated by the vacuum pump 257 fluidly coupled to the internal region 211 and the system foreline (not shown).

[0038] Purified gas supplied from the purified gas source 262 can be introduced into the purified area 238 through a purified gas inlet 264 formed on the side wall of the main body 212. The purified gas inlet 264 can be positioned at a height lower than the processing gas inlet 214. The purified gas inlet 264 can be configured to guide the purified gas in a generally radially inward direction. The purified gas inlet 264 can be configured to guide the purified gas upward. During the film formation process, the substrate support 206 can be positioned such that the purified gas flows generally along the flow path 265 across the back side of the substrate support 206. The purified gas can be discharged from the purified area 238 (e.g., along the flow path 266) and can be discharged from the processing chamber 200 via a gas outlet 216 located on the opposite side of the purified gas inlet 264.

[0039] The processing chamber 200 may further include a point heating module 271. The point heating module 271 may include one or more point heaters 270, which can individually heat one or more locations on the substrate 202 during processing. For example, in an embodiment, a cold spot may be formed at the location on the substrate 202 that contacts the lifting pin 232.

[0040] The processing chamber 200 described above can be controlled by a processor-based system controller, such as the controller 247 shown in FIG. 2. For example, the controller 247 can be configured to control the flow rates of various precursors, processing gases, and purification gases from a gas source in different substrate processing sequence operations. Further, for example, the controller 247 can be configured to control the activation of the point heating module 271, predict the activation algorithm of the point heating module 271, and / or encode or synchronize the operation of the point heating module 271 with substrate rotation, gas supply, lamp operation, or other processing parameters, as well as other controller operations. The controller 247 includes a programmable central processing unit (CPU) 252, which can operate together with memory 255 and large storage devices, input control units, and display units (not shown) (e.g., clock, cache, input / output (I / O) circuitry, etc.) and is coupled to various components of the processing chamber 200 to facilitate substrate processing control within the processing chamber 200. The controller 247 may also include support circuitry 258. To facilitate control of the aforementioned processing chamber 200, the CPU 252 can be any type of general-purpose computer processor, suitable for use in industrial environments, such as a programmable logic controller (PLC), for controlling the individual chambers and subprocessors. The memory 255 may be in the form of a computer-readable storage medium containing instructions that, when executed by the CPU 252, facilitate the operation of the processing chamber 200. The instructions in the memory 255 may be in the form of a program product, such as a program implementing the method disclosed herein.

[0041] As described above, this technology can utilize one or more selective epitaxial growth processes to form doped target regions (which may be a silicon-containing material in embodiments). Referring to Figure 3, this figure illustrates an example operation of a method 300 for forming a semiconductor structure according to an embodiment of this technology. Method 300 may include one or more operations prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to said operations. For example, the method may begin after multiple layers have been deposited, for example, to produce a 3D DRAM structure. However, as described above, it will be understood that the figures only illustrate one exemplary process that may employ a process according to an embodiment of this technology, and this description is not intended to limit the technology to this process or structure. Some or all of the operations may be performed in a chamber or system tool as previously described, or may be performed in different chambers of the same system tool, which may include chambers where the operations of method 300 may be performed.

[0042] Method 300 may include several optional operations as shown in the figures, which may be specifically related or not specifically related to certain embodiments of the present technology. For example, many operations are described as providing a broader scope of structure formation but are not critical to the technology or may be performed by alternative methods that will be discussed further below. Method 300 describes operations schematically shown in Figures 4A and 4B, and the illustrations of these operations will be described together with the operations of Method 300. It should be understood that Figures 4A and 4B show only partial schematics, and the substrate may contain any number of structural portions having the patterns shown in the figures, as well as other structural patterns that may still benefit from the operations of the present technology.

[0043] Method 300 may or may not involve selective operations such as developing a semiconductor structure for a specific manufacturing operation. It should be understood that method 300 can be performed on any number of semiconductor structures 400, as shown in FIG. 4A, including example structures on which one or more doped regions are desired to be formed. Doped regions are shown herein as doped junctions. However, it should be understood that the methods and systems discussed herein are equally suitable for doping other desired regions, such as any one or more non-line-of-sight locations mentioned herein. Nevertheless, as shown in FIG. 4A, the semiconductor structure 400 can allow a multilayer material to be deposited over a substrate. The semiconductor structure 400 can be formed of any number of materials, such as silicon or silicon-containing materials, germanium, other substrate materials, and a substrate wafer or substrate made of one or more materials that may be formed over the substrate during semiconductor processing.

[0044] The semiconductor structure 400 may be shown as a partial view of alternating layers of materials stacked together. In embodiments, these materials may be used for the formation of 3D DRAM memory or for the orientation of vertical extensions, such as for the formation of 4F2 memory. As shown in FIG4A, the semiconductor structure 400 may include one or more channels 402 extending between adjacent word lines 414. In embodiments, the one or more channels may be formed of one or more materials, including substrate materials or substrate material layers, such as silicon, polycrystalline silicon, amorphous silicon, doped silicon, strained silicon, carbon-doped silicon dioxide, SiGe, germanium, gallium arsenide, gallium nitride, indium phosphide, carbon nanotubes, and other materials such as group III-IV materials, 2D TMD metals, metal oxides, metal nitrides, metal alloys and other conductive materials and combinations thereof, as well as other channel materials known in the art. Since the embodiment shown in FIG4A is a 3D DRAM structure, the one or more channels 402 may extend along a generally horizontal direction and be substantially perpendicular to the access via or hole 406 and / or bit line 410, or the planned location of the access via or hole 406 and / or planned bit line 410. For example, in an embodiment, the one or more channels 402 may differ from the direction perpendicular to the memory via 406 and / or substrate 405 by about 10°, such as less than or about 7.5°, less than or about 5°, less than or about 2.5°, less than or about 1°, or any range or value between these values. However, as described above, in an embodiment, the bit line 410 may be formed after depositing one or more interface layers, as described herein. In an embodiment, the one or more channels 402 may be perpendicular to each other with respect to the memory via 406.

[0045] However, while non-line-of-sight structures, such as junctions and high aspect ratio features, have been discussed to date, it should be understood that the methods and systems described herein can also be used to form any semiconductor structure with access vias (e.g., contact vias). Therefore, this technique can be used to replace conventional epitaxial doping or implantation doping processes to dope a target material (e.g., silicon-containing material) exposed at the bottom of the corresponding via. For example, the methods and systems described herein may also be applicable to junction doping of one or more bit-line contacts or storage node contacts in current 6F2 DRAM, or even junction doping of logic FinFETs or nanosheet transistors.

[0046] In an embodiment, the length of one or more channels 402 is greater than or about 300 nm, for example greater than or about 400 nm, greater than or about 500 nm, greater than or about 600 nm, greater than or about 700 nm, or more, or any range or value therein. The width or critical dimension of one or more channels is greater than or about 5 nm, for example greater than or about 25 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, or greater, or for example less than or about 50 nm, for example less than or about 40 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm, less than or about 5 nm, or any range or value therein. Therefore, in the embodiments, the channel and / or adjacent features may be considered to have a high aspect ratio, such as an aspect ratio greater than or about 50, greater than or about 60, greater than or about 70, greater than or about 80, greater than or about 90, greater than or about 100, greater than or about 110, greater than or about 120, greater than or about 130, greater than or about 140, greater than or about 150, or any range or value between therewith.

[0047] However, as described above, in embodiments, one or more channels may not have a high aspect ratio or a large height. Instead, the target area may be located in a recess 404 as shown in FIG. 4A. For example, as shown, this recess 404 may obstruct the view of the process gas or plasma source, such as through the memory hole 406. In embodiments, adjacent caps 416 may form all or part of the recess between adjacent channels 402, but the recess can be formed by any structure or feature known in the art. Nevertheless, in embodiments, the one or more channels 402 may have any of the height, width, or aspect ratio discussed above and be disposed in the recess 404.

[0048] The semiconductor structure 400 may further include a bit line interface 408 adjacent to the bit line 410 and a storage node interface 412 adjacent to the word line 414, as shown in FIG4A. The bit line 410 may extend along a first direction, which is generally a vertical direction, and one or more word lines may extend in a second direction, which in some embodiments may be orthogonal to the bit line 410. Nevertheless, as described above, the one or more channels 402 may extend along a direction that is generally orthogonal to the first direction, the second direction, or both directions (e.g., within about 10° of the orthogonal direction, such as less than or about 7.5°, less than or about 5°, less than or about 2.5°, less than or about 1°, or any range or value in between). However, it should be clear that FIG4A to FIG4B are exemplary structures, and therefore the entire structure can be rotated such that the bit line 410 extends along a generally horizontal orientation.

[0049] Nevertheless, as shown in FIG4A, the bit line junction 408 may have undergone junction doping to form the bit line junction 408, for example, through the processes discussed herein, through vapor phase doping, or through other processes known in the art. However, in the embodiment, the bit line 410 may not have been formed, while both the bit line junction 408 and the storage node junction 412 may be formed according to method 300. Nevertheless, as shown, the storage node junction 412 may not have undergone junction doping.

[0050] Therefore, in embodiments, the method according to the present technology may include providing a semiconductor structure 400 to a processing region of a processing chamber in operation 305. The semiconductor structure 400 has one or more undoped target regions, such as one or more junctions, such as storage node junctions 412, and / or one or more other undoped target regions, the processing chamber being, for example, one or more processing chambers discussed above. However, as discussed above, in embodiments, the semiconductor structure 400 may have one or more other regions that need to be doped, such as regions blocked from plasma sources, such as regions disposed within recesses 404 as shown in FIG. 4A, or regions disposed in narrow and / or high aspect ratio features. Nevertheless, in embodiments, the methods and systems according to this technology may include forming and / or providing one or more junctions (e.g., within line of sight or outside of high aspect ratio features) on an accessible portion of a semiconductor structure, such as bitline junction 408, which may include silicide as shown in FIG. 4A, or forming and / or providing one or more features that reduce the thermal budget of the semiconductor structure, for example, reducing the thermal budget to below or about 800°C, below or about 775°C, below or about 7 50°C, below or about 725°C, below or about 700°C, below or about 675°C, below or about 650°C, below or about 625°C, below or about 600°C, below or about 575°C, below or about 550°C, below or about 525°C, below or about 500°C, below or about 475°C, below or about 450°C, below or about 425°C, or even down to about 400°C or lower, or between any of the above ranges or values.

[0051] However, in embodiments, the semiconductor structure may undergo one or more pretreatment and / or pre-cleaning operations prior to the selective epitaxial process to remove some or all of the oxides and / or carbon present on the surface of the target doped regions, as oxides (including native oxides) may interfere with the selective epitaxial process described herein. In embodiments, the pre-cleaning and / or pretreatment operations may include wet or dry cleaning processes and may be integrated pre-cleaning within a processing chamber. Alternatively, the semiconductor structure may be transferred to a pre-cleaning chamber. However, in such embodiments, the transfer may be performed without an air barrier, such as in an oxygen-free environment. Therefore, in embodiments, regardless of whether the pre-cleaning operation is integrated within a chamber or located in a separate chamber, the semiconductor structure should not be significantly exposed to air or other oxygen sources, or to reduced oxygen levels or air, after the start of the pre-cleaning operation 310, to avoid the formation or reformation of continuous or discontinuous native oxide layers. While any cleaning operation suitable for removing surface oxides and / or surface carbon can be used, in this embodiment, pre-cleaning, such as Siconi™ cleaning or plasma etching cleaning, can be used to remove any surface oxides present.

[0052] In an embodiment, an optional hydrogen baking operation may be used in operation 315. In an embodiment, this hydrogen baking operation may not be necessary if sufficient pre-cleaning is achieved in operation 310 and no air isolation occurs. Nevertheless, in an embodiment, it may be desirable to further ensure that there are virtually no or no surface oxides in the target doped regions. Therefore, in an optional embodiment, the semiconductor structure 400 may undergo hydrogen baking. Hydrogen baking may involve removing contaminants and defects from the surface of the semiconductor structure by combining a high-temperature flowing hydrogen gas at or above 600°C, above or about 700°C, above or about 750°C, such as above or about 800°C, above or about 850°C, above or about 900°C, above or about 950°C, above or about 1000°C, above or about 1050°C, or any range or value between these temperatures. However, in an embodiment, the hydrogen baking operation may be performed after the formation of the first junction and / or one or more features that reduce the thermal budget of the semiconductor structure. Therefore, in the embodiments, hydrogen baking may be limited by the thermal budget of the semiconductor structure and may therefore be carried out at temperatures below or about 800°C, such as below or about 775°C, below or about 750°C, below or about 725°C, below or about 700°C, or any range or value in between.

[0053] Regardless of whether the optional baking operation 315 is used, the target area (e.g., the storage node interface or area 412 in the illustrated embodiment) may contain less than or about 5% by weight of total oxides, including natural oxides, such as less than or about 4% by weight, less than or about 3% by weight, less than or about 2% by weight, less than or about 1% by weight, less than or about 0.5% by weight, or less than or about 0.1% by weight, or generally contains no oxides.

[0054] However, after the pre-cleaning operation 310 and the optional baking operation 315, a first epitaxial layer with one or more first doping concentrations is deposited on the substrate. Specifically, in embodiments, it may be desirable to form a first doped layer on the substrate having a low doping concentration, including doping concentrations as low as or about 1 x 10¹⁷ cm⁻³ (number of dopant atoms per cubic centimeter of deposited material), to improve junction functionality. However, the present invention has surprisingly found that a single chamber cannot apply such a gradient. Instead, the present invention has found that chambers used to apply high doping concentrations (e.g., chambers with concentrations greater than 1 x 10¹⁹ cm⁻³) can still provide unexpectedly high doping concentrations in low-doped epitaxial materials, even after cleaning or otherwise washing between operations. Therefore, this technology has found that the first epitaxial layer 420 formed on the channel / substrate 402 can be formed in a first selective epitaxial deposition chamber, wherein the first selective epitaxial deposition chamber is used to deposit one or more junction layers having a maximum doping concentration of 1x1020 cm-3 or, in some embodiments, 1x1019 cm-3.

[0055] Therefore, in an embodiment, operation 320 may deposit a first junction layer 420 having a low doping concentration on a channel 402 formed of one or more substrate materials. In an embodiment, the first junction layer 420 may have a doping concentration in the deposited layer that is greater than or equal to about 5 x 10¹⁶ cm⁻³, for example, greater than or equal to about 6 x 10¹⁶ cm⁻³, for example, greater than or equal to about 7 x 10¹⁶ cm⁻³, for example, greater than or equal to about 8 x 10¹⁶ cm⁻³, for example, greater than or equal to about 9 x 10¹⁶ cm⁻³, for example, greater than or equal to about 1 x 10¹⁷ cm⁻³, for example, greater than or equal to about 2 x 10¹⁷ cm⁻³, for example, greater than or equal to about 4 x 10¹⁷ cm⁻³, for example, greater than or equal to about 6 x 10¹⁷ cm⁻³, for example, greater than or equal to about 8 x 10¹⁷ cm⁻³, for example, greater than or equal to about 5 x 10¹⁶ ...5 x 10¹⁶ cm⁻³, for example, greater than or equal to about 6 x 10¹ Approximately 1 x 10¹⁸ cm⁻³, for example, greater than or approximately 2 x 10¹⁸ cm⁻³, for example, greater than or approximately 4 x 10¹⁸ cm⁻³, for example, greater than or approximately 6 x 10¹⁸ cm⁻³, for example, greater than or approximately 8 x 10¹⁸ cm⁻³, for example, greater than or approximately 1 x 10¹⁹ cm⁻³, greater than or approximately 5 x 10¹⁹ cm⁻³, up to approximately 1 x 10²⁰ cm⁻³, or for example, less than or approximately 1 x 10²⁰ cm⁻³, less than or approximately 5 x 10¹⁹ cm⁻³, less than or approximately 1 x 10¹⁹ cm⁻³, for example, less than or approximately 5 x 10¹⁸ cm⁻³, or any range or value in between.

[0056] As known in the art, typical selective epitaxial processes involve deposition and etching reactions. The deposition reaction includes depositing an epitaxial layer on a single-crystal surface of a substrate, such as one or more substrate materials discussed herein, and forming polycrystalline and / or amorphous layers on a non-single-crystal surface, such as a patterned dielectric layer or cap layer deposited over the substrate. Subsequent etching operations selectively remove the epitaxial layer and the polycrystalline and / or amorphous layer at different rates, thereby providing a net selective process that can result in limited or no deposition of epitaxial material and polycrystalline and / or amorphous material. However, at low temperatures, typical etching gases may not provide adequate selectivity between the epitaxial layer and the polycrystalline and / or amorphous layer.

[0057] As described above, in the embodiments, the current technology performs epitaxial growth processes of operations 320 and / or 325 at low temperatures to maintain the thermal budget of the semiconductor structure at, for example, the following temperatures: below or about 800°C, below or about 750°C, below or about 725°C, below or about 700°C, below or about 675°C, below or about 650°C, below or about 625°C, below or about 600°C, below or about 575°C, below or about 550°C, below or about 525°C, below or about 500°C. Below or about 475°C, below or about 450°C, below or about 425°C, or for example, above or about 400°C, above or about 425°C, above or about 450°C, above or about 475°C, above or about 500°C, above or about 525°C, above or about 550°C, above or about 575°C, above or about 600°C, above or about 625°C, above or about 650°C, above or about 675°C, above or about 700°C, above or about 725°C, or any range or value between these values.

[0058] Therefore, to overcome the problems associated with selectivity at low temperatures, the epitaxial growth process of operations 320 and / or 325 includes the inflow of higher-order silanes and / or higher-order chlorosilanes, along with dopants, into a processing region of the processing chamber to form a doped junction layer 420, and undesirable growth (amorphous silicon) that may occur in regions not corresponding to the channel / substrate 402. However, as will be discussed in more detail below, in embodiments, other epitaxial growth materials may be used in conjunction with the capping process, and thus other silanes may be used when forming junction layers 418 and / or 420. During the epitaxial growth process of operations 320 and / or 325, positioning the substrate in the processing region of the processing chamber may include adjusting one or more reactor conditions, such as temperature, pressure, and / or the flow rate of a carrier gas (e.g., Ar, N2, H2, or He), to conditions suitable for epitaxial film formation. Epitaxial deposition processes operating at 320 and / or 325 can be performed in a processing chamber located on a cluster tool (e.g., any of the processing chambers discussed above).

[0059] The pressure within the processing chamber can be adjusted such that the pressure in the reaction zone is in the range of about 1 to about 760 Torr, or in the range of about 1 Torr to about 600 Torr, or in the range of about 10 Torr to about 300 Torr, or in the range of about 10 Torr to about 100 Torr. In embodiments, a carrier gas (e.g., nitrogen) can flow into the processing chamber at a flow rate of about 1 to 40 SLM (standard liters per minute). Nitrogen remains inert during the cryogenic deposition process. Therefore, nitrogen is not incorporated into the deposited layer during the cryogenic epitaxial growth process. Furthermore, the nitrogen carrier gas does not form a hydrogen-terminated surface as a hydrogen carrier gas. However, in embodiments, different carrier / diluent gases, such as inert carrier gases like argon or helium, can be used, different flow rates can be used, or the gas(s) can be omitted.

[0060] In embodiments, the epitaxial growth process discussed herein may include introducing a deposition gas and a dopant precursor gas into a processing region of a processing chamber. The deposition gas includes higher-order silane precursor gases and / or chlorosilane precursor gases, and the dopant precursor gases include dopant (e.g., n-type or p-type dopant) precursor gases. Higher-order silanes include silanes with the chemical formula SixH(2x+2), where x is 2 or more, for example, where x is 2, 3, 4, 5, 6, 7, 8 or more. Examples of higher-order silanes include bis(Si2H6), tri(Si3H8), and tetra(Si4H10), or other higher-order silanes. chlorosilanes include those with the chemical formula ClySixH(2x+2-y), where y is 1 or more, 2 or more, 3 or more, or 5 or more, and x is 1 or more, 2 or more, or 3 or more. In one example, y ranges from 5 to 8, and x ranges from 2 to 3. In embodiments, the second chlorosilane precursor gas includes chlorosilane (ClSiH3), dichlorosilane (Cl2SiH2), trichlorosilane (Cl3SiH), hexachlorobissilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorobissilane (Cl5Si2H), octachlorotrisilane (Cl8Si3), or combinations thereof. However, other silanes may also be used herein. In one instance, the deposited gas is introduced into the treatment zone at a flow rate ranging from about 1 sccm to about 500 sccm, or from about 10 sccm to about 400 sccm, or from about 50 sccm to about 300 sccm, or from about 100 sccm to about 200 sccm.

[0061] In embodiments, the epitaxial growth process discussed herein may include introducing a dopant precursor (e.g., an n-type or p-type dopant precursor) into the processing region. In embodiments, dopant precursors such as n-type dopant precursors include phosphorus-containing precursors, antimony precursors, arsenic-containing precursors, or combinations thereof. In embodiments, antimony-containing precursors include one or a combination of antimony hydride, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenyl antimony, antimony trihydride, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony, or combinations thereof. In embodiments, phosphorus-containing precursors include one or a combination of phosphine and alkylphosphine. Suitable alkylphosphines include trimethylphosphine ((CH3)3P), dimethylphosphine ((CH3)2PH), triethylphosphine ((CH3CH2)3P), tert-butylphosphine, and diethylphosphine ((CH3CH2)2PH), and combinations thereof. In the examples, phosphines are used. In the examples, the arsenic-containing precursor includes one or a combination of the following: arsine (AsH3), arsenic halo compounds, trimethylarsenic, and silane [(H3Si)3-xAsRx], where x = 0, 1, 2, and Rx is hydrogen or deuterium. The flow rate of the n-type dopant precursor gas may be in the range of about 0.1 sccm to 10000 sccm, or in the range of about 100 sccm to about 5000 sccm, or in the range of about 500 to about 3000 sccm.

[0062] In an embodiment, the epitaxial layer may be a silicon-germanium (SiGe) layer, and the deposition gas further comprises a germanium source. Suitable germanium sources include germananes (GeH4) and higher-order germananes. Higher-order germananes include compounds with the empirical formula GexH(2x+2), where x is 2 or more, for example, x is 2, 3, 4 or greater. Examples of higher-order germananes include digerane (Ge2H6), trigerane (Ge3H8), and tetragerane (Ge4H10), as well as others and combinations thereof.

[0063] It is envisioned that the deposition precursor gas and the dopant precursor gas can be introduced simultaneously, substantially simultaneously, or in any particular order. In at least one embodiment, the deposition precursor gas and the dopant precursor gas flow into the processing region simultaneously and co-currently. In an embodiment, at least two precursor gases are mixed before being conveyed to the processing region. In an embodiment, at least two precursor gases are conveyed to the processing region separately and mixed within the processing region.

[0064] Nevertheless, in embodiments, an undoped or lightly doped crystalline silicon capping layer is applied on the first junction layer. The term "undoped" includes embodiments where the undoped crystalline silicon capping layer and the undoped amorphous silicon layer are accidentally doped or doped at very low concentrations, resulting in the undoped crystalline silicon capping layer and the undoped amorphous silicon layer lacking sufficient charge carriers (electrons or holes) to be conductive under a typical electric field. The undoped crystalline silicon capping layer protects the underlying doped junction layer during subsequent selective etching processes to remove the doped and undoped amorphous layers.

[0065] An undoped crystalline silicon capping layer is grown on or directly on the upper surface of the first junction layer (e.g., a low-doping junction layer), while an undoped amorphous silicon layer is formed on material accidentally deposited on feature sidewalls or other non-substrate surfaces during the first epitaxial deposition process. The epitaxial growth process forming the capping layer can use the methods and materials discussed above for the first junction layer, but may contain very little or no dopants. In embodiments, the undoped crystalline silicon capping layer can be grown to a thickness such that at least a portion of the undoped crystalline silicon capping layer remains on the first junction layer during etching.

[0066] For example, in an embodiment, the doped amorphous silicon layer and the undoped amorphous silicon layer are selectively removed relative to the undoped crystalline silicon capping layer, which may be only partially removed. That is, the etching process can be adjusted to be selective for the amorphous material of the undoped amorphous silicon layer and the doped amorphous silicon layer 342 (such as doped and undoped amorphous silicon), and to perform little or no etching on the undoped crystalline silicon capping layer and the first junction layer. Thus, the undoped amorphous silicon layer and the doped amorphous silicon layer are removed, while the first junction layer remains protected by at least a portion of the undoped crystalline silicon capping layer. Thus, even if selectivity decreases at low temperatures, the first junction layer can be protected during selective etching. The etching process may include dry etching, wet etching, reactive ion etching, or other suitable etching methods. In this embodiment, the etching process is a self-aligned process, meaning that no etching mask is required. Instead, the etching process relies on the etch selectivity of the doped amorphous silicon layer and the undoped amorphous silicon layer material relative to the undoped crystalline silicon capping layer.

[0067] During the etching process, an etching gas is introduced into the processing area to selectively remove the amorphous silicon layer relative to the crystalline silicon layer. In embodiments, the etching gas is selected from chlorine, germanium, germanium chloride, or combinations thereof. In embodiments, the etching gas is selected from Cl2, GeCl2, GeCl4, GeH4, or combinations thereof. In embodiments, the etching gas is free of hydrogen chloride (HCl). In this disclosure, the etching gas free of hydrogen chloride (HCl) includes embodiments where the etching gas unintentionally contains HCl or otherwise contains a very low concentration of HCl, such that the HCl gas does not perform etching under typical etching conditions. The etching gas may be introduced into the processing area at a flow rate ranging from about 1 sccm to about 1000 sccm, or from about 1 sccm to about 200 sccm, or from about 1 sccm to about 100 sccm.

[0068] In an embodiment, the doped amorphous silicon layer and the undoped amorphous silicon layer have etch selectivity relative to the undoped crystalline silicon capping layer 350 (i.e., the etch rate of the amorphous silicon material is higher than that of the crystalline silicon material). In an embodiment, the etch selectivity (i.e., the ratio of the etch rate of the amorphous silicon material to the etch rate of the crystalline silicon material) is in the range of about 100:1 to about 3000:1, 300:1 to about 3000:1, or in the range of about 300:1 to about 2000:1, or in the range of about 300:1 to about 1500:1.

[0069] Nevertheless, the capping layer can then be removed to expose the first junction layer. The etching process may be selective for the undoped crystalline silicon capping layer and may not etch the substrate and / or the first junction layer, or may etch only minimally. The etching process may include dry etching, wet etching, reactive ion etching, and other suitable etching methods. However, it should be understood that other selective low-temperature epitaxial methods are also envisioned herein.

[0070] After removing the capping layer, or otherwise exposing the top surface of the first junction layer 420 (e.g., without etching), the second junction layer 418 is formed in operation 325. However, as described above, in this embodiment, operation 325 is performed in a second epitaxial growth chamber, such as the further processing chamber discussed above. In this way, the second junction layer can be formed with a different doping concentration than the first junction layer without increasing the target doping concentration of the first junction layer (e.g., automatically increasing the doping concentration due to the aforementioned residual dopant). In this embodiment, further cleaning operations may be used to ensure that no oxide forms between the first and second junction layers. However, in this embodiment, no further cleaning operations are required.

[0071] In an embodiment, operation 325 can therefore deposit a second junction layer 418 with a high doping concentration on the first junction layer 420. In an embodiment, the second junction layer 418 may have a doping concentration in the deposited layer greater than or about 1 x 10¹⁹ cm⁻³, for example greater than or about 2 x 10¹⁹ cm⁻³, for example greater than or about 3 x 10¹⁹ cm⁻³, for example greater than or about 4 x 10¹⁹ cm⁻³, for example greater than or about 5 x 10¹⁹ cm⁻³, for example greater than or about 6 x 10¹⁹ cm⁻³, for example greater than or about 7 x 10¹⁹ cm⁻³, for example greater than or about 8 x 10¹⁹ cm⁻³, for example greater than or about 9 x 10¹⁹ cm⁻³. cm⁻³, for example, greater than or about 1 x 10²⁰ cm⁻³, for example, greater than or about 2 x 10²⁰ cm⁻³, for example, greater than or about 3 x 10²⁰ cm⁻³, for example, greater than or about 4 x 10²⁰ cm⁻³, for example, greater than or about 5 x 10²⁰ cm⁻³, for example, greater than or about 8 x 10²⁰ cm⁻³, for example, up to about 1 x 10²⁰ cm⁻³, or for example, less than 9 x 10²⁰ cm⁻³, for example, less than or about 8 x 10²⁰ cm⁻³, or any range or value between the above ranges or values.

[0072] Depending on the selective epitaxial growth process used, in the embodiments, it may be desirable or necessary to utilize the etching process discussed above for the first junction layer. In other words, a capping layer and an undoped layer can be formed on the second junction layer, and etched back according to any one or more of the processes described above.

[0073] In an embodiment, after the second junction layer 418 is formed, it may be desirable to establish or improve a doping gradient that extends from the exposed surface of the second junction layer to the interface between the channel / substrate 402 and the first junction layer 420. While it should be understood in the embodiment that two or more junction layers with various doping concentrations can be applied, in the embodiment, it may be desirable to perform an optional post-annealing operation 330 to drive the dopant into or deeper into the target features. Annealing the semiconductor structure 400 can be performed using any suitable technique known in the art. However, in this technique, annealing may be performed at a temperature below the thermal budget. For example, in an inert atmosphere, annealing may occur in a temperature range of about 300°C to about 1100°C, or, for example, above or about 350°C, above or about 400°C, above or about 450°C, above or about 500°C, above or about 550°C, above or about 600°C, above or about 650°C, above or about 700°C, above or about 750°C, above or about 800°C, above or about 850°C, above or about 900°C, above or Approximately 950°C, above or about 1000°C, or for example, below or about 1050°C, below or about 1000°C, below or about 950°C, below or about 900°C, below or about 850°C, below or about 800°C, below or about 750°C, below or about 700°C, below or about 650°C, below or about 600°C, below or about 550°C, below or about 500°C, below or about 450°C, or any range or value in between.

[0074] In other words, such a post-annealing operation may "smooth" the dopant gradient extending from the exposed surface of the second junction layer toward or towards the channel / substrate 402. In embodiments, the doping concentration profile may therefore decrease linearly or logarithmically from the exposed / capacitor side surface of the second junction layer toward the channel / substrate 402. Regardless of the profile chosen, the boundary between the first and second junction layers, and / or the boundary between the first junction layer and the substrate, may become blurred or mixed, such that the layers no longer remain in their respective bonds after annealing. Of course, as mentioned above, in embodiments, additional junction layers may be used to form the desired profile, or the layer thickness may be precisely controlled. For example, as a mere example, if a logarithmic profile with a large ratio between higher and lower doping concentrations is desired, a second junction layer thickness greater than the first junction material thickness may be deposited, and vice versa. However, if a linear profile is desired, these layers may be deposited to make their thickness or depth relatively uniform.

[0075] Regardless of whether post-annealing operation 425 is used, the semiconductor structure of the doped target region according to the present technology can maintain a low oxide level after doping. Therefore, in embodiments, based on the total weight of the target region, in the case of one or more of the doping depths or concentrations discussed above, the doped target region (e.g., storage node junction / target region 412 in FIG. 4B) may contain less than or about 5% by weight of oxide, including intrinsic oxide, such as less than or about 4% by weight, less than or about 3% by weight, less than or about 2% by weight, less than or about 1% by weight, less than or about 0.5% by weight, or less than or about 0.1% by weight, or substantially no oxide.

[0076] Nevertheless, as described above, method 300 according to the present technology is well-suited for doping target regions disposed in grooves, such as groove 404. In other words, the present technology can be used to dope features lacking a linear path from the target region to the processing gas source. In embodiments, the groove may be substantially perpendicular to a second feature containing a linear path to the processing gas source. Furthermore, or alternatively, the methods described herein may also be well-suited for doping regions disposed within channels or features having any of the length, width, and / or aspect ratios discussed above with respect to channel 402, such as these features and channels.

[0077] In the foregoing description, numerous details have been set forth for illustrative purposes in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without these details or with the addition of other details.

[0078] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the technology, many well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the technology.

[0079] Where a numerical range is provided, it should be understood that, unless the context explicitly specifies otherwise, each intermediate value between the upper and lower limits of the range is also specifically disclosed, representing the minimum fraction of the lower limit unit. Any narrower range between any specified value or unspecified intermediate value within the specified range and any other specified value or intermediate value within the specified range is included. The upper and lower limits of these smaller ranges may be independently included or excluded from the range, and each range in which one, two, or neither limit is included is also included in the technique, based on any specifically excluded limit value within the range. When the range includes one or two limits, ranges that do not include one or both of these included limits are also included.

[0080] In the scope of this document and the accompanying claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to “a material” includes multiple such materials, a reference to “the precursor” includes references to one or more precursors and their equivalents known to those skilled in the art, and so on.

[0081] Furthermore, when the words “including,” “comprising,” “containing,” etc. are used in this specification and subsequent claims, they are intended to indicate the presence of the said feature, integer, component, or operation, but do not exclude the presence or addition of one or more other features, integers, components, operations, behaviors, or groups. [Simplified Explanation of the Diagram]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and the illustrations.

[0013] Figure 1 shows a top plan view of an exemplary processing system according to an embodiment of the present technology.

[0014] FIG2 shows a schematic cross-sectional view of an exemplary plasma system according to an embodiment of the present technology.

[0015] Figure 3 illustrates the operation of an exemplary semiconductor processing method according to an embodiment of the present technology.

[0016] Figures 4A and 4B show cross-sectional views of a semiconductor structure according to an embodiment of the present technology.

[0017] Several diagrams are included in schematic form. It should be understood that these diagrams are for illustrative purposes only and should not be considered as representations to scale unless specifically indicated that they are drawn to scale. Furthermore, as illustrative diagrams, these diagrams are provided to aid understanding and may not include all appearances or information compared to realistic representations, and may contain exaggerated material for illustrative purposes.

[0018] In the accompanying drawings, similar parts and / or features may have the same element symbols. Furthermore, various parts of the same type can be distinguished by the letters following the element symbols. If only the first element symbol is used in the specification, the description applies to any similar part having the same first element symbol, regardless of the letters that follow it. [Biomaterial Storage]

[0083] Domestic Deposit Information (Please note in order of deposit institution, date, and number) None

[0084] Overseas Deposit Information (Please note in the order of deposit country, institution, date, and number) None

Claims

1. A semiconductor processing method, comprising: A semiconductor structure having one or more undoped non-visible target regions is provided on a substrate within a semiconductor processing chamber, wherein one or more low thermal budget features are formed on the semiconductor structure; a pre-cleaning operation is performed on the one or more undoped target regions to remove at least a portion of any oxides present on the one or more undoped target regions; a first junction layer is epitaxially deposited over the substrate, the first junction layer having a first dopant concentration of less than 5 x 10¹⁸ dopant atoms / cm³; a second junction layer is epitaxially deposited over the first junction layer, the second junction layer having a second dopant concentration of more than 1 x 10¹⁹ dopant atoms / cm³; wherein a temperature within the semiconductor processing chamber is maintained at less than or about 800°C.

2. The method of claim 1, wherein the temperature within the semiconductor processing cavity is maintained at or below 750°C.

3. The method of claim 1, further comprising, prior to epitaxial deposition of the first interface layer, performing a hydrogen baking on the one or more target regions, wherein the hydrogen baking is performed at a temperature below or about 750°C.

4. The method of claim 1, wherein the one or more target regions are disposed in a recess located within the semiconductor structure.

5. The method as described in claim 1, wherein the one or more target regions are disposed within a feature having a width of 10 nm or less.

6. The method of claim 1, wherein the semiconductor structure is maintained in an oxygen-free environment during the pre-cleaning operation, during epitaxial deposition of the first junction layer, during epitaxial deposition of the second junction layer, or a combination thereof.

7. The method of claim 6, wherein the pre-cleaning operation is integrated into the semiconductor processing chamber.

8. The method of claim 1, further comprising annealing the semiconductor structure after epitaxial deposition of the second junction layer, wherein the annealing is performed at a temperature below or about 1100°C.

9. The method of claim 8, wherein the annealing is performed over a time period and / or at a temperature to form a linear dopant gradient or a logarithmic dopant gradient extending from an outer surface of the second interface layer to the substrate.

10. The method as described in claim 1, wherein the one or more low-thermal budget features include a bit-line contact.

11. A semiconductor processing system, comprising: A first processing chamber; a second processing chamber; a third processing chamber; And a system controller configured to remove at least a portion of any oxide present on one or more undoped target regions of a semiconductor structure in a first processing chamber, the one or more undoped target regions including one or more non-line-of-sight target regions on a substrate of a semiconductor structure within a semiconductor processing chamber, wherein one or more low thermal budget features are formed on the semiconductor structure; epitaxially deposit a first junction layer over the substrate in a second processing chamber, the first junction layer having a first doping concentration of less than 5 x 10¹⁸ dopant atoms / cm³; and epitaxially deposit a second junction layer over the first junction layer in a third processing chamber, the second junction layer having a second doping concentration of more than 1 x 10¹⁹ dopant atoms / cm³.

12. The semiconductor processing system as claimed in claim 11, wherein the semiconductor processing system includes a clustering tool.

13. The semiconductor processing system of claim 11, wherein the semiconductor processing system maintains an oxygen-free environment during the oxide removal, during the epitaxial deposition of the first junction layer, during the epitaxial deposition of the second junction layer, between the oxide removal and the epitaxial deposition of the first junction layer, between the epitaxial deposition of the first junction layer and the epitaxial deposition of the second junction layer, or in a combination thereof.

14. The semiconductor processing system of claim 11, wherein the semiconductor processing system is maintained at a temperature below or at about 750°C.

15. The semiconductor processing system of claim 11, wherein the controller is further configured to perform a hydrogen baking on the one or more target regions prior to epitaxial deposition of the first junction layer, wherein the hydrogen baking is performed at a temperature below or about 750°C.

16. The semiconductor processing system of claim 11, wherein the controller is further configured to anneal the semiconductor structure after epitaxial deposition of the second junction layer, wherein the annealing is performed at a temperature below or about 1100°C.

17. A semiconductor processing system, comprising: A system controller configured to remove at least a portion of any oxide present on one or more undoped target regions of a semiconductor structure, the one or more undoped target regions including one or more non-line-of-sight target regions on a substrate of the semiconductor structure located in a semiconductor processing chamber, wherein one or more low thermal budget features are formed on the semiconductor structure, a first junction layer is epitaxially deposited over the substrate having a first doping concentration of less than 5 x 10¹⁸ dopant atoms / cm³, and a second junction layer is epitaxially deposited over the first junction layer having a second doping concentration of more than 1 x 10¹⁹ dopant atoms / cm³; wherein a temperature within the semiconductor processing chamber is maintained at less than or about 800°C.

18. The semiconductor processing system of claim 17, wherein the semiconductor structure includes a 3D DRAM element.

19. The semiconductor processing system of claim 17, wherein the semiconductor structure includes a 4F2 element, wherein the one or more undoped target regions are disposed in or adjacent to a feature with a width less than or about 10 nm.

20. The semiconductor processing system of claim 17, wherein the length of the one or more undoped target regions from an exposed surface to an internal end is greater than or about 40 nm.

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