Electronic device and manufacturing method of electronic device

Abstract

An electronic component and a method for manufacturing the same are provided. The manufacturing method includes: providing a first portion, wherein the first portion includes a first substrate, an active element formed by a semiconductor epitaxial structure grown on the first substrate, and a first bonding structure formed above the first substrate and electrically coupled to the active element; providing a second portion, wherein the second portion does not contain an active element and includes a second substrate, a passive element formed above the second substrate, and a second bonding structure electrically coupled to the passive element; and forming a signal processing circuit by bonding the first portion and the second portion, wherein the active element and the passive element are electrically coupled by bonding the first bonding structure and the second bonding structure to form the signal processing circuit.

Description

Technical Field

[0001] This invention relates to an electronic component and a method for manufacturing the same, and more particularly to an integrated microelectronic component and a method for manufacturing the same. Prior Technology

[0002] With the rapid development of wireless communication standards, communication devices (such as smartphones and tablets) are constantly evolving to meet user needs. This requires communication components to be smaller, faster in processing speed, and cheaper. Reducing the size of electronic components can help reduce the size of wireless communication components.

[0003] Early integrated circuits (ICs) used discrete, bulky active and passive components, integrating these components onto a circuit board (such as a printed circuit board, PCB). These active and passive components were electrically connected to the circuit board via wire bonding or surface mount technology. The circuit board with the components mounted on it was then processed to form a packaged element. The packaged element could operate in the microwave frequency range (or beyond). This type of integrated circuit is called a microwave integrated circuit (MIC).

[0004] With the advancement of communication standards, the frequency spectrum is increasing. Because it is difficult to implement and process these discrete components at higher frequencies, integrated circuits are no longer suitable for using discrete component microphones (MICs). Instead, monolithic microwave integrated circuits (MMICs) are an alternative method for semiconductor circuit integration. In MMICs, active and passive components are monolithically integrated, meaning they are formed directly on a shared semiconductor substrate.

[0005] Microchips (MMICs) can be fabricated from semiconductor epitaxial layers grown on high-quality substrate materials, such as gallium arsenide (GaAs). In an MMIC, active and passive components are arranged side-by-side in a planar manner and do not overlap in the thickness direction of the MMIC. Layout designs for one or more active components and one or more passive components are inefficient and wasteful. For example, active components formed from a semiconductor epitaxial layer may occupy only a small portion of the semiconductor epitaxial layer, with the remaining portion etched and wasted, while passive components are subsequently formed in those remaining areas. Summary of the Invention

[0006] This invention provides a method for manufacturing an electronic component, comprising at least the following steps: Forming a first portion, wherein the first portion includes a first substrate, an active element formed from an epitaxial structure grown on the first substrate, and a first bonding structure formed above the first substrate and electrically coupled to the active element. Forming a second portion, wherein the second portion includes a second substrate, a passive element formed above the second substrate, and a second bonding structure electrically coupled to the passive element. A signal processing circuit is formed by bonding the first portion and the second portion, wherein the active element and the passive element are electrically coupled by bonding the first bonding structure and the second bonding structure to form the signal processing circuit.

[0007] The present invention also provides an electronic component manufactured by the above-described manufacturing method.

[0008] Based on the above, the present invention provides a novel method for forming electronic components and their structures, wherein a first part and a second part are fabricated separately and then joined together to form a signal processing circuit of the electronic component. The signal processing circuit can be a monolithic microwave integrated circuit (MMIC). Since the active element, as part of the MMIC, is formed in the first part, and the active element is formed separately and independently from almost all (or most, e.g., more than about 80%) of the passive elements, which are also part of the MMIC and formed in the second part, different material choices and different process parameters and techniques can be used, thereby achieving flexible design choices and more adjustable process margins. According to embodiments of the manufacturing method, the separate and independent fabrication of the active and passive elements not only allows for the construction of passive elements with better quality and higher performance but also facilitates the layout design of the integrated circuit. In some embodiments, according to the manufacturing method of the present invention, the passive elements can be stacked above the active elements along the thickness direction, resulting in a smaller occupied area of ​​the circuit.

[0009] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0010] The accompanying drawings are provided to further illustrate the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention. Figures 1A to 1E are schematic cross-sectional views illustrating a method for manufacturing an active element wafer according to some embodiments of the present invention. Figure 1F is a schematic diagram illustrating exemplary layouts of various structures at different levels of an active element wafer according to some embodiments. Figure 2 is a schematic cross-sectional view of a passive component wafer according to some embodiments. Figures 3A to 3G are schematic cross-sectional views illustrating a method of manufacturing electronic components having a front-to-front configuration according to some embodiments. Figure 4 is a circuit diagram of the electronic components of Figure 3G according to some embodiments. Figure 5 is a schematic cross-sectional view of an electronic component according to an alternative embodiment. Figures 6A to 6E are schematic cross-sectional views illustrating a method of manufacturing an electronic component having a front-to-back configuration according to some embodiments. Figure 7 is a schematic cross-sectional view of an electronic component according to an alternative embodiment. Figures 8A to 8E are schematic cross-sectional views illustrating another method of manufacturing electronic components having a front-to-front configuration according to some embodiments. Implementation

[0011] Reference will now be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Throughout the drawings and description, the same reference numerals will be used to refer to the same or similar parts whenever possible.

[0012] Embodiments of the present invention provide novel methods for forming electronic components and their structures. The present invention provides a more efficient method for manufacturing MMICs, wherein active component wafers and passive component wafers are manufactured separately and then joined together to form electronic components. For example, the individual electronic components are monolithic microwave integrated circuit (MMIC) chips. Unlike some MMICs where both passive and active components are formed from the same semiconductor wafer, the manufacturing method of the present invention focuses on forming substantially all the active components required for the MMIC from the active component wafer and substantially all (or most, e.g., more than 80%) of the passive components required for the MMIC from the passive component wafer. According to embodiments of the present invention, the active component wafers and passive component wafers are manufactured separately but are co-designed and vertically integrated to form a complete signal processing circuit. Both the active component wafer and the passive component wafer can be considered as work-in-process or semi-finished units that are part of the signal processing circuit. Through such vertical integration, the die size or occupied area of ​​the signal processing circuit is significantly reduced in the horizontal plane, thus reducing the die size. Furthermore, since the manufacturing of active components is separate and independent from that of passive components, the process methods and conditions for forming passive components are no longer limited by the stringent requirements of the process technologies used to manufacture active components. This provides more flexible choices of process technologies and greater process margins, thereby simplifying manufacturing and improving the overall performance and reliability of components.

[0013] According to embodiments of the present invention, the manufacturing method allows active components to be fabricated on higher-cost wafers, while passive components can be fabricated on lower-cost wafers, thereby achieving higher production yields and more economical production costs. Furthermore, passive components, as part of an integrated circuit, can be fabricated on a substrate with lower dielectric loss, lower signal loss, or a higher quality factor (Q-factor), while active components, as part of an integrated circuit, can be fabricated on an epitaxial layer that provides better electron mobility or a higher breakdown voltage, this epitaxial layer being grown on a substrate with good lattice matching. Since the fabrication of active components is separate and independent from the fabrication of most passive components, and is not limited to the use of process technologies suitable for both active and passive components, active components or passive components can be fabricated separately using the most suitable process technologies and conditions, thereby enabling the optimization of performance characteristics individually for different types of components.

[0014] Figures 1A to 1E are schematic cross-sectional views illustrating a method of manufacturing an active device wafer 100 according to some embodiments of the present invention. Referring to Figure 1A, a semiconductor epitaxial structure 1200 may be formed on a first substrate 1100. The first substrate 1100 may include a first side (or active side) 1100a and a second side (or back side) 1100b opposite to the first side 1100a. The first substrate 1100 may include one or more semiconductor materials, such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), indium phosphide (InP), other suitable compound semiconductors, elemental semiconductors (e.g., silicon (Si), germanium (Ge), etc.), the like, and combinations thereof (e.g., GaN-on-SiC, SiGe, or the like). In some other embodiments, the first substrate 1100 may also include one or more non-semiconductor materials, such as glass, sapphire, and / or the like. Other suitable substrates with higher quality materials may be used to provide good device performance.

[0015] In some embodiments, one or more epitaxial processes may be performed on a first side 1100a of a first substrate 1100 to form a semiconductor epitaxial structure 1200. The semiconductor epitaxial structure 1200 may include one or more semiconductor epitaxial layers. The epitaxial process may be or include metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other suitable epitaxial growth techniques. By optimizing the epitaxial design parameters, the size of the subsequently formed active device can be reduced. In some embodiments, one or more doping processes may be performed on the semiconductor epitaxial structure 1200. In some embodiments where the first substrate 1100 includes one or more non-semiconductor materials (e.g., glass, sapphire, etc.), appropriate surface treatment, specialized buffer layer design, and precise temperature control during the process are required when growing the semiconductor epitaxial structure 1200 on the first substrate 1100. The selection and design of these processes and techniques may vary depending on different application requirements and the design of the semiconductor epitaxial structure 1200.

[0016] The semiconductor epitaxial structure 1200 may include an active region (or active area) R1 and a sacrificial region (or sacrificial area) R2 adjacent to the active region R1. The semiconductor epitaxial structure 1200 in the active region R1 can be used for subsequently formed active devices, while the semiconductor epitaxial structure 1200 in the sacrificial region R2 may be removed or ion-neutralized for electrical isolation. In some embodiments, the semiconductor epitaxial structure 1200 includes a plurality of stacked semiconductor epitaxial layers. Some semiconductor epitaxial layers may be doped, while others may be undoped. For example, one or more semiconductor epitaxial layers doped with p-type dopant and one or more semiconductor epitaxial layers doped with n-type dopant are alternately stacked. In some embodiments, the semiconductor epitaxial structure 1200 includes a semiconductor epitaxial layer having a plurality of doped regions. For example, a portion of the region is doped with p-type dopant and other portions of the region are doped with n-type dopant. The dashed lines shown within the semiconductor epitaxial structure 1200 indicate that the semiconductor epitaxial structure 1200 may include one or more semiconductor epitaxial layers. It should be noted that the number and thickness of one or more semiconductor epitaxial layers 1200 depend on the type of active element subsequently formed, and the present invention does not impose any limitations on this.

[0017] Referring to Figures 1B and 1A, a portion of the semiconductor epitaxial structure 1200 can be patterned to form a plurality of active elements 120, while other portions of the semiconductor epitaxial structure 1200 can be removed (or ion-neutralized). For example, the semiconductor epitaxial structure 1200 in the active region R1 is etched or patterned by performing one or more etching processes to form individual active elements 120 (with corresponding outlines or configurations). The active elements 120 can be or include transistors, such as bipolar transistors (e.g., heterojunction bipolar transistors (HBTs), bipolar junction transistors (BJTs), etc.), field-effect transistors (FETs) (e.g., high electron mobility transistors (HEMTs)), diodes, the like, combinations thereof, etc. Other portions of the semiconductor epitaxial structure 1200 in the sacrificial region R2 can be removed by one or more etching processes and / or neutralized by one or more ion bombardment processes.

[0018] In some embodiments, referring to the exemplary unfolded view shown at the top of FIG1B, where the HBT serves as an exemplary active element, each active element 120 includes a sub-collector layer 120C1, a collector layer 120C2, a base layer 120B covering the collector layer 120C2, an emitter layer 120E covering the base layer 120B, and a capping layer 120P covering the emitter layer 120E, wherein the sub-collector layer 120C1, collector layer 120C2, base layer 120B, emitter layer 120E, and capping layer 120P are operatively coupled to form an HBT. As shown in FIG1B, the active element 120 implemented as an HBT may have a stepped profile. Such a stepped profile may result in an uneven top surface of the subsequently formed dielectric layer (1300 in FIG1C). In some embodiments, the base layer 120B is made of a p-type doped material, the emitter layer 120E is made of an n-type doped material, and the capping layer 120P is made of an n-type doped material. For example, the thickness 120EH of the junction of the emitter layer 120E and the capping layer 120P is in the range of about 50 nm to 300 nm, and the thickness 120BH of the base layer 120B is in the range of about 30 nm to 100 nm. The base layer 120B may be thinner than the thickness 120EH and the collector layer 120C2. For example, the sub-collector layer 120C1 is an n-type doped material and the collector layer 120C2 is an n-type doped material. The collector layer 120C2 may be formed using a gradient doping technique, and the doping concentration of the collector layer 120C2 is lower than the doping concentration of the sub-collector layer 120C1. For example, the total thickness 120CH of the collector layer 120C2 and the sub-collector layer 120C1 is approximately in the range of 1000 nm to 3500 nm. It should be noted that the thickness range provided here is only an example and may vary depending on product and design requirements.

[0019] In some embodiments, the ion-neutralized epitaxial structure 1200N in the sacrificial region R2 laterally surrounds the subcollector layer 120C1. Alternatively, the portion of the semiconductor epitaxial structure in the sacrificial region R2 is ion-neutralized (or etched away). Therefore, the ion-neutralized epitaxial structure 1200N is shown in dashed lines to indicate that it is non-functional or absent.

[0020] In some embodiments, contacts (including 120CC, 120BC, and 120EC) are formed on the sub-collector layer 120C1, the base layer 120B, and the capping layer 120P covering the emitter layer 120E, respectively. The contacts (e.g., 120EC, 120BC, and 120CC) may be formed during or after etching the semiconductor epitaxial structure 1200 to form a stepped pyramidal profile of the sub-collector layer 120C1, collector layer 120C2, base layer 120B, emitter layer 120E, and capping layer 120P. For example, the contacts (including 120EC, 120BC, and 120CC) may be made of one or more conductive materials. In some embodiments, emitter contact 120EC is formed on the top surface of capping layer 120P, base contact 120BC is formed on the top surface of base layer 120B and disposed next to emitter layer 120E, and collector contact 120CC is formed on the top surface of sub-collector layer 120C1 and disposed next to collector layer 120C2.

[0021] The main application areas for using HBTs as active components 120 include wireless communication, fiber optic communication, satellite communication, and automotive electronics. For example, the active component 120 is implemented using an HBT with excellent high-frequency performance and can be used in power amplifiers in wireless communication components and base stations. In some embodiments, due to the high electron mobility and excellent frequency response of HBTs, the active component 120 is implemented as an HBT in fiber optic communication modules. In some embodiments, due to the high gain and high-frequency performance of HBTs, the active component 120 is implemented as an HBT in satellite communication equipment and for power amplification and signal processing. In some embodiments, due to the high reliability and high power performance of HBTs, the active component 120 is implemented as an HBT in automotive electronic systems.

[0022] Referring again to FIG1B, specifically the exemplary unfolded view shown in the middle portion of FIG1B, where the HEMT serves as an exemplary active element, in some embodiments, each active element 120 includes a source region 120S, a drain region 120D, and a channel region 120C' formed between the source and drain regions (120S and 120D), wherein these regions and subsequently formed gate and source / drain electrodes are operatively coupled to form the HEMT. The channel region 120C' utilizes a heterostructure composed of a suitable compound semiconductor material to form a high electron mobility two-dimensional electron gas (2DEG), thereby improving the high-frequency performance and electron mobility of the device. In some embodiments, an ion-neutralized epitaxial structure 1200N in the sacrificial region R2 laterally surrounds the source and drain regions (120S and 120D). For example, the portion of the semiconductor epitaxial structure in the sacrificial region R2 may be ion-neutralized (or etched away) by ion implantation. Therefore, the ion-neutralized epitaxial structure 1200N is shown as a dashed line to indicate that it is non-functional or non-existent. It should be noted that the illustration of the active element 120 in Figure 1B is merely an example and the active element 120 may have a different configuration / type than that shown in the figure.

[0023] In some embodiments, the active area layout ratio (AAL ratio), i.e., the ratio of the total surface area of ​​the active area R1 to the total surface area of ​​the first side 1100a of the first substrate 1100, is about 10% or more than 10%, or in the range of about 10% to about 90%. The active area (AA) can be the total surface area of ​​one or more semiconductor epitaxial layers forming the active element 120 and / or can be the total surface area of ​​the active area R1. For example, the AAL ratio can be about 20% or more, or in the range of about 20% to about 50%. The ratio of the total surface area of ​​the active area R1 to the total surface area of ​​the first side 1100a of the first substrate 1100 (referred to as the AAL ratio) can be any suitable value, such as equal to or greater than 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, and equal to or less than 90%, or can be any suitable range between about 10% and about 90%, or any suitable range between about 10% and about 50%. It is worth noting that for some MMICs that include active and passive components integrated on a shared substrate on a single wafer, the ratio of the total surface area of ​​the active region R1 to the total wafer area is typically less than 30%, for example, about 5% to 25%. In this embodiment, the ratio of the total surface area of ​​the active region R1 to the total wafer area (e.g., the AAL ratio) can be higher because the total wafer area (e.g., the active component wafer area) is effectively and primarily used to form active components, rather than passive components. As the die size shrinks, the number of active components 120 per unit area can be significantly increased, and the active components of the MMIC can be manufactured at a lower cost according to the manufacturing method described herein.

[0024] Referring to Figures 1C and 1B, a dielectric layer 1300 can be formed on a first side 1100a of the first substrate 1100 to cover the active element 120. The dielectric layer 1300 may be thick enough to embed the active element 120 therein. The dielectric layer 1300 may include one or more suitable dielectric materials, such as silicon nitride, silicon oxide, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), similar materials, combinations thereof, etc. The dielectric layer 1300 may be formed by any suitable deposition process (e.g., spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.). In some embodiments, the dielectric layer 1300 has a top surface 1300t that is uneven or even rough, consisting of high points and low points, wherein the high points correspond to the regions where active elements 120 are formed, and the low points correspond to the remaining regions where no active elements 120 are formed.

[0025] Referring to Figures 1D and 1C, a portion of the dielectric layer 1300 can be removed to form a dielectric layer 130 with an opening 130P. A contact plug 140 is then formed in and fills the opening 130P. For example, one or more etching processes are performed on the dielectric layer 1300 to form the opening 130P, wherein the opening 130P exposes at least a portion of the active element 120. Next, one or more conductive materials can be formed in the opening 130P to form the contact plug 140, which makes physical and electrical contact with the portion of the active element 120 exposed by the opening 130P. A smoothing process (e.g., grinding, etching, and / or rough chemical mechanical polishing (CMP)) can be selectively performed on the dielectric layer 130 (and the contact plug 140, if desired) to make the top surfaces of the dielectric layer 130 and the contact plug 140 flush or flat. However, it should be understood that, depending on the non-uniformity of dielectric layer 130, the top surface 130t of dielectric layer 130 can be completely planarized. Dielectric layer 130 can have a sufficient thickness 130H to serve as insulation, and the material of dielectric layer 130 can be selected to help improve electromagnetic interference between active and passive components. Vias, plugs, and via plugs are interchangeable here.

[0026] In some embodiments, referring to the exemplary unfolded view shown at the top of FIG1D, where the HBT serves as an exemplary active element, opening 130P exposes portions of the collector contact 120CC, the base contact 120BC, and the emitter contact 120EC. Therefore, the contact plug 140 formed in opening 130P can physically and electrically contact portions of the collector contact 120CC, the base contact 120BC, and the emitter contact 120EC, thereby forming collector terminal 140C, base terminal 140B, and emitter terminal 140E, respectively.

[0027] In some embodiments, referring to the exemplary unfolded view shown in the middle portion of FIG1D, where the HEMT serves as an exemplary active element, opening 130P exposes a portion of the source region 120S, a portion of the drain region 120D, and a portion of the channel region 120C'. Therefore, the contact plug 140 formed in opening 130P can physically and electrically contact the source region 120S, the drain region 120D, and the channel region 120C', respectively forming the source contact 140S, the drain contact 140D, and the gate electrode 140G.

[0028] Referring to Figures 1E and 1D, an interconnect structure 150 is formed over a dielectric layer 130, followed by a bonding structure 160. In some embodiments, the bonding structure 160 formed over the dielectric layer 130 is electrically coupled to the active element 120 via contact plugs 140 and the interconnect structure 150. In some embodiments, the bonding structure 160 includes a bonding dielectric layer 161 and a plurality of bonding features 162 embedded in the bonding dielectric layer 161. The material of the bonding dielectric layer 161 may be different from the material of the dielectric layer 130. The bonding features 162 may include one or more conductive materials and may be electrically coupled to the contact plugs 140. In some embodiments, the bonding features 162 are made of one or more metals, alloys, or metallic materials. Each bonding feature 162 may be or include a bonding pad, a bonding via, a metal pad, or a combination thereof.

[0029] In some embodiments, a planarization process (e.g., CMP, polishing, etc.) is performed on the bonding structure 160 to form a smoother and flatter surface that facilitates bonding. For example, through a fine planarization process, the top surface 162t of the bonding feature 162 and the top surface 161t of the bonding dielectric layer 161 may be substantially coplanar. In some embodiments, with the fine planarization process, one or more conductive features may be polished so that the top surface 162t is not completely flat, for example, some top surfaces 162t are slightly recessed or protruding from the top surface 161t. The top surface 162t of the bonding feature 162 and the top surface 161t of the bonding dielectric layer 161 can be collectively considered as the bonding surface 160t of the bonding structure 160 of the active element wafer 100. The bonding surface 160t may be substantially uniform and have a higher flatness than the top surface 130t of the dielectric layer 130. For example, the bonding surface 160t exhibits better surface flatness and lower surface roughness than the top surface 130t of the dielectric layer 130.

[0030] Referring again to Figures 1E and 1D, an interconnect structure 150 is formed over a dielectric layer 130 before the bonding structure 160 is formed, and the bonding structure 160 is subsequently formed on the interconnect structure 150. After the interconnect structure 150 and the bonding structure 160 are formed, an active element wafer 100 is formed. For example, the interconnect structure 150 includes at least a dielectric layer 151 and a metallization pattern 152 embedded in the dielectric layer 151, wherein the metallization pattern 152 of the interconnect structure 150 electrically couples the bonding feature 162 above to a plurality of contact plugs 140 below. It should be understood that the dielectric layer 151 may include a plurality of dielectric layers, and the metallization pattern 152 may be sandwiched between adjacent dielectric layers. In some embodiments, the metallization pattern 152 includes conductive pads and wires extending horizontally over the top surface 130t of the dielectric layer 130, and vertically extending vias for electrical coupling to adjacent active elements 120 via contact plugs 140. In some embodiments, the metallization pattern 152 reroutes the electrical signals of the active element 120 and is regarded as a wiring pattern.

[0031] Referring again to Figures 1E and 1D, the bonding structure 160 may include a thermally conductive feature 163 (one shown) embedded in and laterally covered by the bonding dielectric layer 161. In some embodiments, the thermally conductive feature 163 may also serve as one or more electrically conductive features. Each thermally conductive feature 163 may include a thermally conductive pad, a thermally conductive via, or a combination thereof. The thermally conductive feature 163 may include one or more conductive materials that are the same as the material of the bonding feature 162. Alternatively, the thermally conductive feature 163 may include one or more materials with a higher thermal conductivity than the material of the bonding feature 162. The top surface 163t of the thermally conductive feature 163 may be substantially coplanar with the top surface 162t of the bonding feature 162 and may be contained within the bonding surface 160t. In some embodiments, the top surface 163t of one or more of the thermally conductive features 163 is not completely planar; for example, some top surfaces 163t may be slightly recessed or convex from the top surface 161t. In Figure 1E, a schematic top view of the partial structure circled by the lower dashed box is shown in the upper dashed box at the top of Figure 1E, illustrating one arrangement of the thermally conductive features 163 and contact plugs 140. It is important to note that the top view of the components shown in Figure 1E is merely an example, and the invention is not intended to limit this. In some embodiments, the lateral dimension LD1 of each thermally conductive feature 163 is greater than the lateral dimension LD2 of each contact plug 140 (in embodiments where the active element is an HBT, this refers to the common-emitter terminal 140E', or in embodiments where the active element is a HEMT, this refers to the common-source terminal 140S') to achieve better heat dissipation. Alternatively, the lateral dimensions LD1 and LD2 may be approximately equal to each other.

[0032] Referring again to Figures 1E and 1D, in some embodiments where some (or all) of the active elements 120 are implemented as HBTs, the interconnect structure 150 includes at least one conductive layer 145 formed above the common-emitter terminal 140E' of the underlying active element 120 and thermally connected to one or more thermally conductive features 163 above. The conductive layer 145 is thermally connected to the thermally conductive features 163 above and the contact plugs 140 (e.g., common-emitter terminal 140E') of the one or more underlying active elements 120 to facilitate heat transfer and dissipation, and serves as part of a heat transfer element or heat dissipation path in the resulting element. In some embodiments, the conductive layer 145, electrically coupled or connected to the common-emitter terminal 140E', is electrically grounded and serves as a grounding element. For example, the conductive layer 145 is formed as a thermally conductive metal strip or band extending horizontally on and conformally covering the top surface 130t of the dielectric layer 130. In some embodiments where the dielectric layer 130 has a non-flat or uneven top surface, the bottom surface 145b, top surface 145t, or both bottom surface 145b and top surface 145t of the conductive layer 145 may be formed as a non-flat or uneven surface conformal to the top surface 130t of the dielectric layer 130. In some embodiments, the conductive layer 145 is formed within the interconnect structure 150 and is at the same level as any of the metallization patterns 152 of the interconnect structure 150. Notably, the conductive layer 145 may be thermally connected to the thermally conductive feature 163 and the contact plug 140 above it for heat transfer and heat dissipation purposes. However, for heat transfer and heat dissipation purposes, the conductive layer 145 is not necessarily physically directly connected to the thermally conductive feature 163 and / or the contact plug 140.

[0033] Although only two contact plugs 140 (e.g., common emitter 140E') of two active elements 120 are shown in Figure 1E, the conductive layer 145 may span multiple contact plugs 140 (e.g., common emitter 140E') of multiple active elements 120 as required by the product.

[0034] In some embodiments where the active element 120 is implemented as a FET (e.g., a HEMT), a conductive layer 145 is formed over the common source terminal 140S' of the active element 120, and one or more thermally conductive features 163 may be formed over the conductive layer 145. In addition to being part of a heat dissipation path, the conductive layer 145 and the one or more thermally conductive features 163 may then be coupled to an electrically grounded pad (see FIG. 3G) in the fabricated element.

[0035] The active element wafer 100 (see FIG. 3A) can then be prepared for the subsequent bonding process. The active element wafer 100 may consist of the following components: a first substrate 1100, an active element 120 epitaxially grown on the first substrate 1100, a contact plug 140 disposed on the active element 120, a dielectric layer 130 covering the active element 120 and the contact plug 140, a bonding structure 160 covering the dielectric layer 130 and the contact plug 140, and an interconnection structure 150 between the bonding structure 160 and the contact plug 140. In some embodiments, the active element wafer 100 does not contain passive components (e.g., inductors, capacitors, resistors, etc.). The active element 120 and the conductive features coupled thereto (e.g., 140, 145, 162, and 163) may not be formed into functional circuits / signal processing circuits (e.g., power amplifiers, low-noise amplifiers, mixers, etc. for radio frequency (RF) applications) at this stage. Active component wafer 100 can be considered as a work-in-process (WIP) unit.

[0036] In an alternative embodiment, the active element wafer 100 includes active elements 120 and passive elements (e.g., resistors, capacitors, and / or inductors) connected to the active elements 120 for certain purposes. For example, some active elements 120 are connected to resistors (e.g., formed by epitaxial structures or thin-film resistors) to control the current flowing to these active elements, thereby improving thermal stability. In this case, the combination of these active elements and resistors in the active element wafer 100 does not have the functionality of a signal processing circuit. Signal processing circuitry can be formed after the active element wafer 100 and the passive element wafer (see FIG. 3A) are physically and electrically bonded. Therefore, in such an embodiment, the active element wafer 100 can still be considered a WIP (Work in Progress) cell.

[0037] It should be understood that the active element wafer 100 is a wafer structure composed of a plurality of diced units or die units. After the active element wafer 100 and at least one passive element wafer are bonded, the bonded structure is then diced to form an electronic component with signal processing capabilities. Thus, the diced units or die units of the active element wafer 100 can be considered as the active element portion of the electronic component. Figure 1F is a schematic diagram illustrating exemplary layouts of various structures at different levels of the active element wafer according to some embodiments. In Figure 1F, a diced unit of the active element wafer 100A is shown as an example portion of the active element wafer 100A, and the active element wafer 100A is substantially the same as the active element wafer 100 described above. Referring to Figure 1F, in some embodiments, an element layer DL1 is shown to represent an active element formed within the active element wafer 100A, a bonding plane BP1 is shown to represent a bonding surface or interface of a bonding structure, and a common platform CP1 is located between the element layer DL1 and the bonding structure. It should be noted that the common platform CP1 is located at the level of interconnect structure 150 (in FIG. 1E) and can be formed as part of the interconnect structure and located within interconnect structure 150. Although only a portion of the active element wafer is shown, the common platform CP1 extends to the entire element layer in the diced cells (spanning most or all of the active elements) and even extends above most or all of the diced cells of the entire active element wafer 100A.

[0038] Referring to FIG1F, in some embodiments where the active element is implemented as an HBT and shown as element layer DL1, the base terminal B1 and the collector terminal C1 are arranged in separate regions, while the emitter terminal E1 is arranged in several separate regions adjacent to and spaced apart from the base terminal B1 and the collector terminal C1. The exemplary configurations or shapes of the base terminal B1, collector terminal C1, and emitter terminal E1 are merely simplified and schematic and do not reflect the physical outlines, construction, or layout patterns of these components, and the number or size of these components shown in the figures is not intended to limit the scope of the invention. In some embodiments, the common platform CP1 is formed as a sheet of metal extending within the interconnect structure 150 (e.g., extending within the dielectric layer 151 above the dielectric layer 130 and the active element 120, see FIG1E) over the entire diced cell of the active element wafer. In some embodiments, the common platform CP1 serves as a macro ground plane (common ground plane) in the diced cells of all elements in element layer DL1. The common platform CP1 serves as a macro ground plane, especially for high-frequency components, to minimize parasitic grounding inductance on the emitter terminals, thereby achieving better electrical performance. In one embodiment, the common platform CP1, formed together with the metallization pattern, is also made of a high thermal conductivity material (e.g., copper or copper alloy) and also functions as a heat sink or heat transfer component.

[0039] Referring to Figure 1F, the electrical connections between each emitter E1 and the common platform CP1, and between the common platform CP1 and each contact EC2, can be established respectively by at least one vertically extending conductive plug or metal via plug EV1 and EV2 to create shorter or shortest path electrical connections. The dashed box on the common platform CP1 in Figure 1F can be considered as the location of the contact of the metal via plug EV2. The common platform CP1 as a whole serves as the platform for connection contact with the emitter E1, and the metal via plug EV2 electrically connects the common platform CP1 to the contact EC2 of the emitter E1. Furthermore, since all (or most) emitters of the element layer / level are connected to the common platform, the common platform is connected to the ground pad / plane of the cut cell via metal connections, thus establishing a shorter or shortest metal connection path from emitter to ground, minimizing unnecessary additional inductance and further improving the performance of the MMIC. It should be understood that stacked vias and selective metallization patterns (including traces / wires in the interconnect structure) can also be combined for electrical connections.

[0040] In some embodiments, regardless of the location of the emitter E1, the emitter E1s of all (or most) elements in the element layer DL1 are connected to the common platform CP1, thereby merging all (or most) emitter E1s onto the same common platform CP1. In some embodiments, for layout flexibility, the contacts EC2 of the emitter E1 are positioned on the bonding plane BP1 in the peripheral area of ​​the bonding plane BP1 and / or adjacent to the cut cell or at the corner of the cut cell, so that the non-peripheral area (internal middle area) of the bonding plane BP1 of the cut cell can be preserved. The peripheral layout of the contacts EC2 of the emitter E1 on the bonding plane BP1 results in the corresponding bonding pads of the passive element wafers bonded to the active element wafers also being correspondingly peripherally positioned. Therefore, the remaining internal region of the bonding plane of the active component wafer can be regarded as a reserved open internal region. After the active component wafer is bonded to the passive component wafer, the internal region can correspond to the region for the layout of the passive component in the passive component wafer and / or for the layout of other auxiliary circuit components, such as components or components for matching networks, bias circuits, protection circuits, power detection circuits, linearization circuits, temperature compensation circuits, etc.

[0041] In some embodiments, the common platform CP1 has openings G1 and G2, and the positions of openings G1 and G2 may correspond to (or be perpendicularly aligned with) the positions of the common base terminal B1 and the common collector terminal C1, such that the connection between the base terminal B1 and its corresponding contacts BC1 and BC2, and the connection between the collector terminal C1 and its corresponding contacts CC1 and CC2, pass through the openings G1 and G2 on the common platform CP1 and reach the mating plane BP1. The base terminal B1 and the collector terminal C1 are not electrically connected to the common platform CP1. For example, the base terminal B1 is connected to the contact BC1 formed in the opening G1 and to the contact BC2 formed in the mating plane BP1, and the collector terminal C1 is connected to the contact CC1 formed in the opening G2 and to the contact CC2 formed in the mating plane BP1. This layout design of the cut cells allows the base terminal B1 and the collector terminal C1 to pass through the common platform CP1. In Figure 1F, contacts BC1 and BC2 are electrically connected to the base terminal B1, and contacts CC1 and CC2 are electrically connected to the collector terminal C1. This electrical connection is not limited to the exemplary plug shown in the figure. It should be understood that electrical connections can be established via one or more vertically extending vias or metal vias to create shorter electrical connection paths, and can incorporate metallization patterns including traces / wires in the interconnect structure.

[0042] This decentralized arrangement allows the non-peripheral or internal portions of the bonding plane BP1 of the cut cell to become open areas, enabling further peripheral connections between the contacts EC2 of the emitter E1 and the bonding pads in the passive component wafer (within the peripheral area and / or near the corners of the cut cell). This peripheral / decentralized arrangement preserves open internal areas within the passive component portion of the cut cell for the placement of passive components in the passive component wafer and / or for other auxiliary circuitry and matching networks, significantly improving the flexibility of the placement design. This flexibility significantly improves the potentially complex placement process of the passive component wafer. Furthermore, the shared platform configuration excels in controlling thermal runaway in active components, significantly improving the thermal management capabilities of the components through optimized heat dissipation structures, thereby enhancing the overall reliability of the MMIC.

[0043] Figure 2 is a schematic cross-sectional view of a passive component wafer 200 according to some embodiments. Referring to Figure 2, the passive component wafer 200 may include a second substrate 2100, which includes a first side (or front side) 2100a and a second side (or back side) 2100b opposite to the first side 2100a. The second substrate 2100 may have one or more substrate materials, such as glass, silicon, sapphire, compound semiconductor, semiconductor-on-insulator (SOI), or combinations thereof, or other suitable substrate materials selected according to the semiconductor process parameters of the structure formed thereon. In some embodiments, the material of the second substrate 2100 is different from the material of the first substrate 1100 described in Figure 1A. For example, the first substrate 1100 is made of one or more substrate materials suitable for epitaxial growth, while the one or more materials of the second substrate 2100 may be selected from a set of candidate substrate materials according to the type of passive component to be formed, including substrate materials with low dielectric loss or high temperature resistance. For example, the material of the first substrate 1100 can withstand process temperatures below 300°C, while the material of the second substrate 2100 can withstand process temperatures above 300°C (even up to 400°C or 450°C). One or more materials of the second substrate 2100 can be independently selected to appropriately meet the performance requirements of one or more elements or assemblies formed therein or on it, without compromising to meet the process requirements of one or more other elements formed in the first substrate 1100.

[0044] In an alternative embodiment, the first substrate 1100 and the second substrate 2100 comprise one or more substrate materials that are substantially the same or similar.

[0045] Referring again to FIG. 2, the passive component wafer 200 may include passive components 220 formed above a first side 2100a of the second substrate 2100. The passive component 220 may be or include inductors (e.g., planar spiral inductors, solenoid inductors, or the like), capacitors (e.g., metal-insulator-metal (MIM) capacitors, or the like), resistors, the like, combinations thereof, etc. The passive components 220 can be used in various combinations for interconnect, filtering, impedance matching, termination, decoupling, and other applications and combinations thereof. In some embodiments, the passive components 220 are arranged side-by-side above the second substrate 2100. It should be noted that the arrangement of the passive components 220 shown in FIG. 2 is merely an example and the passive components 220 may have different arrangements than those shown. For example, one of the passive components 220 (e.g., implemented as a solenoid inductor) is positioned above another passive component 220 (e.g., implemented as a capacitor) along the thickness direction of the passive component wafer 200, wherein the axis of the solenoid inductor is parallel to the first side 2100a of the second substrate 2100. This structure allows the magnetic field of the solenoid inductor to be more concentrated and uniform inside the solenoid inductor, while the magnetic field outside the solenoid inductor is weaker, thereby reducing interference or coupling between the solenoid inductor and components placed above or below it. The inductance and quality factor of the solenoid inductor can be more controllable and predictable. This is beneficial for circuit design.

[0046] The material of the passive element 220 can be selected to reduce its size. In some embodiments, the dielectric film (not shown separately) in the passive element 220 (e.g., a capacitor) can be or include one or more high-k polymer materials or other suitable dielectric materials that can increase capacitance density and reduce capacitor size. In some embodiments, one or more high-resistivity materials can be used to form the passive element 220 (e.g., a resistor). The size of the passive element 220 (e.g., implemented as a resistor) can be reduced by performing one or more surface polishing processes on the second substrate 2100 and / or the dielectric layer formed thereon. For example, by providing a flatter surface to be patterned, the overlay accuracy of the photomask (not shown) and the passive element wafer 200 can be improved. The flatter the surface, the narrower the width of the resistor can be. Since the active element wafer 100 and the passive element wafer 200 are manufactured separately, certain process issues on the active element are no longer process-limited, thus allowing for greater flexibility in the material selection and design of the passive element 220. One advantage of manufacturing the passive component wafer 200 separately is that one or more processes at higher process temperatures can be performed on the second substrate 2100, thereby obtaining a passive component 220 with improved performance and / or reliability.

[0047] It should be understood that the passive component wafer 200 is a wafer structure composed of multiple diced units or die units. After the passive component wafer 200 is bonded to the active component wafer 100, the bonded structure is then diced to form an electronic component with signal processing function. Thus, the diced units or die units of the passive component wafer 200 can be regarded as the passive component part of the electronic component.

[0048] In some embodiments, the passive component wafer 200 includes a passive component 220 embedded within at least one dielectric layer 230. The material of the dielectric layer 230 may differ from the material of the dielectric layer 130 shown in FIG. 1C. In some embodiments, the dielectric layer 230 comprises one or more polymeric materials with high dielectric constants or other suitable dielectric materials formed as multiple sublayers or a single layer. For example, the material of the dielectric layer 230 can withstand process temperatures higher than the material of the dielectric layer 130. In some embodiments, interconnects (not shown separately) are formed in the dielectric layer 230 for horizontal connection to adjacent passive components 220.

[0049] Referring again to FIG2, the passive component wafer 200 may include an interconnect structure 250 overlying a dielectric layer 230 and electrically coupled to the passive component 220. The interconnect structure 250 may include a dielectric layer 251 and a wiring layer 252 embedded in the dielectric layer 251, wherein the wiring layer 252 is electrically coupled to the passive component 220. The wiring layer 252 may include conductive pads, vias, wires, combinations thereof, etc. The passive component wafer 200 may include a bonding structure 260 formed over the interconnect structure 250 and electrically coupled to the passive component 220 via the interconnect structure 250. In some embodiments, the bonding structure 260 includes a bonding dielectric layer 261 and a plurality of bonding features 262 laterally covered by the bonding dielectric layer 261. The bonding dielectric layer 261 may have a different material than one or more dielectric layers (251 and / or 230). The bonding dielectric layer 261 may comprise the same or similar material as the bonding dielectric layer 161 of the active element wafer 100 described in FIG. 1E. Alternatively, the bonding dielectric layer 261 may comprise a different material than the bonding dielectric layer 161. The bonding feature 262 may comprise one or more conductive materials and may be electrically contacted with the wiring layer 252. In some embodiments, a planarization process (e.g., fine CMP, polishing, etc.) is performed on the bonding structure 260 such that the top surface 262t of the bonding feature 262 and the top surface 261t of the bonding dielectric layer 261 are substantially coplanar with each other. It should be understood that for "substantially coplanar" surfaces, a specific small height difference within the process variation range is acceptable, and the substantially coplanar surfaces can be achieved by chemical mechanical polishing (CMP), and the substantially coplanar surfaces are beneficial for subsequent hybrid wafer bonding. Furthermore, in hybrid bonding, bonding feature 262 and bonding dielectric layer 261 may intentionally form slight height variations (e.g., several nanometers) to facilitate effective bonding, while maintaining generally coplanar surfaces from a macroscopic perspective. The top surface 262t of bonding feature 262 and the top surface 261t of bonding dielectric layer 261 can be collectively considered as the bonding surface 260t of bonding structure 260 of passive component wafer 200.

[0050] Referring again to FIG. 2, the bonding structure 260 may include a thermally conductive feature 263 embedded in and laterally covered by the bonding dielectric layer 261. In some embodiments, one or more thermally conductive features 263 may include one or more conductive materials that are the same as the material of the bonding feature 262. Alternatively, one or more thermally conductive features 263 may include one or more materials with a higher thermal conductivity than the material of the bonding feature 262. The top surface 263t of the thermally conductive feature 263 may be substantially coplanar with the top surface 262t of the bonding feature 262 and may be contained in the bonding surface 260t. In some embodiments, thermally conductive pillars 253 may be formed below the thermally conductive features 263 and pass through the dielectric layers 251 and 230. For example, at this stage, one or more thermally conductive pillars 253 may reach the first side 2100a of the second substrate 2100.

[0051] Referring again to Figure 2, a passive component wafer 200 (see Figure 3A) can then be prepared for the subsequent bonding process. The passive component wafer 200 may consist of: a second substrate 2100, a passive component 220 formed on the second substrate 2100, a dielectric layer 230 in which the passive component 220 is embedded, an interconnect structure 250 covering the dielectric layer 230 and the passive component 220, and a bonding structure 260 covering the interconnect structure 250. Since the second substrate 2100 does not undergo any epitaxial process, the passive component wafer 200 may not contain an epitaxial layer. The passive component wafer 200 may not contain active components (e.g., transistors, diodes, etc.). At this stage, the passive component 220 and its coupled conductive features (e.g., 252 and 262) have not yet been formed into functional circuits / signal processing circuits (e.g., power amplifiers, low-noise amplifiers, mixers, etc. for RF applications). Passive component wafer 200 can be considered as a WIP unit used to form an important part of functional circuits / signal processing circuits.

[0052] Figures 3A to 3G are schematic cross-sectional views illustrating a method of manufacturing electronic components with a front-to-front configuration according to some embodiments. Referring to Figure 3A and Figures 1E and 2, a passive component wafer 200 may be stacked on and bonded to an active component wafer 100. For simplicity, the interconnect structure 150 within the active component wafer 100 in the following figures is simplified by omitting certain components and secondary structures and showing only the conductive layer 145 as a representative component embedded in the dielectric layer. Referring to Figure 3A, a passive component 220 in the passive component wafer 200 is stacked on and above an active component 120 in the active component wafer 100 such that the stacked passive component 220 and the active component 120 overlap in position along the thickness direction (the vertical direction in Figure 3A). For example, a bonding structure 260 of the passive component wafer 200 is bonded to a bonding structure 160 of the active component wafer 100. In some embodiments, the bonding dielectric layer 261 of bonding structure 260 is fused with the bonding dielectric layer 161 of bonding structure 160. In some embodiments, each of the bonding features 262 of bonding structure 260 is bonded to one of the bonding features 162 of bonding structure 160. For example, the metals in the bonding features (262 and 162) contact each other and then diffuse into each other to form a metal-to-metal bond. In some embodiments, the thermally conductive feature 263 in bonding structure 260 is bonded to the thermally conductive feature 163 in bonding structure 160 using the same bonding method as in bonding features 262 and 162.

[0053] In some embodiments, the bonding surfaces (160t and 260t) have high flatness, and the bonding interface 12F between the passive component wafer 200 and the active component wafer 100 is substantially flat and planar. Since the first side (front side) 2100a of the passive component wafer 200 is closer to the first side (active side) 1100a of the active component wafer 100 than the second side (back side) 2100b of the passive component wafer 200, the first side (front side) 2100a of the passive component wafer 200 can be understood as the front side facing the front side of the active component wafer 100. Therefore, the configuration of the bonded structure in FIG. 3A can be considered as a front-to-front configuration. After bonding the passive component wafer 200 to the active component wafer 100, the active component 120 in the active component wafer 100 can be electrically coupled to the passive component 220 in the passive component wafer 200 to form a functional circuit / signal processing circuit (e.g., a power amplifier, low-noise amplifier, mixer, etc. for RF applications).

[0054] Here, as mentioned earlier in the peripheral / decentralized arrangement, the bonding of thermally conductive features between the active component wafer 100 and the passive component wafer 200 can be similar to the connection between the bonding pad 163 (corresponding to the contact EC2 on the bonding plane BP1) of the active component portion and the bonding pad 263 of the passive component portion, which is confined to the peripheral portion or exterior of the passive component portion. With this arrangement, open internal areas for the layout of passive components in the passive component wafer and / or for other auxiliary circuits and matching networks are preserved in the passive component portion of the diced cell, thereby greatly improving the flexibility of the layout design.

[0055] Referring to Figures 3B and 3A, a thinning process is selectively performed on the second side 2100b of the passive component wafer 200 to form a second substrate 210 having a thinned back side 210b. For example, the second substrate 210 has a thinned thickness 210H measured between the thinned back side 210b and the first side (front side) 2100a. In some embodiments, the thinned thickness 210H is in the range of about 50 micrometers to about 250 micrometers. It should be noted that the value of the thinned thickness 210H may vary depending on design and product requirements. Alternatively, the thinning process may be omitted as long as the thickness of the second substrate 2100 meets the requirements of the product or subsequent processes, or a combination of both. Next, a portion of the second substrate 210 may be removed to form an opening 210P in the second substrate 210, wherein the opening 210P exposes at least a portion of the passive component 220. In some embodiments, the passive element 220 is surrounded by a dielectric layer 230, and a portion of the dielectric layer 230 is removed together with a portion of the second substrate 210 to form an opening 210P that exposes at least a portion of the passive element 220. In some embodiments, one or more openings 210P' may be formed to expose at least a portion of one or more heat-conducting pillars 253.

[0056] Referring to Figures 3C and 3B, a through substrate via (TSV) 271 can be formed in the opening 210P, and a back-side contact pad 272 can be formed on the TSV 271. For example, one or more conductive materials can be formed in the opening 210P and on the thinned back side 210b of the second substrate 210 to form the TSV 271 and the back-side contact pad 272 connected to the TSV 271. The TSV 271 can be in physical and electrical contact with the passive element 220. In some embodiments, one or more thermally conductive TSVs 273 can be formed in one or more openings 210P' to be in thermal and physical contact with one or more thermally conductive pillars 253. In some embodiments, one or more thermally conductive pads 274 can be formed on one or more thermally conductive TSVs 273. One or more thermally conductive TSVs 273 and one or more thermally conductive pads 274 may comprise one or more conductive materials that are the same as those used in TSV 271 and back contact pad 272. Alternatively, one or more thermally conductive TSVs 273 and one or more thermally conductive pads 274 may comprise one or more materials that have a higher thermal conductivity than those used in TSV 271 and back contact pad 272.

[0057] Referring to Figures 3D and 3C, a protective layer 281 with an opening 281P can be formed on the thinned back side 210b of the second substrate 210. For example, the opening 281P exposes at least a portion of the back side contact pad 272 for further electrical connection. In some embodiments, the protective layer 281 includes an opening 281P' that exposes at least a portion of one or more thermally conductive pads 274 for further heat dissipation. In some embodiments, the electronic components shown in Figure 3D (or Figure 3C) are provided, and the subsequent steps described in Figures 3E to 3G (or Figures 3D to 3G) are optional.

[0058] Referring to Figures 3E and 3D, conductive bumps 282 may be formed in opening 281P and on protective layer 281 for physical and electrical contact with back contact pads 272. Conductive bumps 282 may comprise one or more conductive materials. In some embodiments, conductive bumps 282 comprise solder material, and a reflow process is performed on the solder material to form the desired bump shape. In some embodiments, each conductive bump 282 includes a pillar portion and a cover portion covering the pillar portion, wherein the pillar portion and the cover portion are made of different materials (e.g., copper and solder or other suitable conductive materials). In some embodiments, one or more thermally conductive bumps 283 may be formed in opening 281P' and on protective layer 281 for physical and / or thermal and / or electrical contact with one or more thermally conductive pads 274. One or more thermally conductive bumps 283 may include one or more materials that are the same as those of the conductive bumps 282, or may include one or more materials that have a higher thermal conductivity than those of the conductive bumps 282.

[0059] Referring to Figures 3F to 3G and 3E, the temporary carrier plate 51 can be bonded to the conductive bumps 282 and the thermal bumps 283 via, for example, a release layer 52. A thinning process can be performed on the second side 1100b of the first substrate 1100 to form a first substrate 110 having a thinned back side 110b. For example, the first substrate 110 has a thinned thickness 110H measured between the thinned back side 110b and the first side 1100a. In some embodiments, the thinned thickness 110H is in the range of about 25 micrometers to about 250 micrometers. It should be noted that the value of the thinned thickness 110H may vary depending on the design and product requirements. After thinning, the temporary carrier plate 51 can be debonded from the conductive bumps 282 and the thermal bumps 283 by removing the release layer 52. Alternatively, the bonding and thinning process of the temporary carrier board 51 can be omitted, as long as the thickness of the first substrate 1100 can meet the requirements of the product or subsequent processes, or a combination of both.

[0060] Referring again to Figure 3G, an electronic component ED1 can be provided. In some embodiments, the aforementioned steps are performed at the wafer level, and a dicing process is performed to separate the electronic components ED1 from each other to form individual dies. In some embodiments, the aforementioned steps may involve wafer-to-wafer bonding, die-to-wafer bonding, die-to-die bonding, etc., and the electronic component ED1 may be an MMIC die, wherein the operating frequency of the MMIC may range from hundreds of megahertz to tens of gigahertz. Each electronic component ED1 may include an active component portion 10 and a passive component portion 20 stacked on and bonded to the active component portion 10. The active component portion 10 and the passive component portion 20 may be bonded together by hybrid bonding. In this way, the electronic component ED1 may have lower signal transmission loss than conventional microwave integrated circuit (MIC) dies that use bonding leads to electrically connect the active and passive components.

[0061] Active element portion 10 includes active elements 120 and may not contain passive elements. Passive element portion 20 includes passive elements 220 and may not contain active elements. In some embodiments, each of the active elements 120 is electrically coupled to one of the passive elements 220 to form functional circuitry for analog signal processing. In some embodiments, each group (or per unit cell) of active elements 120 is electrically coupled to a group of passive elements 220, wherein a group may include one or more active elements 120 and a group may include one or more passive elements 220.

[0062] Referring again to Figure 3G, during operation of electronic component ED1, since heat can be generated primarily by active component 120, a heat dissipation path 109 is provided in electronic component ED1 to effectively transfer heat from active component portion 10 to passive component portion 20 and further to external components / environment. In some embodiments, the heat dissipation path 109 in electronic component ED1 is not only highly thermally conductive but also electrically conductive. The heat dissipation path 109 may include one or more thermally conductive bumps 283, one or more thermally conductive pads 274, one or more thermally conductive TSVs 273, one or more thermally conductive pillars 253, and one or more thermally conductive features (263 and 163), wherein one or more thermally conductive features 163 may be coupled to conductive layer 145, and conductive layer 145 may be coupled to the common-emitter terminal of active component 120 (e.g., implemented as HBT) or the source terminal of active component 120 (e.g., implemented as HEMT), as described in conjunction with Figure 1E.

[0063] Figure 4 is a circuit diagram of the electronic component of Figure 3G according to some embodiments. Referring to Figures 4 and 3G, the electronic component ED1 may include an active component portion 10 and a passive component portion 20 stacked on the active component portion 10. One or more external components 40 may be coupled to the electronic component ED1 via the passive component portion 20. In RF applications, the external components 40 may include discrete semiconductor components, discrete passive components, transmission lines, DC bias terminals, etc. As described above, the active component portion 10 and the passive component portion 20 are combined to form a functional circuit / signal processing circuit (e.g., a power amplifier, low-noise amplifier, mixer, etc. for RF applications). The active component portion 10 alone (or the passive component portion 20 alone) does not form a functional circuit / signal processing circuit. In the illustrated embodiment, the active element (represented by a transistor) is disposed within the active element portion 10 and the active element portion 10 does not contain passive elements (e.g., resistors, capacitors, and inductors), while the passive element (represented by resistors, capacitors, and inductors) is disposed within the passive element portion 20 and the passive element portion 20 does not contain active elements (e.g., transistors and diodes).

[0064] In an alternative embodiment, the active element portion 10 includes an active element 120 and a few passive elements (e.g., resistors, capacitors, and / or inductors) connected to the active element 120 for certain purposes. For example, the active element portion 10 includes a few resistors (e.g., less than about 10% of the total area of ​​the passive elements) connected to the active element, wherein the resistors are configured to control the current flowing to these active elements connected to the resistors, thereby improving thermal stability. In this case, unless the active element portion 10 is combined with the passive element portion 20, the combination of the active element in the active element portion 10 and the passive elements (e.g., resistors) connected to the active element does not have the functionality of a signal processing circuit.

[0065] Figure 5 is a schematic cross-sectional view of an electronic component according to an alternative embodiment. Referring to Figures 5 and 3G, the electronic component ED2 shown in Figure 5 may be similar to the electronic component ED1 described in Figure 3G, except that the electronic component ED2 further includes an additional portion 30 inserted between the active component portion 10 and the passive component portion 20. The additional portion 30 may be electrically coupled and / or thermally coupled to the active component portion 10 and the passive component portion 20 by any suitable means (not shown separately). The additional portion 30 may be or include additional active component portions (e.g., formed by additional active component wafer 100), additional passive component portions (e.g., formed by additional passive component wafer 200), interposers, redistribution structures, the like, combinations thereof, etc.

[0066] Figures 6A to 6E are schematic cross-sectional views illustrating a method of manufacturing an electronic component having a front-to-back configuration according to some embodiments. The embodiments shown in Figures 6A to 6E are similar to those shown in Figures 3A to 3G, and therefore the same reference numerals represent the same components. Referring to Figure 6A, a passive component wafer 200-1 may be bonded to a first temporary carrier 51. The passive component wafer 200-1 may be similar to the passive component wafer 200 shown in Figure 3C, and therefore details are not repeated for simplicity. Similar to the front bonding structure 260 of the passive component wafer 200, the connection structure 260' of the passive component wafer 200-1 does not have the function of a bonding structure and is attached to the first temporary carrier 51 by, for example, a release layer (not shown). In some embodiments, a bonding structure 290 is formed over the thinned back side 210b of the second substrate 210, and a back-side interconnect structure 280 is disposed between the second substrate 210 and the bonding structure 290. For example, a bonding structure 260 formed above the first side 2100a of the second substrate 210 in the passive component wafer 200 is considered a front bonding structure, and a bonding structure 290 formed below the thinned back side 210b of the second substrate 210 opposite to the first side 2100a in the passive component wafer 200-1 is considered a back bonding structure.

[0067] Referring again to FIG. 6A, the bonding structure 290 may include a bonding dielectric layer 291 and a back-side contact pad 272 laterally covered by the bonding dielectric layer 291, wherein the back-side contact pad 272 may serve as a bonding feature 272 of the bonding structure 290. In some embodiments, a planarization process (e.g., fine CMP, polishing, etc.) is performed on the bonding structure 290 such that the lower surface 272t of the bonding feature 272 and the lower surface 291t of the bonding dielectric layer 291 are substantially coplanar with each other within a range of process variations. The lower surface 272t of the bonding feature 272 and the lower surface 291t of the bonding dielectric layer 291 may be collectively regarded as the bonding surface 290t of the bonding structure 290. One or more thermally conductive features 274 laterally covered by the bonding dielectric layer 291 may be included in the bonding structure 290. The lower surface 274t of the thermally conductive feature 274 may be substantially coplanar with the lower surface 272t of the bonding feature 272 and may be included in the bonding surface 290t. In some embodiments, a back-side interconnect structure 280, similar to interconnect structure 150, includes a dielectric layer and one or more metallization patterns (not shown separately) embedded in the dielectric layer. The metallization patterns of the back-side interconnect structure 280 can electrically couple TSV 271 and one or more thermally conductive TSV 273 to back-side contact pad 272 and one or more thermally conductive pads 274, respectively. Alternatively, the back-side interconnect structure 280 can be omitted.

[0068] Referring to Figures 6B and 6A, the passive component wafer 200-1, carried by the first temporary carrier 51, can be aligned with and then bonded to the active component wafer 100. The active component wafer 100 can be similar to the active component wafer 100 shown in Figure 3C, so details are not repeated for simplicity. In some embodiments, the bonding structure 290 of the passive component wafer 200-1 is bonded to the bonding structure 160 of the active component wafer 100. In some embodiments, the bonding dielectric layer 291 of the bonding structure 290 is fused to the bonding dielectric layer 161 of the bonding structure 160. Each of the bonding features 272 of the bonding structure 290 can be bonded to one of the bonding features 162 of the bonding structure 160 in a one-to-one manner. For example, metal bonding features 272 and 162 contact each other, and then a metal-to-metal bond is established between the bonding features 272 and 162. One or more thermally conductive features 274 in the joining structure 290 may be joined with one or more thermally conductive features 163 in the joining structure 160 in the same manner as the joining of features 272 and 162.

[0069] In some embodiments, when the bonding surfaces (160t and 290t) have been planarized and have high flatness, the bonding interface 13F of the passive component wafer 200-1 and the active component wafer 100 is substantially flat and planar. Since the thinned back side 210b of the passive component wafer 200-1 is closer to the first side (front / active side) 1100a of the active component wafer 100 than the first side (front side) 2100a of the passive component wafer 200-1, the thinned back side 210b of the passive component wafer 200-1 can be understood as the back side facing the front side of the active component wafer 100. The configuration of the bonded structure in FIG. 6B can therefore be considered as a front-to-back configuration. After the passive component wafer 200-1 is bonded to the active component wafer 100, the active component 120 in the active component wafer 100 can be electrically coupled to the passive component 220 in the passive component wafer 200-1 to form a functional circuit / signal processing circuit (e.g., a power amplifier, low noise amplifier, mixer, etc. for RF applications).

[0070] Referring to Figures 6C to 6D and 6B, a thinning process is selectively performed on the second side 1100b of the first substrate 1100 to form a first substrate 110 with a thinned back side 110b. The thinning of the active component wafer 100 can be similar to the process described in Figure 3F, so details are not repeated for simplicity. In some embodiments, after thinning the first substrate 1100, a second temporary carrier 53 is bonded to the thinned back side 110b of the first substrate 110 and a release layer is inserted between the first substrate 110 and the second temporary carrier 53. The first temporary carrier 51 can then be separated by any suitable removal technique. After separating the first temporary carrier 51, the connection structure 260' of the passive component wafer 200-1 can be exposed for further processing. In some embodiments, the bonding of the second temporary carrier 53 is selective, and as shown in Figure 6D, an electronic component without the second temporary carrier 53 is provided. The subsequent steps, including the formation and cutting of the conductive bumps as shown in Figure 6E, are selective.

[0071] Referring to Figures 6E and 6D, a protective layer 281 (similar to the protective layer 281 described in Figure 3D) is selectively formed on the connection structure 260'. In some embodiments, conductive bumps 282 (similar to the conductive bumps 282 described in Figure 3E) are formed in the openings of the protective layer 281 to make physical and electrical contact with the conductive feature 262' for further electrical connection. In some embodiments, thermally conductive bumps 283 (similar to the thermally conductive bumps 283 described in Figure 3E) are formed in the openings of the protective layer 281 to make physical and electrical contact with one or more thermally conductive features 263 for further heat dissipation. The formation of the conductive bumps 282 and / or the thermally conductive bumps 283 can be selective.

[0072] Referring again to Figure 6E and referring to Figure 3G, electronic component ED3 is provided in Figure 6E. In some embodiments, the aforementioned steps are performed at the wafer level, and a dicing process is performed to separate electronic components ED3 from each other to form individual dies. In some embodiments, the aforementioned steps may involve wafer-to-wafer bonding, die-to-wafer bonding, die-to-die bonding, etc. Electronic component ED3 may be similar to electronic component ED1 as shown in Figure 3G, except that electronic component ED3 has a front-side to back-side configuration as shown in conjunction with Figure 6B. For example, electronic component ED3 may be an MMIC die, wherein the operating frequency of the MMIC may be from hundreds of megahertz to tens of gigahertz.

[0073] Figure 7 is a schematic cross-sectional view of an electronic component according to an alternative embodiment. Referring to Figures 7, 6E, and 5, the electronic component ED4 shown in Figure 7 is similar to the electronic component ED3 described in Figure 6E, except that the electronic component ED4 further includes an additional portion 30 inserted between the active component portion 10 and the passive component portion 20. The additional portion 30 can be electrically coupled and / or thermally coupled to the active component portion 10 and the passive component portion 20 by any suitable means (not shown separately). The additional portion 30 can be similar to the additional portion 30 described in Figure 5, therefore, for simplicity, the details are not repeated.

[0074] Figures 8A to 8E are schematic cross-sectional views illustrating another method of manufacturing an electronic component having a front-to-front configuration according to some embodiments. The embodiments described in Figures 8A to 8E are similar to those described in Figures 3A to 3G and Figures 6A to 6E, and therefore the same reference numerals denote the same components. Referring to Figures 8A, 3C, and 6A, the passive component wafer 200 may be bonded to a first temporary carrier 51. The passive component wafer 200 may be similar to the passive component wafer 200 shown in Figure 3C, and therefore details are not repeated for simplicity. In some embodiments, the thinned back side 210b of the second substrate 210 is bonded to the first temporary carrier 51 by, for example, a release layer 52. The back side contact pads 272 and thermally conductive pads 274 formed on the thinned back side 210b of the second substrate 210 may be covered by the release layer 52. By forming TSV 271, back contact pad 272, thermally conductive TSV 273 and thermally conductive pad 274 in / on the second substrate 210 before the bonding process, the thermal budget of the electronic component manufacturing process can be reduced.

[0075] Referring to Figures 8B and 8A, the passive component wafer 200, carried by the first temporary carrier 51, can be aligned with and then bonded to the active component wafer 100. The active component wafer 100 can be similar to the active component wafer 100 shown in Figure 3A, therefore details are not repeated for simplicity. For example, the bonding structure 260 of the passive component wafer 200 is bonded to the bonding structure 160 of the active component wafer 100. This bonding can be similar to the process described in Figure 3A, therefore details are not repeated for simplicity.

[0076] Referring to Figures 8C to 8D and 8B, a thinning process is selectively performed on the second side 1100b of the first substrate 1100 to form a first substrate 110 with a thinned back side 110b. The thinning of the active component wafer 100 can be similar to the process described in Figure 3F, so details are not repeated for simplicity. In some embodiments, after thinning the first substrate 1110, a second temporary carrier 53 is bonded to the thinned back side 110b of the first substrate 110 and a release layer is inserted between the first substrate 110 and the second temporary carrier 53. The first temporary carrier 51 can then be separated by any suitable removal technique. After separating the first temporary carrier 51, the thinned back side 210b of the second substrate 210, the back side contact pad 272, and the thermal pad 274 of the passive component wafer 200 can be exposed for further processing. In some embodiments, the bonding of the second temporary carrier 53 is selective, and as shown in FIG8D, an electronic component without the second temporary carrier 53 is provided. Subsequent steps, including the formation and slitting of the conductive bumps as described in FIG8E, are also selective.

[0077] Referring to Figures 8E and 8D, a protective layer 281 (similar to the protective layer 281 described in Figure 3D) is selectively formed on the thinned back side 210b of the second substrate 210. In some embodiments, conductive bumps 282 (similar to the conductive bumps 282 described in Figure 3E) may be formed in / on the protective layer 281 for physical and electrical contact with the back side contact pad 272. Thermally conductive bumps 283 (similar to the thermally conductive bumps 283 described in Figure 3E) may be formed in / on the protective layer 281 for physical and / or thermal and / or electrical contact with the thermally conductive pad 274. The formation of the conductive bumps 282 and the thermally conductive bumps 283 may be selective.

[0078] Referring again to FIG. 8E and referring to FIG. 3G, electronic component ED1 can be provided in FIG. 8E. In some embodiments, the foregoing steps are performed at the wafer level, and a dicing process is performed to separate electronic component ED1 from each other to form individual dies. In some embodiments, the foregoing steps may involve wafer-to-wafer bonding, die-to-wafer bonding, die-to-die bonding, etc. Electronic component ED1 may be similar to electronic component ED1 described in FIG. 3G, therefore, for simplicity, details will not be repeated.

[0079] Based on the above, electronic components include active component portions and passive component portions stacked on and bonded to the active component portions. The active and passive component portions are manufactured separately and then bonded together to form functional circuitry / signal processing circuitry (e.g., power amplifiers, low-noise amplifiers, mixers, etc. for RF applications). This circuitry can be an MMIC (Micro-Instrument Microcontroller). The active component portions include active components, and the passive component portions include passive components; unless the active and passive component portions are bonded together, these components in either portion do not possess the required MMIC functionality. MMICs can be used in RF and millimeter-wave band applications.

[0080] Furthermore, heat dissipation paths are provided within the electronic components to transfer heat from the active component section to the passive component section and further dissipate it to external components / environment. Compared to conventional MMICs that utilize substrate vias occupying a large area of ​​the active component wafer for heat dissipation, this invention employs a novel heat dissipation and distribution architecture, thus requiring a smaller area to form active components in the active component section. Therefore, the number of active components per unit area in the active component section can be increased compared to the number of active components per unit area in conventional MMICs. Moreover, since the thermally conductive connections between active and passive components (e.g., contact EC2 in FIG. 1F) are located on the periphery to form a decentralized arrangement, the central area can be freed up for use as the main circuit wiring, thereby increasing the density of passive components in the passive component section. Based on the optimized selection of materials, the size of each active and passive component in the electronic components can be reduced.

[0081] Furthermore, by separately forming the active component portion from the active component wafer and the passive component portion from the passive component wafer, and then bonding the active and passive component portions to form a three-dimensional MMIC (3DMMIC), the active and passive component wafers can be manufactured separately and independently, without waiting for the manufacturing of one wafer to be completed before starting the manufacturing of the other, thus significantly shortening manufacturing time and increasing throughput. Moreover, by processing the wafers separately, the material and processing options for each wafer are more flexible. All the manufacturing processes described above enable cost-effective manufacturing.

[0082] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0083] 10: Active Components Section 12F, 13F: Joint interface 20: Passive Components Section 30: Additional parts 40: External components 51: Temporary carrier board / First temporary carrier board 52: Release layer 53: Second Temporary Carrier 100, 100A: Active component wafers 109: Heat dissipation path 110, 1100, 1110: First substrate 110H, 210H: Thinned thickness 110b, 210b: Thinned back side 120: Active component 120B: Base layer 120BC: Base contact / contact 120BH, 120EH: Thickness 120C1: Subcollector layer 120C2: Collector Layer 120CC: Collector Contact / Contact 120CH: Total thickness 120C': Passage Area 120D: Drainage Zone 120E: Emitter 120EC: Emitter Contact / Contact 120P: Top Cover 120S: Source Region 130, 151, 230, 251, 1300: Dielectric layer 130H: Thickness 130P, 210P, 210P', 281P, 281P', G1, G2: Opening 130t, 145t, 161t, 162t, 163t, 261t, 262t, 263t, 1300t: Top surface 140: Contact plug 140B, B1: Base-end exciton 140C, C1: Set of extreme subunits 140D: Drain Contact 140E': Common-fired extreme particle 140G: Gate electrode 140S: Source contact 140S': Common source extreme subson 145: Conductive layer 145b: Bottom surface 150, 250: Interconnection structure 152: Metallized Pattern 160, 260, 290: Joint structure 160t, 260t, 290t: Joint surfaces 161, 261, 291: Bonding dielectric layer 162, 262: Joining features 163, 263: Thermal conductivity characteristics 200, 200-1: Passive component wafers 210, 2100: Second substrate 220: Passive component 252: Wiring Layer 253: Thermal Conductor Column 260': Connection structure 262': Electrical conductivity characteristics 271:Substrate Via (TSV) 272: Back side contact pad / joint feature 272t, 274t, 291t: Lower surface 273: Thermally Conductive Substrate Via (TSV) 274: Thermally conductive pad / thermal conductivity characteristics 280: Backside interconnect structure 281: Protective layer 282: Conductive bump 283: Thermal bumps 1100a, 2100a: First side 1100b, 2100b: Second side 1200: Semiconductor epitaxial structure 1200N: Epitaxial structure neutralized by ions BC1, BC2, CC1, CC2, EC2: Contacts BP1: Joint plane CP1: Shared Platform DL1: Component Layer E1: Emitter terminal ED1, ED2, ED3, ED4: Electronic components EV1, EV2: Metal through-hole plugs LD1, LD2: Lateral dimensions R1: Active Zone R2: Sacrifice Zone

Claims

1. A method for manufacturing an electronic component, comprising: Forming a first portion from a first wafer, wherein forming the first portion includes: providing the first wafer having a first substrate; forming a semiconductor epitaxial structure on the first substrate; forming an active element from the semiconductor epitaxial structure grown on the first substrate; and forming a first bonding structure over the first substrate and electrically coupling it to the active element; forming a second portion from a second wafer, wherein the second portion is formed without an active element, and forming the second portion includes: providing the second wafer having a second substrate; forming a passive element over the second substrate; and forming a second bonding structure electrically coupled to the passive element; and forming a signal processing circuit by bonding the first portion and the second portion, wherein the active element and the passive element are electrically coupled to form the signal processing circuit by bonding the first bonding structure and the second bonding structure, wherein forming the first bonding structure in the first portion includes forming a first thermally conductive feature thermally coupled to at least a portion of the active element, forming the second portion includes forming a second thermally conductive feature through the second substrate and the second bonding structure, and the manufacturing method further includes: bonding the first thermally conductive feature to the second thermally conductive feature during bonding the first portion and the second portion.

2. A method of manufacturing an electronic component as claimed in claim 1, wherein each of the first portion and the second portion is formed as a semi-finished unit incapable of performing signal processing functions before the first portion is joined to the second portion.

3. A method for manufacturing an electronic component as claimed in claim 1, wherein the signal processing circuit is a microwave single-crystal integrated circuit.

4. A method of manufacturing an electronic component as claimed in claim 1, wherein forming the first part comprises: A dielectric layer is formed above the first substrate to embed the active element therein; A planarization process is performed on the top surface of the dielectric layer; The first bonding structure is formed above the dielectric layer; And before joining the first portion to the second portion, a planarization process is performed on the joining surface of the first joining structure, wherein the surface roughness of the joining surface of the first joining structure is less than the surface roughness of the top surface of the dielectric layer.

5. A method of manufacturing an electronic component as claimed in claim 1, wherein the first wafer is provided with a plurality of diced cells, and forming the first portion further comprises: A common platform is formed on the active element and between the active element and the first bonding structure to be electrically coupled to a portion of the active element, wherein the common platform is connected to the first bonding structure via through holes arranged in the peripheral region of each of the cut cells.

6. A method of manufacturing an electronic component as claimed in claim 1, wherein forming the first part comprises: The semiconductor epitaxial structure is formed by epitaxially growing the semiconductor epitaxial structure on the active side of the first substrate; And partially removing the semiconductor epitaxial structure to form the active element, wherein the ratio of the total surface area of ​​the active region of the active element to the total surface area of ​​the active side of the first substrate ranges from 10% to 90%.

7. A method for manufacturing the electronic component as claimed in claim 1, wherein: The first bonding structure includes a first bonding dielectric layer, and forming the first thermally conductive feature thermally coupled to at least a portion of the active element includes: forming the first thermally conductive feature in the first bonding dielectric layer that is laterally covered by the first bonding dielectric layer; and the second bonding structure includes a second bonding dielectric layer, and forming the second thermally conductive feature through the second substrate and the second bonding structure includes: forming the second thermally conductive feature in the second bonding dielectric layer that is laterally covered by the second bonding dielectric layer.

8. The method for manufacturing the electronic component as claimed in claim 1, further comprising: After the first portion is joined to the second portion, at least one of the first substrate and the second substrate is thinned.

9. The method for manufacturing the electronic component as claimed in claim 1, further comprising: A substrate through-hole is formed in the second substrate to contact the passive element between the second substrate and the second bonding structure.

10. A method of manufacturing an electronic component as claimed in claim 1, wherein the second bonding structure and the passive element are formed on opposite sides of the second substrate, and forming the second portion comprises: A substrate through-hole is formed in the second substrate to contact the passive element.

11. An electronic component manufactured by the method of manufacturing an electronic component as claimed in claim 1.

12. An electronic component, comprising: A first portion includes: a first substrate having a semiconductor epitaxial structure grown on the first substrate; an active element formed from the semiconductor epitaxial structure on the first substrate; and a first bonding structure formed over the first substrate and electrically coupled to the active element; a second portion stacked on the first portion and bonded to the first portion, the second portion not containing an active element and including: a second substrate; a passive element disposed on the second substrate; and a second bonding structure electrically coupled to the passive element, wherein the first portion is obtained from a first semiconductor wafer and the second portion is obtained from a second semiconductor wafer, and the active element in the first portion and the passive element in the second portion are electrically coupled by the bonded first bonding structure and the second bonding structure to form a signal processing circuit; and a heat dissipation path transferring heat generated from the active element to the second portion, the heat dissipation path including: a first thermally conductive feature disposed in the first bonding structure of the first portion; and a second thermally conductive feature disposed in the second portion and bonded to the first thermally conductive feature, the second thermally conductive feature passing through the second bonding structure and the second substrate.

13. The electronic component as claimed in claim 12, wherein the signal processing circuitry comprises a microwave single-crystal integrated circuit.

14. The electronic component of claim 12, wherein the first semiconductor wafer comprises a plurality of diced cells, the first portion comprising a common platform located above the active element and between the active element and the first bonding structure, the common platform electrically coupled to a portion of the active element being connected to the first bonding structure via vias disposed in a peripheral region of each of the diced cells.

15. The electronic component as claimed in claim 12, wherein the second portion does not contain an epitaxial layer.

16. An electronic component, comprising: The signal processing circuit includes an active element in the first part that is electrically coupled to a passive element in the second part; The first portion includes: a first substrate having a semiconductor epitaxial layer on a front surface of the first substrate; an active element made of the semiconductor epitaxial layer and disposed on the front surface of the first substrate; and a first bonding structure disposed above and electrically coupled to the active element; and a second portion stacked on and bonded to the first portion, the second portion not containing an active element and including: a second substrate; the passive element disposed on a front side of the second substrate; and a second bonding structure electrically coupled to the passive element and bonded to the first bonding structure to electrically connect with the active element and the passive element to form the signal processing circuit; and a heat dissipation path transferring heat generated from the active element to the second portion, the heat dissipation path including: a first thermally conductive feature disposed in the first bonding structure of the first portion; and a second thermally conductive feature disposed in the second portion and bonded to the first thermally conductive feature, the second thermally conductive feature passing through the second bonding structure and the second substrate.

17. The electronic component as claimed in claim 16, wherein the first portion further comprises: A dielectric layer is applied over the first substrate and covers the active element, wherein the top surface of the dielectric layer is rougher than the bonding surface of the first bonding structure of the first portion.

18. The electronic component as claimed in claim 16, wherein: The first bonding structure of the first portion includes a first bonding dielectric layer and a first bonding feature in the first bonding dielectric layer, and the second bonding structure of the second portion includes a second bonding dielectric layer and a second bonding feature in the second bonding dielectric layer, wherein the first bonding dielectric layer is fused with the second bonding dielectric layer, and the first bonding feature is bonded with the second bonding feature.

19. The electronic component as claimed in claim 16, wherein the second portion does not contain an epitaxial layer.

20. The electronic component as claimed in claim 16, wherein: The first bonding structure includes a first bonding dielectric layer, the first thermally conductive feature being laterally covered by the first bonding dielectric layer, and the second bonding structure includes a second bonding dielectric layer, the second thermally conductive feature being laterally covered by the second bonding dielectric layer.

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