Method of processing a semiconductor substrate and apparatus for conducting dry development of EUV resist

Abstract

Dry development of photoresist can be used, for example, to form patterned masks in high-resolution patterning. Dry development can be advantageously achieved by a semiconductor substrate processing method comprising: providing photopatterned photoresist on a substrate layer of the semiconductor substrate in a processing chamber; and subjecting the photopatterned photoresist to dry development, wherein the dry development process removes exposed or unexposed portions of the photoresist, the dry development process including exposure to a chemical compound to form a photoresist mask. The photoresist can be an EUV-sensitive thin-film EUV photoresist containing organometallic or organometallic oxides.

Description

Technical Field

[0001] The present invention relates to dry development of photoresist. Prior Art

[0002] In semiconductor manufacturing, thin film patterning is often a crucial step in semiconductor processing. Patterning involves lithography. In conventional lithography techniques (e.g., 193 nm lithography), a pattern is created by emitting photons from a photon source onto a mask and imprinting the pattern onto a photosensitive photoresist. This triggers a chemical reaction in the photoresist that, after development, removes portions of the photoresist to form the pattern.

[0003] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include the 22 nm, 16 nm, and other nodes. At the 16 nm node, for example, the width of a typical via or line in a damascene structure is typically no greater than approximately 30 nm. The scaling of features in advanced semiconductor integrated circuits (ICs) and other devices is driving the need for improved lithography resolution. Summary of the Invention

[0004] Dry development of photoresist can be used, for example, to form a patterned mask in high-resolution patterning. According to certain aspects of this disclosure, dry development can be advantageously achieved by a method for processing a semiconductor substrate, the method comprising: providing a photopatterned photoresist on a substrate layer on a semiconductor substrate in a processing chamber; and dry developing the photopatterned photoresist by removing exposed or unexposed portions of the photoresist through a dry development process, the dry development process comprising exposure to a chemical compound to form a photoresist mask. In certain embodiments, the photoresist can be an EUV-sensitive EUV photoresist containing an organometallic or organometallic oxide thin film.

[0005] In certain embodiments of the present disclosure, a suitable photoresist may be an EUV photoresist vapor-deposited onto a substrate layer. In other embodiments, a suitable photoresist may be an EUV photoresist spin-coated onto the substrate layer. In certain embodiments, the EUV photoresist may be an organotin oxide. In certain embodiments, the dry development process may include a plasma. In other embodiments, the dry development process may be a thermal process without plasma.

[0006] In some embodiments, the dry development process may involve exposure to a compound comprising RxZy, where R = B, Al, Si, C, S, SO and x>0, and Z = Cl, H, Br, F, CH4 and y>0, at an appropriate flow rate, pressure, and temperature for an appropriate time.

[0007] In certain embodiments, the photo-patterned EUV resist is a 10-20 nm thick film containing an organotin oxide, which is deposited based on a vapor phase reaction of an organotin precursor, isopropyl(tris)(dimethylamino)tin, with water vapor, subjected to an EUV exposure dose and a post-exposure bake, and the dry development process involves a non-plasma thermal exposure of the photo-patterned EUV resist at 120° C., 10 mT, 500 sccm BCl 3 for 30 seconds.

[0008] In some embodiments, the process further involves: after performing dry development to form a photoresist mask, etching the substrate layer using the photoresist mask.

[0009] In some embodiments, the photoresist is sensitive to a radiation source selected from the group consisting of DUV, EUV, X-ray, and electron beam radiation.

[0010] In other aspects, an apparatus for performing dry development of patterned photoresist is provided. Such an apparatus may include a vacuum processing chamber having a substrate (e.g., wafer) support; a vacuum line; a dry development chemical gas line; one or more heaters for substrate temperature control; and a controller programmed with instructions for processing a semiconductor substrate. The instructions may include code for: providing patterned photoresist on a substrate layer on the semiconductor substrate to the vacuum processing chamber; and removing exposed or unexposed portions of the patterned photoresist by a dry development process, wherein the dry development process includes exposure to a chemical compound to form a photoresist mask.

[0011] In some embodiments, the interior of the processing chamber of the apparatus may be coated with a corrosion inhibitor.

[0012] In some embodiments, the controller can be programmed with instructions for the dry development process, wherein the dry development process includes a plasma. In other embodiments, the controller can be programmed with instructions for the dry development process, wherein the dry development process is a thermal process without plasma.

[0013] In some embodiments, the controller can be programmed with instructions for the dry development process, wherein the dry development process involves exposure to a compound comprising RxZy, where R = B, Al, Si, C, S, SO and x>0, and Z = Cl, H, Br, F, CH4 and y>0, at an appropriate flow rate, pressure, and temperature for an appropriate time.

[0014] In certain embodiments, the controller may be programmed with instructions for the dry development process, wherein the photo-patterned EUV photoresist is a 10-20 nm thick film containing an organotin oxide, which is deposited based on a vapor phase reaction of an organotin precursor, isopropyl(tris)(dimethylamino)tin, with water vapor, subjected to an EUV exposure dose, and a post-exposure bake, and the dry development process involves a non-plasma thermal exposure of the photo-patterned EUV photoresist at 120° C., 10 mT, and 500 sccm BCl for 30 seconds.

[0015] In some embodiments, the controller may be programmed wherein the process further involves etching the substrate layer using the photoresist mask after dry developing to form the photoresist mask. Simple diagram description

[0016] 1A-1B and 2 illustrate the processing stages and results of negative tone dry development, according to certain embodiments of the present disclosure.

[0017] FIG3 depicts a schematic diagram of an embodiment of a processing station apparatus suitable for implementing the described dry development embodiment.

[0018] FIG. 4 depicts an embodiment of a multi-station processing tool suitable for performing the described dry development embodiment.

[0019] FIG5 schematically illustrates a cross-sectional view of an inductively coupled plasma apparatus suitable for implementing certain embodiments or aspects of the present invention.

[0020] FIG. 6 depicts a semiconductor processing cluster tool architecture having a vacuum integrated deposition and patterning module coupled to a vacuum transfer module suitable for performing the processes described herein. Implementation Method

[0021] The present disclosure generally relates to the field of semiconductor processing. In particular aspects, the present disclosure relates to processes and apparatus for dry development of photoresists (e.g., EUV, DUV, X-ray, or e-beam sensitive photoresists containing metals and / or metal oxides), for example, to form patterned masks.

[0022] Reference will be made in detail to specific embodiments of the present disclosure. Examples of specific embodiments are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with these specific embodiments, it should be understood that the present disclosure is not limited to these specific embodiments. Rather, it is intended to encompass permutations, modifications, and equivalents within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known processing operations have not been described in detail to avoid unnecessarily obscuring the present disclosure.

[0023] Extreme ultraviolet (EUV) lithography expands lithography technology by moving to smaller imaging source wavelengths than are achievable with conventional photolithography methods. EUV light sources with wavelengths of approximately 10-20 nm, or 11-14 nm (e.g., 13.5 nm), can be used in cutting-edge lithography tools (also known as scanners). EUV radiation is strongly absorbed by many solid and fluid materials, including quartz and water vapor, and therefore operates in a vacuum. Similar good performance can be achieved using other forms of radiation, including DUV, X-ray, or electron beam radiation. While the description herein primarily refers to EUV as a photoresist illumination source, it should be understood that other forms of such radiation are also contemplated in alternative embodiments.

[0024] EUV lithography uses an EUV photoresist that is patterned to form a mask for etching underlying layers. The EUV photoresist can be a polymer-based chemically amplified photoresist (CAR), produced by liquid-based spin-coating techniques. An alternative to CARs is a directly photopatternable metal oxide-containing film, such as those available from Inpria Corporation, Corvallis, OR, and described in, for example, U.S. Patent Publications US 2017 / 0102612, US 2016 / 021660, and US 2016 / 0116839, which are incorporated herein by reference at least for their disclosure of photopatternable metal oxide-containing films. Such films can be produced by spin-coating techniques or dry vapor deposition. Films containing metal oxides can be patterned directly by EUV exposure in a vacuum environment (i.e., without the use of a separate photoresist), providing sub-30 nm patterning resolution, as described, for example, in U.S. Patent No. 9,996,004, entitled “EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS,” issued on June 12, 2018, and / or PCT / US19 / 31618, entitled “METHODS FOR MAKING EUV PATTERNABLE HARD MASKS,” filed on May 9, 2019, and / or PCT / US19 / 31618, entitled “METHODS FOR MAKING EUV PATTERNABLE HARD MASKS,” filed on November 11, 2019, and / or PCT / US19 / 31618, entitled “METHODS FOR MAKING HARD MASKS USEFUL IN NEXT-GENERATION TECHNOLOGY.” PCT / US2019 / 060742, entitled "LITHOGRAPHY," discloses at least the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV photoresist masks, and is incorporated herein by reference. Typically, patterning involves exposing EUV photoresist to EUV radiation to form a photopattern in the photoresist, followed by development to remove a portion of the photoresist according to the photopattern to form a mask.

[0025] Directly photopatternable EUV photoresists can be composed of or contain metals and / or metal oxides mixed within an organic component. Metals / metal oxides are particularly promising because they enhance EUV photon absorption and generate secondary electrons and / or exhibit increased etch selectivity toward underlying film stacks and device layers. To date, developing these photoresists has been performed using wet (solvent) methods, which require moving the wafer onto a track, where it is exposed to the developer, dried, and baked. This wet development step not only limits throughput but can also lead to line collapse and / or delamination due to surface tension effects.

[0026] In one embodiment of the present disclosure, an EUV-sensitive metal oxide-containing film (e.g., an organotin oxide) is vapor-deposited onto a semiconductor substrate. The metal oxide-containing film is then directly patterned by EUV exposure in a vacuum environment, and the pattern is developed to form a metal oxide-containing mask. As described herein, development of organometallic oxide-containing, organometallic-containing, or other directly photopatternable EUV photoresist films is performed using a dry process.

[0027] The presently disclosed methods and apparatus provide general approaches that can be applied to a variety of specific implementations. Embodiments of the present disclosure provide processes and apparatus for dry development of metal- and / or metal oxide-containing photoresists for EUV photopatterning, using chemical compounds as part of the EUV photoresist mask formation process. Other embodiments include combining all dry steps of film formation by vapor deposition, (EUV) lithographic photopatterning, and dry development. Dry development can improve performance (e.g., by preventing line collapse and delamination caused by surface tension in wet development) and increase throughput (e.g., by avoiding wet development rails). Other advantages may include eliminating the use of organic solvent developers, reducing sensitivity to adhesion issues, and eliminating solubility-based limitations.

[0028] According to certain embodiments, dry methods are provided for developing EUV-sensitive photoresists containing metals and / or metal oxides. One embodiment is suitable for dry development of Sn and SnOx (tin oxide)-based photoresists containing some C, H, and O (and possibly additional components such as F). In various embodiments, the metal oxide-containing film can be a photosensitive organometallic oxide film, such as an organotin oxide, for example, an alkyltin oxide (oxide / hydroxide) RSnOxOH(3-x). Effective compositions include those in which the alkyl substituent is a tert-butyl or isopropyl substituent, wherein the carbon atom bonded to the tin atom is bonded to three or two other carbon atoms (respectively). Upon exposure to EUV light, such substituents appear to undergo more efficient cleavage, resulting in changes that allow pattern development. In various embodiments, EUV exposure results in the loss of the alkyl substituent, forming new Sn-O-Sn crosslinks, which may occur after the EUV exposure step, for example, during a post-exposure bake step where the film may be exposed to ambient oxygen and / or moisture.

[0029] Development can be performed using a mild plasma (high voltage, low power) or thermal process while flowing a dry developer chemical (e.g., BCl3 or other Lewis acid). According to certain embodiments, BCl3 can quickly remove unexposed material, leaving behind an exposed film pattern that can be transferred to underlying layers by a plasma-based etch process (e.g., conventional etch processes).

[0030] According to the present disclosure, in a dry development process using a mild plasma or thermal treatment (e.g., >5 mT (e.g., >15 mT), <1000 W (e.g., <500 W), transformer-coupled plasma (TCP) (in other embodiments, CCP, ICP, or downstream plasma may be used), 0-300° C. (e.g., 30-120° C.), 100-1000 sccm (e.g., about 500 After photopatterning in an EUV scanner using dry developer chemicals (e.g., 10-600 seconds) at 200 sccm for 1 to 3000 seconds, the wafer can proceed directly to a dry develop / etch chamber, bypassing the material and production costs associated with wet development on a rail machine. Alternatively, a post-exposure bake can be performed in the develop chamber or another chamber, during which the exposed areas undergo further crosslinking to form a denser SnO2-like network. Dry processing offers greater tunability, providing improved critical dimension (CD) control, and residue removal.

[0031] By employing a non-plasma thermal approach, productivity can be significantly improved because multiple wafers can be developed simultaneously in batches within a low-cost thermal vacuum chamber / furnace. A suitable chamber can include vacuum lines, lines for dry developing chemicals (e.g., BCl3), and heaters for temperature control. Furthermore, because the process is thermal, the chamber interior can be covered with corrosion-resistant films, such as organic polymers (e.g., polytetrafluoroethylene (PTFE), such as Teflon™) or inorganic coatings, without the risk of removal by plasma exposure.

[0032] In various embodiments, dry development of photoresists containing some metal, metal oxide, and organic components can be performed by plasma or thermal, plasma (including possible photoactivation (i.e., lamp-heated, such as UV lamp-heated), or a combination of methods, while flowing a dry developer gas comprising a compound of the formula RxZy, where R = B, Al, Si, C, S, SO and x>0, and Z = Cl, H, Br, F, CH4 and y>0. Dry development can produce positive or negative working, where the RxZy species selectively removes unexposed or exposed material, leaving the exposed or unexposed complement as a mask.

[0033] This process has been used for EUV photoresist compositions based on organotin oxides and is applicable to commercially available spin-coatable formulations (e.g., those available from Inpria Corporation) as well as formulations applied using dry vacuum deposition techniques (e.g., formulations in the aforementioned applicant's prior applications). Negative-tone dry development has been achieved by selective dry development (removal) of non-EUV-exposed areas by exposing them to a flow of BCl₃ without igniting the plasma. One specific example of a dry development process involves an EUV-sensitive photoresist film (e.g., 10-20 nm thick) containing an organotin oxide. The film is deposited based on the vapor phase reaction of the organotin precursor isopropyl(tris)(dimethylamino)tin with water vapor, subjected to EUV exposure and post-exposure baking, and then dry developed using a non-plasma thermal treatment at 120°C, 10 mT, and 500 sccm BCl₃ for 30 seconds.

[0034] 1A-1B and 2 illustrate negative-tone dry development according to certain embodiments of the present disclosure. As shown in FIG1A , a wafer 100 includes a substrate 102 (e.g., Si), a layer to be etched 104 disposed on the substrate (e.g., an ashing hard mask (e.g., silicon oxycarbide (SOC)), or other materials (e.g., silicon, silicon oxide, silicon nitride, etc.); in other embodiments, a layer stack), and a photo-patterned EUV photoresist film 106 (e.g., a 10-20 nm thick layer containing organic tin oxide disposed on the layer to be etched). After photo-patterning and an optional bake in the aforementioned EUV scanner, the wafer 100 can be provided to an etching chamber. As shown in FIG1B , non-EUV-exposed regions 106a (darker areas in the figure) of the photoresist 106 can be removed during the dry development process by exposing the photoresist 106 to a flow of dry developer chemicals (e.g., BCl3) without igniting the plasma. Thereafter, the developed photoresist 106 may be used as a mask to etch the layer 104 to provide the structure shown in the figure. Alternative Embodiments

[0035] EUV-sensitive photoresists containing metals and metal oxides, such as those mentioned above, are being used in EUV patterning due to their enhanced absorption of EUV photons. However, challenges include high line widths and line-edge roughness, as well as residue issues. These two challenges can be largely attributed to the random nature and non-optimal Gaussian distribution of light, resulting in partially or fully exposed material in areas of the photoresist that should remain unexposed, and vice versa.

[0036] Wet development is highly selective and exhibits a well-defined on / off behavior, preventing wet development from removing partially or completely misexposed areas. This leaves residual residues after wet development, resulting in slag and high line-edge and line-width roughness. Interestingly, dry development, due to its tunability in etch rate and selectivity via multiple control knobs (e.g., time, temperature, pressure, and gas / flow), can be further applied to slag removal and smoothing of metal-containing photoresist lines by removing these partially exposed residues. equipment

[0037] As described above, a suitable processing chamber for implementing the non-plasma thermal embodiments of the present disclosure can be comprised of a vacuum processing chamber with a substrate (e.g., wafer) support, a vacuum line, a BCl3 line, and one or more heaters for temperature control. The interior of the non-plasma thermal processing chamber can be coated with a corrosion-resistant organic polymer (e.g., polytetrafluoroethylene (PTFE), such as Teflon™) without the risk of removal by plasma exposure.

[0038] FIG3 schematically illustrates an embodiment of a processing station 300 having a processing chamber body 302 for maintaining a low-pressure environment suitable for performing the dry development embodiments described herein. Multiple processing stations 300 may be included in a common low-pressure processing tool environment. For example, FIG4 illustrates an embodiment of a multi-station processing tool 400, such as the VECTOR® processing tool available from Lam Research Corporation, Fremont, CA. In some embodiments, one or more hardware parameters of the processing station 300 (including those discussed in detail below) may be programmatically adjusted by one or more computer controllers 350.

[0039] Processing stations can be configured as modules within a cluster tool. Figure 6 depicts a semiconductor processing cluster tool architecture with a vacuum-integrated deposition and patterning module suitable for performing the embodiments described herein. Such a cluster processing tool architecture can include photoresist deposition, photoresist exposure (EUV scanner), photoresist dry development, and etching modules, as described above and further described below with reference to Figures 5 and 6.

[0040] In some embodiments, certain processing functions, such as dry development and etching, can be performed sequentially in the same module. Embodiments of the present disclosure relate to methods and apparatus for receiving a wafer (including a photo-patterned EUV photoresist film layer disposed over a layer or layer stack to be etched) into a dry development / etch chamber after photo-patterning in an EUV scanner; dry-developing the photo-patterned EUV photoresist film layer; and then etching underlying layers using the patterned EUV photoresist film as a mask, as described herein.

[0041] Returning to FIG. 3 , process station 300 is in fluid communication with a reactant delivery system 301a for delivering process gases to a distribution showerhead 306. Reactant delivery system 301a optionally includes a mixing vessel 304 for mixing and / or conditioning process gases for delivery to showerhead 306. One or more mixing vessel inlet valves 320 can control the introduction of process gases into mixing vessel 304. When plasma exposure is used, plasma can also be delivered to showerhead 306 or generated within process station 300. As discussed above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0042] FIG3 includes an optional vaporization point 303 for vaporizing liquid reactants to be supplied to a mixing vessel 304. In some embodiments, a liquid flow controller (LFC) may be positioned upstream of vaporization point 303 to control the mass flow of the liquid being vaporized and delivered to processing station 300. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The LFC's plunger valve may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller (electrically connected to the MFM).

[0043] The showerhead 306 distributes the process gas toward the substrate 312. In the embodiment shown in FIG3 , the substrate 312 is positioned below the showerhead 306 and is shown resting on a pedestal 308. The showerhead 306 can have any suitable shape and can have any suitable number and configuration of ports for distributing the process gas to the substrate 312.

[0044] In some embodiments, the pedestal 308 can be raised or lowered to expose the substrate 312 to the volume between the substrate 312 and the showerhead 306. It should be understood that in some embodiments, the pedestal height can be programmatically adjusted by an appropriate computer controller 350.

[0045] In some embodiments, the susceptor 308 can be temperature controlled by a heater 310. In some embodiments, as described in the disclosed embodiments, the susceptor 308 can be heated to a temperature greater than 0°C and up to 300°C or higher, such as 50-120°C, for example, about 65-80°C, during the non-plasma thermal exposure of the photo-patterned photoresist to a dry developer chemistry (e.g., BCl3).

[0046] Additionally, in some embodiments, pressure control of the processing station 300 can be provided by a butterfly valve 318. As shown in the embodiment of FIG3 , the butterfly valve 318 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the processing station 300 can also be adjusted by varying the flow rate of one or more gases introduced into the processing station 300.

[0047] In some embodiments, the position of the showerhead 306 can be adjusted relative to the pedestal 308 to change the volume between the substrate 312 and the showerhead 306. Furthermore, it should be understood that the vertical position of the pedestal 308 and / or showerhead 306 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 308 can include a rotation axis for rotating the position of the substrate 312. It should be understood that in some embodiments, one or more of these exemplary adjustments can be programmatically implemented by one or more suitable computer controllers 350.

[0048] When plasma may be used, such as in mild plasma-based dry development embodiments and / or etching operations performed in the same chamber, the showerhead 306 and pedestal 308 are electrically connected to a radio frequency (RF) power source 314 and matching network 316 for providing energy to the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 314 and matching network 316 can be operated at any appropriate power to form a plasma with a desired radical species composition. An example of a suitable power is up to approximately 500 W.

[0049] In some embodiments, instructions for controller 350 may be provided via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some examples, the process recipe phases may be arranged sequentially so that all instructions for a process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a recipe phase may include instructions for setting the flow rate of a dry developer chemical reactant gas (e.g., BCl3) and time delay instructions for the recipe phase. In some embodiments, controller 350 may include any of the features described below with respect to system controller 450 in FIG. 4 .

[0050] As described above, one or more processing stations may be included in a multi-station processing tool. Figure 4 shows a schematic diagram of an embodiment of a multi-station processing tool 400 having an inbound load chamber 402 and an outbound load chamber 404, either or both of which may include a remote plasma source. A robot 406 operating at atmospheric pressure is used to move wafers from a wafer boat (loaded via cassette 408) into the inbound load chamber 402 via an atmospheric port 410. The robot 406 places the wafer on a pedestal 412 in the inbound load chamber 402, closes the atmospheric port 410, and evacuates the load chamber. In the case where the inbound load chamber 402 includes a remote plasma source, the wafer can be exposed to a remote plasma treatment in the load chamber before being introduced into a processing chamber 414 to treat the silicon nitride surface. Furthermore, the wafer may be heated in the inbound load chamber 402, for example, to remove moisture and adsorbed gases. Next, a chamber transfer port 416 leading to the processing chamber 414 is opened, and another robot (not shown) places the wafer in the reactor and on a susceptor at the first station shown in the reactor for processing. Although the embodiment depicted in FIG4 includes a load chamber, it should be understood that in some embodiments, the wafer can be directly placed into the processing station.

[0051] In the embodiment shown in FIG. 4 , the depicted processing chamber 414 includes four processing stations, numbered 1 through 4. Each processing station has a heated susceptor (shown as 418 in processing station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station may have different or multiple purposes. For example, in some embodiments, a processing station may be switchable between dry development and etching processing modes. Additionally or alternatively, in some embodiments, the processing chamber 414 may include one or more matched pairs of dry development and etching processing stations. While the depicted processing chamber 414 includes four processing stations, it should be understood that a processing chamber according to the present disclosure may have any suitable number of processing stations. For example, in some embodiments, the processing chamber may have five or more processing stations, while in other embodiments, the processing chamber may have three or fewer processing stations.

[0052] FIG4 depicts an embodiment of a wafer handling system 490 for transferring wafers within the processing chamber 414. In some embodiments, the wafer handling system 490 can transfer wafers between various processing stations and / or between a processing station and a load chamber. It should be understood that any suitable wafer handling system can be employed. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG4 also depicts an embodiment of a system controller 450 for controlling processing conditions and hardware states of the processing tool 400. The system controller 450 may include one or more memory devices 456, one or more mass storage devices 454, and one or more processors 452. The processor 452 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0053] In some embodiments, the system controller 450 controls all activities of the processing tool 400. The system controller 450 executes system control software 458, which is stored in the mass storage device 454, loaded into the memory device 456, and executed on the processor 452. Alternatively, the control logic may be hard-coded in the controller 450. Application-specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), and the like may be used for these purposes. In the following discussion, in any case where the terms "software" or "code" are used, functionally similar hard-coded logic may be used as appropriate. The system control software 458 may include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or processing station pressures, chamber and / or processing station temperatures, wafer temperatures, target power levels, RF power levels, substrate pedestal, chuck, and / or holder positions, and other parameters of the specific process performed by the processing tool 400. The system control software 458 can be configured in any suitable manner. For example, various process tool component subroutines or control objects can be written to control the operation of the process tool components used to perform various process tool processes. The system control software 458 can be coded in any suitable computer-readable programming language.

[0054] In some embodiments, the system control software 458 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on the mass storage device 454 and / or the memory device 456 associated with the system controller 450 may be used. Examples of programs or program segments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0055] The substrate positioning program may include program code for processing tool components to load a substrate onto the pedestal 418 and to control the distance between the substrate and other parts of the processing tool 400.

[0056] The process gas control program may include code for controlling gas composition (e.g., BCl3 gas as described herein) and flow rate, and optionally for flowing gas into one or more process stations to stabilize the process station pressure prior to deposition. The pressure control program may include code for controlling the pressure within the process station by adjusting, for example, a throttle valve in the exhaust system of the process station, the flow of gas into the process station, etc.

[0057] The heater control program may include code for controlling the current to a heating unit that heats the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (eg, helium) to the substrate.

[0058] According to embodiments herein, a plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations.

[0059] According to embodiments herein, a pressure control program may include code for maintaining pressure within a reaction chamber.

[0060] In some embodiments, a user interface may be provided in communication with the system controller 450. The user interface may include a display screen, a graphical software display of device and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0061] In some embodiments, the parameters adjusted by system controller 450 may be related to processing conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of a recipe, which may be input using a user interface.

[0062] Signals used to monitor the process can be provided from various process tool sensors via analog and / or digital input connections of the system controller 450. Signals used to control the process can be output on analog and digital output connections of the process tool 400. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain process conditions.

[0063] The system controller 450 may provide program instructions for implementing the deposition process described above. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. According to various embodiments described herein, the instructions may control parameters to operate dry development and / or etching processes.

[0064] Typically, the system controller 450 will include one or more memory devices and one or more processors for executing instructions so that the apparatus will perform methods according to the disclosed embodiments. A machine-readable medium may be coupled to the system controller 450, the machine-readable medium including instructions for controlling processing operations according to the disclosed embodiments.

[0065] In some embodiments, system controller 450 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for performing processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics that control their operation before, during, and after processing of semiconductor wafers or substrates. The electronics may be referred to as a "controller," which may control various components or sub-components of one or more systems. Depending on the processing conditions and / or system type, system controller 450 may be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positioning and handling settings, wafer transfer into and out of tools connected to or interfaced with the particular system, other transfer tools, and / or load chambers.

[0066] Broadly speaking, system controller 450 can be defined as an electronic component having various integrated circuits, logic, memory, and / or software for receiving commands, issuing commands, controlling operations, enabling cleaning operations, performing endpoint measurements, and similar functions. The integrated circuits may include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be communicated to system controller 450 in the form of various individual configurations (or program files) that define operating parameters for performing specific processes on or with a semiconductor wafer, or with the system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to perform one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies on a wafer.

[0067] In some embodiments, system controller 450 may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, system controller 450 may be in the "cloud" or in whole or in part on a mainframe computer system in a wafer fab, allowing remote control of wafer processing. The computer may enable remote control of the system to monitor the current process of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance metrics across multiple manufacturing operations, change parameters of the current process, set a processing step after the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network, such as a local area network (LAN) or the Internet. The remote computer may include a user interface that enables the input or programming of parameters and / or settings, which are then transferred from the remote computer to the system. In some examples, system controller 450 receives instructions in the form of data specifying a plurality of parameters for each of the processing steps to be performed during one or more operating sessions. It should be understood that these parameters can be specific to the type of processing to be performed, as well as the type of tool to which system controller 450 is coupled or controlled. Thus, as described above, system controller 450 can be distributed, for example by including one or more independent controllers connected together via a network and working toward a common goal, such as the processing and control described herein. An example of a distributed controller for such a goal is one or more integrated circuits in a chamber communicating with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), which together control the processing in the chamber.

[0068] Without limitation, exemplary systems may include plasma etch chambers or modules, deposition chambers or modules, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, dry developer chambers or modules, and any other semiconductor processing system related to or used in the processing and / or manufacture of semiconductor wafers.

[0069] As described above, depending on one or more process steps to be performed by the tool, the system controller 450 may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or material handling tools used to move wafer containers into and out of tool locations and / or load ports in a semiconductor manufacturing facility.

[0070] An inductively coupled plasma (ICP) reactor is now described, which may be suitable for use in etching operations in certain embodiments. While an ICP reactor is described herein, it should be understood that a capacitively coupled plasma reactor may also be used in certain embodiments.

[0071] FIG5 schematically illustrates a cross-sectional view of an inductively coupled plasma apparatus 500 suitable for performing certain embodiments or aspects of embodiments (e.g., dry development and / or etching). An example of such an apparatus is a Kiyo® reactor manufactured by Lam Research Corp., Fremont, CA. Inductively coupled plasma apparatus 500 includes a processing chamber 524 structurally defined by chamber walls 501 and a window 511. Chamber walls 501 can be made of stainless steel or aluminum. Window 511 can be made of quartz or other dielectric materials. An optional internal plasma grid 550 divides the processing chamber into an upper subchamber 502 and a lower subchamber 503. In most embodiments, plasma grid 550 can be removed, thereby utilizing the chamber space formed by subchambers 502 and 503. A chuck 517 is located within lower subchamber 503 near the bottom inner surface. Chuck 517 is used to receive and hold semiconductor wafer 519 for performing etching and deposition processes thereon. Chuck 517 can be an electrostatic chuck for supporting wafer 519 (when present). In some embodiments, an edge ring (not shown) surrounds chuck 517, and the upper surface of the edge ring and the upper surface of wafer 519 (when present on chuck 517) are approximately planar. Chuck 517 also includes electrostatic electrodes for clamping and unclamping wafer 519. To this end, filters and DC clamping power supplies (not shown) may be provided. Other control systems may also be provided to lift wafer 519 off chuck 517. Chuck 517 can be energized using RF power supply 523. RF power supply 523 is connected to matching circuit 521 via connection 527. Matching circuit 521 is connected to chuck 517 via connection 525. In this manner, RF power supply 523 is connected to chuck 517. In various embodiments, the bias power supply of the electrostatic chuck can be set to approximately 50 V, or to a different bias power supply depending on the process performed according to the disclosed embodiments. For example, the bias power supply can be between approximately 20 V and approximately 100 V, or between approximately 30 V and approximately 150 V.

[0072] The components for plasma generation include a coil 533 positioned above the window 511. In some embodiments, the coil is not used in the disclosed embodiments. The coil 533 is made of a conductive material and includes at least one full turn. The example of coil 533 shown in FIG5 includes three turns. The cross-section of the coil 533 is shown with symbols, where the coil with an "X" extends into the page and the coil with a "●" extends out of the page. The components for plasma generation also include an RF power supply 541 for supplying RF power to the coil 533. Generally, the RF power supply 541 is connected to a matching circuit 539 via a connection 545. The matching circuit 539 is connected to the coil 533 via a connection 543. In this manner, the RF power supply 541 is connected to the coil 533. An optional Faraday shield 549a is positioned between the coil 533 and the window 511. The Faraday shield 549a can be spaced apart from the coil 533. In some embodiments, the Faraday shield 549a is positioned immediately above the window 511. In some embodiments, the Faraday shield 549b is positioned between the window 511 and the chuck 517. In some embodiments, the Faraday shield 549b and the coil 533 are not spaced apart. For example, the Faraday shield 549b may be positioned directly below the window 511 without a gap. The coil 533, the Faraday shield 549a, and the window 511 are each arranged substantially parallel to one another. The Faraday shield 549a prevents metal or other species from depositing on the window 511 of the processing chamber 524.

[0073] Processing gases may flow into the processing chamber via one or more main gas inlets 560 and / or one or more side gas inlets 570 located in the upper sub-chamber 502. Similarly, although not explicitly shown, similar gas inlets may be used to supply processing gases to a capacitively coupled plasma processing chamber. A vacuum pump (e.g., a single or dual mechanical dry pump and / or a turbomolecular pump) 540 may be used to pump processing gases from the processing chamber 524 and maintain pressure within the processing chamber 524. For example, during an ALD purge operation, the vacuum pump may be used to evacuate the lower sub-chamber 503. A valve-controlled conduit may be used to fluidically connect the vacuum pump to the processing chamber 524 to selectively control the application of the vacuum environment provided by the vacuum pump. During plasma processing operations, this may be achieved by employing a closed-loop controlled flow limiting device, such as a throttle valve (not shown) or a pendulum valve (not shown). Likewise, fluid connections to the vacuum pump and valve control of a capacitively coupled plasma processing chamber may be employed.

[0074] During operation of the apparatus 500, one or more process gases may be supplied through gas inlets 560 and / or 570. In some embodiments, process gases may be supplied only through the main gas inlet 560 or only through the side gas inlet 570. In some cases, the gas inlets shown may be replaced with, for example, more complex gas inlets, one or more showerheads. The Faraday shield 549a and / or the optional grid 550 may include internal channels and holes that allow process gases to be delivered to the processing chamber 524. Either or both the Faraday shield 549a and the optional grid 550 may function as showerheads to deliver process gases. In some embodiments, a liquid vaporization and delivery system may be located upstream of the processing chamber 524 so that once a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the processing chamber 524 through the gas inlets 560 and / or 570.

[0075] RF power is supplied from RF power source 541 to coil 533, causing RF current to flow through coil 533. The RF current flowing through coil 533 generates an electromagnetic field around coil 533. This electromagnetic field induces a current within upper sub-chamber 502. The generated ions and radicals interact physically and chemically with wafer 519, etching features of wafer 519 and selectively depositing films on wafer 519.

[0076] If a plasma gate 550 is used, thereby providing both an upper sub-chamber 502 and a lower sub-chamber 503, an induced current acts on the gas present in the upper sub-chamber 502 to generate an electron-ion plasma in the upper sub-chamber 502. An optional internal plasma gate 550 limits the number of hot electrons in the lower sub-chamber 503. In some embodiments, the apparatus 500 is designed and operated so that the plasma in the lower sub-chamber 503 is an ion-ion plasma.

[0077] Both the upper electron-ion plasma and the lower ion-ion plasma can contain both positive and negative ions, though the ion-ion plasma will have a greater ratio of negative to positive ions. Volatile etching and / or deposition byproducts can be removed from the lower subchamber 503 through opening 522. The chuck 517 disclosed herein can operate at elevated temperatures between approximately 10°C and approximately 250°C. The temperature will depend on the processing operation and the specific recipe.

[0078] When installed in a cleanroom or manufacturing facility, the apparatus 500 can be coupled to a facility infrastructure (not shown). The facility infrastructure includes piping that provides process gases, vacuum, temperature control, and environmental particle control. The facility infrastructure is coupled to the apparatus 500 when installed in the target manufacturing facility. Furthermore, the apparatus 500 can be coupled to a transfer chamber that allows robots to transfer semiconductor wafers into and out of the apparatus 500 using typical automation.

[0079] In some embodiments, a system controller 530 (which may include one or more physical or logical controllers) controls some or all operations of the processing chamber 524. The system controller 530 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 500 includes a switching system for controlling flow rates and durations when performing the disclosed embodiments. In some embodiments, the switching time of the apparatus 500 may be up to approximately 500 ms, or up to approximately 750 ms. The switching time may depend on the flowing chemicals, the selected recipe, the reactor architecture, and other factors.

[0080] In some embodiments, the system controller 530 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for performing processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling the operation of these systems before, during, and after processing of semiconductor wafers or substrates. The electronics may be integrated into the system controller 530, which may control various components or sub-components of one or more systems. Depending on the processing parameters and / or system type, the system controller may be programmed to control any of the steps disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positioning and handling settings, wafer transfer into and out of tools connected to or interfaced with the particular system, other transfer tools, and / or load chambers.

[0081] Broadly speaking, system controller 530 can be defined as an electronic component having various integrated circuits, logic, memory, and / or software for receiving commands, issuing commands, controlling operations, enabling cleaning operations, performing endpoint measurements, and similar functions. The integrated circuits may include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be communicated to the controller in the form of various individual configurations (or program files) that define operating parameters for performing specific processes on or with the semiconductor wafer, or with the system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to perform one or more processing steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies on the wafer.

[0082] In some embodiments, the system controller 530 may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may reside in the "cloud" or in whole or in part on a mainframe computer system in a wafer fab, allowing remote control of wafer processing. The computer may enable remote control of the system to monitor the current process of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance metrics across multiple manufacturing operations, change parameters of the current process, set a processing step after the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network, such as a local area network (LAN) or the Internet. The remote computer may include a user interface that enables the input or programming of parameters and / or settings, which are then transferred from the remote computer to the system. In some examples, the system controller 530 receives instructions in the form of data specifying a plurality of parameters for each of the processing steps to be performed during one or more operating sessions. It should be understood that these parameters can be specific to the type of processing to be performed, as well as the type of tool to which the controller is coupled or controlled. Thus, as described above, the system controller 530 can be distributed, for example by including one or more independent controllers connected together via a network and working toward a common goal, such as the processing and control described herein. An example of a distributed controller for such a goal is one or more integrated circuits in a chamber communicating with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), which together control the processing in the chamber.

[0083] Without limitation, exemplary systems may include plasma etch chambers or modules, deposition chambers or modules, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, dry developer chambers or modules, and any other semiconductor processing system related to or used in the processing and / or manufacture of semiconductor wafers.

[0084] As described above, depending on one or more process steps to be performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or material handling tools used to move wafer containers into and out of tool locations and / or load ports in a semiconductor manufacturing facility.

[0085] EUVL patterning can be performed using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B® platform offered by ASML of Veldhoven, NL. The EUVL patterning tool can be a stand-alone device into which and from which substrates are moved for the deposition and etching described herein. Alternatively, as described below, the EUVL patterning tool can be a module within a larger, multi-component tool. Figure 6 depicts a semiconductor processing cluster tool architecture having vacuum-integrated deposition, EUV patterning, and dry develop / etch modules coupled to a vacuum transfer module, suitable for performing the processes described herein. While these processes can be performed without such vacuum-integrated equipment, such equipment may be advantageous in certain implementations.

[0086] Figure 6 depicts a semiconductor processing cluster tool architecture featuring vacuum-integrated deposition and patterning modules coupled to a vacuum transfer module, suitable for performing the processes described herein. The configuration of a transfer module used to transfer wafers between multiple storage devices and processing modules is referred to as a "cluster tool architecture" system. Depending on the requirements of a particular process, the deposition and patterning modules are vacuum-integrated. Other modules (e.g., for etching) may also be included in the cluster.

[0087] Vacuum transfer module (VTM) 638 interfaces with four processing modules 620a-620d, each of which can be optimized to perform various manufacturing processes. For example, processing modules 620a-620d can be used to perform deposition, evaporation, ELD, dry development, etching, stripping, and / or other semiconductor processing. For example, module 620a can be an ALD reactor operable to perform non-plasma thermal atomic layer deposition as described herein, such as a Vector tool available from Lam Research Corporation, Fremont, CA. Module 620b can be a PEALD tool (e.g., a Lam Vector®). It should be understood that the drawings are not necessarily drawn to scale.

[0088] Gas chambers 642 and 646 (also known as load chambers or transfer modules) interface with VTM 638 and patterning module 640. For example, as mentioned above, a suitable patterning module may be the TWINSCAN NXE: 3300B® platform (available from ASML of Veldhoven, NL). This tool architecture allows workpieces (e.g., semiconductor substrates or wafers) to be transferred under vacuum so as to not react prior to exposure. The integration of deposition modules and lithography tools is facilitated by the fact that EUVL also requires significantly reduced pressures due to the strong optical absorption of incident photons by ambient gases (e.g., H₂O, O₂, etc.).

[0089] As described above, this integrated architecture is only one possible embodiment of a tool for performing the processes described. These processes can also be performed using more conventional standalone EUVL scanners and deposition reactors (e.g., Lam Vector tools) as modules, either standalone or integrated with other tools (e.g., etch, strip, etc. (e.g., Lam Kiyo or Gamma tools)) in a cluster architecture, such as that described with reference to FIG6 (but without the integrated patterning module).

[0090] Plenum 642 can be an "output" load chamber, representing the transfer of substrates from the VTM 638 serving deposition module 620a to patterning module 640, while plenum 646 can be an "input" load chamber, representing the transfer of substrates from patterning module 640 back to VTM 638. Input load chamber 646 can also serve as an interface to the exterior of the tool, allowing for the entry and exit of substrates. Each processing module has a facet that connects it to VTM 638. For example, deposition processing module 620a has facet 636. Within each facet, sensors (e.g., sensors 1-18 shown) are used to detect the passage of wafer 626 as it moves between individual stations. Patterning module 640 and plenums 642, 646 can be similarly equipped with additional facets and sensors (not shown).

[0091] The main VTM robot 622 transfers wafers 626 between modules (including plenums 642 and 646). In one embodiment, robot 622 has one arm, while in another embodiment, robot 622 has two arms, each with an end effector 624 for picking up wafers (such as wafer 626) for transport. The front-end robot 644 is used to transfer wafers 626 from the output plenum 642 to the patterning module 640 and from the patterning module 640 to the input plenum 646. The front-end robot 644 also transports wafers 626 between the input load chamber and the exterior of the tool, facilitating the entry and exit of substrates. Because the input plenum module 646 can accommodate environments between atmospheric pressure and vacuum, wafers 626 can be moved between these two pressure environments without damage.

[0092] It should be noted that EUVL tools typically operate at higher vacuum levels than deposition tools. If this is the case, it may be desirable to increase the vacuum level of the substrate during transfer from the deposition process to the EUVL tool to allow for degassing of the substrate before entering the patterning tool. The output plenum 642 provides this function by maintaining the transferred wafer at a lower pressure (no higher than the pressure in the patterning module 640) for a period of time and evacuating any exiting gas, preventing contamination of the optical components of the patterning tool 640 by exiting gas from the substrate. A suitable pressure for the output exiting gas plenum is no more than 1E-8 Torr.

[0093] In some embodiments, a system controller 650 (which may include one or more physical or logical controllers) controls some or all operations of the cluster tool and / or its individual modules. It should be noted that the controller may be local to the cluster architecture, external to the cluster architecture on the manufacturing floor, or remotely located and connected to the cluster architecture via a network. The system controller 650 may include one or more memory devices and one or more processors. The processors may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor control boards, and other similar components. A plurality of instructions for performing appropriate control operations are executed on the processors. These instructions may be stored on a memory device connected to the controller or provided over a network. In some embodiments, the system controller executes system control software.

[0094] The system control software may include instructions for controlling the timing of the application and scale of the implementation of any tool or module operations. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components required to implement various process tool procedures. The system control software may be encoded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by the system controller. For example, instructions for setting process conditions for condensation, deposition, evaporation, patterning, and / or etching stages may be included in the corresponding recipe stage.

[0095] In various embodiments, an apparatus for forming a negative-tone pattern mask is provided. The apparatus may include a processing chamber for patterning, deposition, and etching, and a controller including instructions for forming a negative-tone pattern mask. The instructions may include program code for executing the following processes in the processing chamber: exposing a substrate surface by EUV exposure to pattern features in a chemically amplified photoresist (CAR) on a semiconductor substrate; dry-developing the photopatterned photoresist; and etching an underlying layer or layer stack using the patterned photoresist as a mask.

[0096] It should be noted that the computer controlling the wafer movement can be local to the cluster architecture, or can be located external to the cluster architecture on the manufacturing floor, or can be located at a remote location and connected to the cluster architecture via a network. The controller described above with respect to any of Figures 3, 4, or 5 can be implemented with the tool in Figure 6. in conclusion

[0097] Processes and apparatus are disclosed in the context of EUV patterning for dry development of metal and / or metal oxide photoresists to, for example, form patterned masks.

[0098] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications and variations are suggested to those skilled in the art. Although various details have been omitted for clarity, various design alternatives are possible. Therefore, the examples should be considered illustrative rather than restrictive, and the present disclosure is not limited to the details set forth herein, but may be modified within the scope of the disclosure.

[0099] 1-4: Processing Station 100: Wafer 102:Substrate 104: layer to be etched 106:EUV photoresist film 106a: non-EUV exposure area 300: Processing Station 301a: Reactant Delivery System 302: Processing chamber body 303: Vaporization point 304: Mixing container 306:Sprinkler head 308: Base 310: Heater 312:Substrate 314: Radio Frequency (RF) Power Supply 316: Matching Network 318: Butterfly Valve 320: Mixing container inlet valve 350: Computer controller 400:Multi-station processing tool 402: Inbound loading room 404: Outbound loading room 406: Robot 408:Box 410: Atmospheric Port 412: Base 414: Processing chamber 416: Chamber transfer port 418: Base 450: System Controller 452:Processor 454: Mass storage device 456:Memory device 458:System Control Software 500: Inductively coupled plasma equipment 501: Chamber wall 502: Upper sub-chamber 503: Lower sub-chamber 511: Window 517:Chuck 519: Wafer 521: Matching circuit 522: Open 523: Radio Frequency (RF) Power Supply 525:Connection 527:Connection 530: System Controller 533: Coil 539: Matching Circuit 540: Vacuum pump 541:RF Power Supply 543:Connection 545:Connection 549:Faraday shield 550: Plasma Gate 560: Main air flow inlet 570: Side air flow inlet 620a-620d: Processing module 622: Robot 624: End effector 626: Wafer 636: Dimension 638: Vacuum Transfer Module (VTM) 640: Patterned module 642: Air Chamber 644:Front-end robot 646: Air Chamber 650: System Controller

Claims

1. A method for processing a semiconductor substrate, comprising: Dry development of a photopatterned photoresist involves removing either an exposed portion or an unexposed portion of the photopatterned photoresist through a dry development process, the dry development process including exposure to a dry development gas that is selective between organometallic oxide materials in the unexposed portion and metal oxide materials in the exposed portion.

2. The method of claim 1, wherein the unexposed portion of the photopatterned photoresist is removed.

3. The method of claim 1, wherein the dry development process comprises a mild plasma.

4. The method of claim 3, wherein the mild plasma is generated at a pressure greater than 5 mT and a plasma power less than about 1000 watts.

5. The method of claim 3, wherein the mild plasma is generated at a pressure greater than 15 mT and a plasma power of less than 500 watts.

6. The method of claim 1, wherein the dry development process includes plasma-free heat treatment.

7. The method of claim 1, wherein the dry development process includes a combination of multiple methods, including mild plasma treatment and plasma-free thermal treatment.

8. The method of claim 1, wherein the optically patterned photoresist is sensitive to a radiation source selected from the group consisting of DUV, EUV, X-rays and electron beam radiation.

9. The method of claim 1, wherein the dry developing gas comprises RxZy, wherein R = B, Al, Si, C, S, SO and x > 0, and Z = Cl, H, Br, F, CH4 and y > 0.

10. The method of claim 9, wherein the dry developing gas comprises BCl3.

11. The method of claim 9, wherein the dry developing gas contains a Lewis acid.

12. The method of claim 9, wherein the dry developing gas comprises BBr3.

13. The method of claim 9, wherein the dry developing gas comprises SOF2.

14. The method of claim 9, wherein the dry developing gas comprises SOCl2.

15. The method of claim 1, wherein the photopatterned photoresist is a 10-20 nm thick film containing organotin oxide, deposited based on the vapor-phase reaction of the organotin precursor isopropyl(tris)(dimethylamino)tin with water vapor, subjected to EUV exposure and post-exposure baking, and the dry development process includes non-plasma thermal exposure of the photopatterned photoresist at 120°C, 10 mT, 500 sccm BCl3 for 30 seconds.

16. The method of claim 1, wherein the dry development process is performed at about 0 to 300°C.

17. The method of request item 1 further includes: After dry development to form a photoresist mask, the photoresist mask is used to etch one of the underlying layers.

18. The method of request item 1 further includes: A photoresist on the semiconductor substrate is exposed to a radiation source selected from the group consisting of DUV, EUV, X-rays and electron beam radiation to form the photopatterned photoresist, and a baking step is performed to increase the crosslinking in the photopatterned photoresist.

19. The method of claim 18, wherein the dry development and the baking step are performed in the same chamber.

20. The method of claim 18, wherein the dry development is performed in a first chamber and the baking step is performed in a second chamber different from the first chamber.

21. The method of claim 1 further includes: adjusting the dry development process to remove residue.

22. An apparatus for dry development of photoresist with pre-patterned photoresist, the apparatus comprising: One processing chamber; A substrate support member in the processing chamber is used to support a substrate having the photo-patterned photoresist. A gas delivery system fluidly coupled to the processing chamber to deliver one or more dry developing gases selectively between organometallic oxide materials in the unexposed portion and metal oxide materials in the exposed portion of the photopatterned photoresist; and one or more heaters for substrate temperature control.

23. The apparatus of claim 22, wherein the interior of the processing chamber is coated with a corrosion inhibitor.

24. The apparatus of claim 22, wherein the interior of the processing chamber is coated with a corrosion-resistant organic polymer or inorganic coating.

25. The apparatus of claim 24, wherein the corrosion-resistant organic polymer comprises polytetrafluoroethylene.

26. The method of claim 22 further includes a plasma source.

27. The apparatus of claim 26, wherein the plasma source is configured to generate transformer-coupled plasma, capacitor-coupled plasma, or downstream plasma.

28. The device of claim 26 further includes an RF power supply and a matching network configured to supply power to one of the plasma sources.

29. The apparatus of claim 28, wherein the plasma source is configured to control the timing of plasma power pulses in the plasma.

30. The apparatus of claim 22, wherein the one or more heaters are configured to control the temperature of the substrate between about 0 °C and about 300 °C.

31. The apparatus of claim 22, wherein the gas delivery system comprises: a spray head; and one or more mixing containers configured to mix or regulate the one or more dry developing gases, wherein the one or more mixing containers are fluidly coupled to the spray head.

32. The apparatus of claim 22 further includes a vacuum pump configured to remove one of the etched and / or deposited byproducts from the processing chamber.

33. The apparatus of claim 22 further includes a vacuum pump configured to control the pressure in the processing chamber between about 5 mT and about 15 mT.

34. The apparatus of claim 33, wherein the vacuum pump comprises a mechanical dry pump and / or a turbomolecular pump.

35. The apparatus of claim 22 further includes a controller programmed to have a plurality of instructions for controlling one or more of the following: processing chamber pressure, substrate temperature, concentration of one or more dry developing gases, RF source power, RF source frequency, and plasma power pulse timing.

36. The apparatus of claim 22, wherein the one or more dry developing gases comprise BCl3.

37. The apparatus of claim 22, wherein the gas delivery system is further configured to deliver one or more etching gases to etch one layer beneath the photopatterned photoresist.

38. A semiconductor processing cluster tool for processing a semiconductor substrate, the semiconductor processing cluster tool comprising: one or more vacuum deposition modules configured to deposit a photoresist on the semiconductor substrate; a photoresist exposure module configured to expose the photoresist to DUV, EUV, X-ray, or electron beam radiation to form a photopatterned photoresist; a photoresist dry development module configured to expose the photopatterned photoresist to one or more dry development gases, the one or more dry development gases being selective between organometallic oxide materials in unexposed portions and metal oxide materials in exposed portions of the photopatterned photoresist; and an etching module configured to etch a layer beneath the photopatterned photoresist.

39. The semiconductor processing cluster tool of claim 38, wherein the one or more vacuum deposition modules include an atomic layer deposition (ALD) reactor or a plasma-assisted chemical vapor deposition (PECVD) reactor, and wherein the photoresist exposure module includes an EUVL scanner.

40. The semiconductor processing cluster tool of claim 38 further includes: a vacuum transfer module configured to engage with the one or more vacuum deposition modules, the photoresist exposure module, the photoresist dry development module, and the etching module to transfer the semiconductor substrate between the one or more vacuum deposition modules, the photoresist exposure module, the photoresist dry development module, and the etching module.

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