Semiconductor device and method of forming the same

Abstract

In some embodiments, a semiconductor device is provided, comprising: an interconnect structure disposed above a substrate, wherein the interconnect structure includes conductive features disposed in a dielectric layer; a first passivation layer disposed above the interconnect structure; a second passivation layer disposed above an etch stop layer; a plurality of holes and a plurality of trenches extending from an upper surface of the second passivation layer into the second passivation layer, wherein the trenches overlap the etch stop layer in a plan view; a first capacitor structure disposed above the second passivation layer and extending into the holes, including a first conductive layer, a first insulating layer, and a second conductive layer; and a second capacitor structure disposed above the second passivation layer and extending into the trenches, including a third conductive layer, a second insulating layer, and a fourth conductive layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device including a capacitor structure and a method for forming the same. Prior Technology

[0002] Electronic devices involving semiconductor devices are crucial for many modern applications. Technological advancements in materials and design have yielded generation after generation of semiconductor devices, each with circuits that are smaller and more complex than the last. In the course of progress and innovation, functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while geometry (i.e., the smallest component that can be built using manufacturing processes) has decreased. Such advancements have increased the complexity of semiconductor device fabrication and manufacturing.

[0003] Capacitors are typically embedded in integrated passive devices, replacing ceramic capacitors to reduce device size, lower cost, increase functionality, or any combination thereof. To improve capacitor characteristics and performance, metal-insulator-metal (MIM) capacitor designs have recently been introduced, comprising multiple interleaved metal and dielectric layers. When the layers of a MIM capacitor are formed within grooves with high aspect ratios, the manufacturing process becomes complex and difficult to control. Therefore, an improved MIM capacitor structure and its manufacturing method are needed. Summary of the Invention

[0004] This disclosure provides some embodiments of a semiconductor device. The semiconductor device includes: an interconnect structure located above a substrate, wherein the interconnect structure includes conductive features disposed in a dielectric layer; a first passivation layer disposed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; an etch stop layer disposed above the first passivation layer; a second passivation layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from the upper surface of the second passivation layer into the second passivation layer, wherein at least one of the plurality of holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the plurality of trenches includes a first width in a first direction and a second width in a second direction perpendicular to the first direction. The plurality of trenches have a third width that is less than the first width in the upward direction and a fourth width that is greater than the second width in the second direction, wherein the plurality of trenches overlap with the etch stop layer in the plan view; a first capacitor structure includes a first conductive layer, a first insulating layer and a second conductive layer disposed above the second passivation layer and extending into the plurality of holes, wherein the second conductive layer is located above the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer above the upper surface of the second passivation layer has a curved top surface; and a second capacitor structure includes a third conductive layer, a second insulating layer and a fourth conductive layer disposed above the second passivation layer and extending into the plurality of trenches.

[0005] This disclosure provides a semiconductor device according to several embodiments. The semiconductor device includes: a means disposed above a substrate, wherein the means includes a plurality of source / drain features, each of the plurality of source / drain features including a plurality of layers containing the same semiconductor material at different concentrations; a first dielectric layer disposed above the means; an etch stop layer disposed above the first dielectric layer; a second dielectric layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from an upper surface of the second dielectric layer into the second dielectric layer, wherein the plurality of holes are disposed in a first region, the plurality of trenches are disposed in a second region, wherein at least one of the plurality of holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the plurality of trenches includes a third width in the first direction and a fourth width in the second direction, wherein the difference between the first width and the second width is less than the difference between the third width and the fourth width; and a capacitor structure including a first conductive layer, an insulating layer, and a second conductive layer disposed above the upper surface of the second dielectric layer and extending into the plurality of holes and the plurality of trenches, wherein a first occupancy area of ​​the first region is greater than a second occupancy area of ​​the second region.

[0006] This disclosure provides a method for forming a semiconductor device through some embodiments. The method includes: forming an interconnect structure over a substrate, wherein the interconnect structure includes conductive features disposed in a dielectric layer; forming a first passivation layer over the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; forming an etch stop layer over the first passivation layer; forming a second passivation layer over the etch stop layer; performing an etching process to form a plurality of holes and a plurality of trenches in the second passivation layer, wherein at least one of the plurality of holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the plurality of trenches includes a third width in the first direction less than the first width and a fourth width in the second direction greater than the second width; and forming a first capacitor structure and a second capacitor structure over the second passivation layer, wherein the first capacitor structure includes a first conductive layer, a first insulating layer and a second conductive layer extending into the plurality of holes, wherein the second conductive layer is disposed over the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer over the second passivation layer has a curved top surface, wherein the second capacitor structure includes a third conductive layer, a second insulating layer and a fourth conductive layer extending into the plurality of trenches, wherein the plurality of trenches overlap with the etch stop layer in a plan view. Simple Explanation of the Diagram

[0007] The concepts of the disclosed embodiments will be better understood by referring to the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration. Figure 1 is a perspective view of a semiconductor device including a device layer and interconnect structure according to some embodiments. Figure 2 is a cross-sectional view of the interconnect structure of a semiconductor device according to some embodiments. Figure 3 shows a cross-sectional view of a semiconductor device including an interconnect structure in a passivation structure according to some embodiments. Figure 4 is a schematic diagram, in plan view, of a region for arranging capacitor structures within a unit area of ​​a semiconductor device, according to some embodiments. Figures 5A, 5B, and 5C respectively show enlarged views of the aperture capacitor, trench capacitor, and hybrid capacitor in the area shown in Figure 4 according to some embodiments. Figures 6 through 12 show cross-sectional views of intermediate stages in the manufacture of a semiconductor device according to some embodiments. Figure 13 shows a cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments. Figure 14 shows a cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments. Figure 15 shows a cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments. Figure 16 shows a cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments. Figure 17 shows a cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments. Figure 18 shows a cross-sectional view of a semiconductor package according to some embodiments. Figure 19 shows a cross-sectional view of a semiconductor device including a capacitor structure and a back-side interconnect structure according to some embodiments. Implementation

[0008] The following disclosure provides many different embodiments or examples to implement different features of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the description of the embodiments disclosed herein. Of course, these specific examples are merely illustrative and not intended to limit the embodiments disclosed herein. For example, in the following description, reference to a first feature being formed on or above a second feature indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself limit the relationship between the various embodiments and / or configurations described.

[0009] In addition, spatial terms such as "below," "lower," "above," "above," "top," "higher," and similar terms may be used in this document to describe the relationship between one element or feature shown in the diagram and another element(s). Besides the orientation shown in the diagram, these spatial terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial terms used herein may be interpreted accordingly.

[0010] According to some embodiments, a semiconductor device including a capacitor structure is provided. The semiconductor device may include a via capacitor and a trench capacitor formed in a passivation structure above an interconnect structure. The via capacitor includes a layer extending into the via, while the trench capacitor includes a layer extending into the trench. The via capacitor can generate less stress in the semiconductor device, while the trench capacitor can be disposed in a small area. The passivation structure may include an etch stop layer at least located at the location where the trench is to be formed. The etch stop layer can partially or completely resist the etch process for forming the trench. Thus, although the etch rate during trench formation may be higher than the etch rate during via formation, the trench can be located away from the underlying interconnect structure without damaging the underlying interconnect structure when the via reaches its desired depth. Therefore, the semiconductor device can simultaneously include both via capacitors and trench capacitors, improving manufacturing yield.

[0011] Figure 1 is a perspective cross-sectional view of a semiconductor device 100 including a device layer 200 and an interconnect structure 250. The device layer 200 includes a substrate 102 and one or more devices formed in or on the substrate 102. The substrate 102 may be a semiconductor substrate. In some embodiments, the substrate 102 includes at least a crystalline semiconductor layer located on the surface of the substrate 102. The substrate 102 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide arsenide (GaAsSb), and indium phosphide (InP). For example, the substrate 102 is made of Si. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one respect, the insulating layer is an oxygen-containing material, such as an oxide.

[0012] The substrate 102 may include various regions, including active regions and isolation regions. The active regions may be suitably doped with impurities (e.g., p-type or n-type impurities) to form, for example, well regions.

[0013] As described above, device layer 200 may include any suitable device, such as a transistor, diode, imaging sensor, resistor, capacitor, inductor, memory cell, or a combination thereof. In some embodiments, device layer 200 includes a transistor, such as a planar field-effect transistor (FET), FinFET, nanostructured transistor, or other suitable transistor. Nanostructured transistors may include nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel (MCB) transistors, or any transistor having a gate electrode surrounding the channel. An example of a device formed on substrate 102 is a FinFET, as shown in Figure 1. Device layer 200 includes source / drain (S / D) regions 124 and gate stacks 140 (only one is shown in Figure 1). Each gate stack 140 may be disposed between one or more S / D regions 124 serving as source regions and one or more S / D regions 124 serving as drain regions. For example, each gate stack 140 may extend along the Y-axis between one or more S / D regions 124 serving as source regions and one or more S / D regions 124 serving as drain regions. Although not shown, channel regions are formed between the S / D regions 124 and have at least three surfaces surrounded by the gate stack 140.

[0014] The S / D region 124 may include semiconductor materials such as Si or Ge, III-V compound semiconductors, II-VI compound semiconductors, or other suitable semiconductor materials. Exemplary S / D regions 124 may include, but are not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, etc. The S / D region 124 may include p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. The S / D region 124 may be formed by epitaxial growth methods using CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The channel region may include one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, or InP. The channel region may include the same semiconductor material as the substrate 102. In some embodiments, the device layer 200 may include a FinFET, and the channel region is a plurality of fins disposed below the gate stack 140. In some embodiments, the device layer 200 may include a nanostructured transistor, and the channel region is surrounded by the gate stack 140.

[0015] Gate stack 140 includes a gate electrode layer 138 disposed above the channel region (or surrounding the channel region for nanostructured transistors). Gate electrode layer 138 may be a metallic material, such as tungsten, cobalt, aluminum, ruthenium, copper, or multilayers thereof, and may be deposited using ALD, plasma-enhanced chemical vapor deposition (PECVD), MBE, physical vapor deposition (PVD), or any suitable deposition technique. Gate stack 140 may also include a gate dielectric layer 136 disposed above the channel region. Gate electrode layer 138 may be disposed above gate dielectric layer 136. In some embodiments, an interface layer (not shown) may be disposed between the channel region and gate dielectric layer 136, and one or more work function layers (not shown) may be formed between gate dielectric layer 136 and gate electrode layer 138. The interface layer may include a dielectric material, such as an oxygen-containing or nitrogen-containing material, or multiple layers thereof, and may be formed by any suitable deposition method, such as CVD, PECVD, or ALD. The gate dielectric layer 136 may include a dielectric material, such as an oxygen-containing or nitrogen-containing material, a high dielectric constant (k) dielectric material with a k-value greater than that of silicon dioxide, or multiple layers thereof. The gate dielectric layer 136 may be formed by any suitable method, such as CVD, PECVD, or ALD. In some embodiments, the gate dielectric layer 136 may be a conformal layer. The term "conformal" may be used herein to conveniently describe layers having substantially the same thickness in various regions. The one or more work function layers may include titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, etc.

[0016] Gate spacers 122 are formed along the sidewalls of the gate stack 140 (e.g., the sidewalls of the gate dielectric layer 136). Gate spacers 122 may comprise silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., multilayers thereof, or combinations thereof, and may be deposited by CVD, ALD, or other suitable deposition techniques. In some embodiments, fin sidewall spacers 123 may be disposed on opposite sides of each S / D region 124, and fin sidewall spacers 123 may comprise the same material as gate spacers 122. Portions of the gate stack 140, gate spacers 122, and fin sidewall spacers 123 may be disposed on isolation regions 114. Isolation regions 114 are disposed on the substrate 102. Isolation regions 114 may comprise insulating materials, such as oxygen-containing materials, nitrogen-containing materials, or combinations thereof. In some embodiments, isolation regions 114 are shallow trench isolation (STI). The insulating material can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one aspect, the insulating region 114 comprises silicon oxide formed by an FCVD process.

[0017] A contact etch stop layer (CESL) 126 is formed on the S / D region 124 and the isolation region 114, and an interlayer dielectric (ILD) layer 128 is formed on the contact etch stop layer 126. The contact etch stop layer 126 provides a mechanism to stop the etch process when an opening is formed in the interlayer dielectric layer 128. The contact etch stop layer 126 may be conformally deposited on the surfaces of the S / D region 124 and the isolation region 114. The contact etch stop layer 126 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or combinations thereof, and may be deposited using CVD, PECVD, ALD, or any suitable deposition technique. The interlayer dielectric layer 128 may comprise an oxide formed of tetraethyl orthosilicate (TES), an undoped silicate glass, or a doped silica, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), organosilicate glass (OSG), SiOC, and / or any suitable low dielectric constant (k) dielectric material (e.g., a material with a dielectric constant lower than that of silica), and may be deposited by spin coating, CVD, FCVD, PECVD, PVD, or any suitable deposition technique.

[0018] S / D contact 142 may be disposed in the interlayer dielectric layer 128 and above the S / D region 124. S / D contact 142 may be conductive and comprise a material having one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN, and the conductive contact may be formed by any suitable method, such as electrochemical plating (ECP), CVD, or PVD. A silicate layer 144 may be disposed between S / D contact 142 and S / D region 124. Silicate layer 144 may be made of a metal or metal alloy silicate, and said metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof.

[0019] In integrated circuits, interconnect structures are used to provide signal routing and power for semiconductor devices. An integrated circuit wafer typically includes device layers fabricated during front-end-of-line (FEOL) and middle-end-of-line (MEOL) processes, and a back-end-of-line (BEOL) layer. Device layers may be formed in and / or on a substrate, and BEOL layers are formed on the front and / or back sides of the device layers. Device layers may include various semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., and may be formed in and / or on a substrate. In some embodiments, the device layer may also include MEOL structures, such as one or more dielectric layers having conductive structures connected to gate and source / drain features within the device layer. Interconnect structures typically include conductive lines and vias formed in the device layers and BEOL layers.

[0020] Figure 2 is a cross-sectional view of the interconnect structure at an intermediate stage of manufacturing a semiconductor device 100 according to some embodiments, wherein the interconnect structure is depicted in detail. Interconnect structure 250 is formed over device layer 200. Interconnect structure 250 includes various conductive features 204 formed in dielectric layer 202, such as conductive lines 205 and conductive vias 206. Dielectric layer 202 may be an intermetallic dielectric (IMD) layer or an interlayer dielectric (ILD) layer. Dielectric layer 202 may include multiple dielectric layers embedded with multiple layers of conductive lines 205 and conductive vias 206. Dielectric layer 202 includes a dielectric material, such as SiOx, SiOxCyHz, or SiOxCy, where x, y, and z are integers or non-integers. In some embodiments, dielectric layer 202 includes a low-k dielectric material whose k value is less than the k value of silicon oxide. The conductive wire 205 and the conductive via 206 may be made of one or more conductive materials, such as metal, metal alloy, metal nitride, or silicon. The conductive via 206 and the conductive wire 205 are arranged in layers to provide electrical paths to the gate electrode layer 138 (Figure 1) and the S / D contact 142 (Figure 1) in the device layer.

[0021] Figure 3 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device 100 according to some embodiments, wherein the passivation structure is depicted in detail. In Figure 3, a passivation structure 300 is formed over an interconnect structure 250. The passivation structure 300 may include a first passivation structure 310 disposed over the interconnect structure 250 and a second passivation structure 350 disposed over the first passivation structure 310. A capacitor structure 320 and / or other passivation devices may be formed in the first passivation structure 310. A bonding structure 360 ​​may be formed in the second passivation structure 350. In some embodiments, a conductive through-via 370 extends through the first passivation structure 310 to electrically couple the bonding structure 360 ​​to the conductive feature 204 of the interconnect structure 250.

[0022] In some embodiments, the first passivation structure 310 includes a first etch stop layer 312 above the dielectric layer 202 of the interconnect structure 250, a first passivation layer 314 above the first etch stop layer 312, a second etch stop layer 316 above the first passivation layer 314, and a second passivation layer 318 above the second etch stop layer 316. The first etch stop layer 312 may comprise a material different from the dielectric layer 202 to have a different etch selectivity compared to the dielectric layer 202. In some embodiments, the first etch stop layer 312 is made of an insulating material, such as a carbide, nitride, metal oxide, metal nitride, or a combination thereof. Suitable materials for the first etch stop layer 312 may include, but are not limited to, silicon carbide, silicon carbonitride, silicon carbonitride oxide, aluminum nitride, aluminum oxide, titanium oxide, or a combination thereof. The first etch stop layer 312 may be formed by any suitable process, such as CVD, ALD, PVD, PECVD, or a combination thereof. According to some embodiments, the thickness of the first etch stop layer 312 is approximately 100 nm to approximately 200 nm. The first etch stop layer 312 can partially or completely resist the etching process for forming through holes for accommodating conductive vias 370. In this way, an additional etch process with a lower etch rate can be implemented to etch through the first etch stop layer so that the through holes extend through the first etch stop layer 312, thereby reducing or avoiding over-etching that could damage the conductive features 204 of the interconnect structure 250.

[0023] According to some embodiments, the first passivation layer 314 comprises a material different from that of the dielectric layer 202 and the first etch stop layer 312. For example, the first passivation layer 314 is a passivation layer that provides, for example, moisture-proof sealing properties or mechanical robustness to protect the underlying interconnect structure 250 and device layer 200. The dielectric constant of the first passivation layer 314 may be greater than that of the dielectric layer 202 in the interconnect structure 250. In some embodiments, the first passivation layer 314 comprises silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the dielectric layer 202 is silicon oxide, and the first passivation layer 314 is silicon nitride. The first passivation layer 314 may have a thickness T1 of about 150 nm to about 500 nm.

[0024] The second etch stop layer 316 may comprise a different material than the first passivation layer 314 to have a different etch selectivity compared to the first passivation layer 314. For example, the second etch stop layer 316 may be or comprise a high-resistance material, such as silicon carbonitride, silicon carbide, silicon carbonitride oxide, undoped silicon, undoped germanium, undoped silicon germanium, silicon nitride, hafnium oxide, zirconium oxide, or a stacked structure comprising oxide-nitride-oxide layers (e.g., SiO-SiN-SiO). The thickness of the second etch stop layer 316 is greater than the thickness of the first etch stop layer 312 and less than the thickness of the first passivation layer 314. For example, the thickness of the second etch stop layer 316 may be approximately 30 nm to approximately 80 nm.

[0025] According to some embodiments, the second passivation layer 318 comprises a material different from that of the dielectric layer 202 and the second etch stop layer 316. For example, the second passivation layer 318 is a passivation layer that provides, for example, moisture-proof sealing properties or mechanical robustness to protect the underlying interconnect structure 250 and device layer 200. The second passivation layer 318 may be or comprise a material similar to that of the first passivation layer 314. For example, the second passivation layer 318 comprises silicon nitride, silicon oxynitride, or combinations thereof. The second passivation layer 318 may have a thickness T2 of about 150 nm to about 500 nm. In some embodiments, the second passivation layer 318 has substantially the same thickness as the first passivation layer 314, although the first passivation layer 314 and the second passivation layer 318 may have different thicknesses.

[0026] A capacitor structure 320 is formed over a second passivation layer 318. According to some embodiments, the capacitor structure 320 extends into the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318 to increase the surface area. The capacitor structure 320 may be a metal-insulator-metal (MIM) structure. For example, each capacitor structure 320 may include a first conductive layer 322, an insulating layer 324 above the first conductive layer 322, and a second conductive layer 326 above the insulating layer 324. Although three layers are shown in Figure 3, the capacitor structure 320 may include more layers.

[0027] In some embodiments, the first conductive layer 322 comprises one or more layers of Cu, Al, W, Co, Ti, Ta, TiN, TaN, or alloys thereof. In some embodiments, the thickness of the first conductive layer 322 is in the range of about 10 nm to about 100 nm, depending on design and / or process requirements. An insulating layer 324 is formed over the first conductive layer 322 and the first passivation layer 314. In some embodiments, the insulating layer 324 comprises one or more high-k dielectric layers with a dielectric constant greater than that of silicon oxide. In some embodiments, the insulating layer 324 comprises one or more layers of metal oxides or silicates of Hf, Al, Zr, combinations thereof, or multiple layers thereof. In some embodiments, hafnium oxide is used. Other suitable materials include La, Mg, Ba, Ti, Pb, and Zr in the form of metal oxides, metal alloy oxides, or combinations thereof. Exemplary materials include MgO, BaTiO, BaSrTiO, PbTiO, PbZrTiyO, AlO, LaO, TaO, YO, HfO, ZrO, HfSiON, YGeO, YSiO, and LaAlO, combinations thereof, etc. In some embodiments, the thickness of the insulating layer 324 is in the range of about 1 nm to about 10 nm, and in other embodiments, it is in the range of about 2 nm to about 5 nm, depending on design and / or process requirements. The second conductive layer 326 may include or may be the same material as the first conductive layer 322. In some embodiments, seams or air gaps may be formed in the capacitor structure 320 and sealed by the second conductive layer 326 or the insulating layer 324. In some embodiments, at least a portion of the first conductive layer 322 above the upper surface of the second passivation layer 318 has a curved top surface. At least a portion of the insulating layer 324 above the upper surface of the second passivation layer 318 may have a curved top surface. At least a portion of the second conductive layer 326 above the upper surface of the second passivation layer 318 may have a curved top surface.

[0028] According to some embodiments, a plurality of holes 328A and trenches 328B are formed in a second passivation layer 318. The holes 328A and trenches 328B may extend from the upper surface of the second passivation layer 318 into the second passivation layer 318. For example, referring to Figures 4 and 5A to 5C, the holes 328A may be arranged in a matrix in the hole region 329A. Each hole 328A may have a circular or near-circular shape in a plan view. For example, at least one hole 328A has a first width W1 in a first direction (e.g., the X direction in Figure 4) and a second width W2 in a second direction perpendicular to the first direction (e.g., the Y direction in Figure 4). The trenches 328B may have a longitudinal axis along the first direction and be repeatedly arranged in the second direction, and / or have a longitudinal axis along the second direction and be repeatedly arranged in the first direction. For example, as shown in Figure 4, at least one trench 328B has a third width W3 in a first direction (e.g., the X direction in Figure 4) and a fourth width W4 in a second direction (e.g., the Y direction in Figure 4), the fourth width W4 being greater than the third width W3. In some embodiments, the difference between the first width W1 and the second width W2 is less than the difference between the third width W3 and the fourth width W4, and the second spacing S2 between adjacent trenches 328B of the trench capacitor 320B is less than the first spacing S1 of the aperture capacitor 320A.

[0029] Referring back to Figure 3, capacitor structure 320 may include multiple portions extending into aperture 328A and trench 328B. For example, capacitor structure 320 may include one or more aperture capacitors 320A, one or more trench capacitors 320B, one or more hybrid capacitors 320C, and one or more dummy MIM structures 320D. Aperture capacitor 320A may include a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 disposed above the upper surface of the insulating layer 324 and extending into aperture 328A. Trench capacitor 320B may include a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 disposed above the upper surface of the insulating layer 324 and extending into trench 328B. Hybrid capacitor 320C may include a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 disposed above the upper surface of the insulating layer 324 and extending into both aperture 328A and trench 328B. The dummy MIM structure 320D can be disposed above the second passivation layer 318. The dummy MIM structure 320D can be electrically isolated from other capacitors in the capacitor structure 320.

[0030] As will be discussed below, the hole 328A for accommodating the via capacitor 320A and the trench 328B for accommodating the trench capacitor 320B can be formed in the same process, wherein, for pattern variation, the etching rate for forming the trench 328B will be greater than the etching rate for forming the hole 328A. After the etching process, the trench 328B may be etched to a greater depth than the hole 328A. For example, the depth D1 of the hole 328A can be in the range of about 200 nm to about 400 nm, for example, about 100 nm to about 300 nm, although deeper or shallower holes may also be used. The depth D2 of the trench 328B can be in the range of about 500 nm to about 850 nm, for example, about 600 nm to about 700 nm, although deeper or shallower trenches may also be used. The trench 328B and the hole 328A may have a vertical gap G1 of about 100 nm to about 300 nm, which is about 0.5 to about 1.5 times the depth D1 of the hole 328A.

[0031] In some embodiments, the bottom of the trench 328B is located below the second etch stop layer 316, while the bottom of the via 328A is located above the second etch stop layer 316. Therefore, the trench capacitor 320B has a greater depth than the via capacitor 320A. In some embodiments, after the etching process, the trench capacitor 320B penetrates the second etch stop layer 316, while the via capacitor 320A is located above the second etch stop layer 316. As shown in Figure 3, the first conductive layer 322 in the via capacitor 320A may be at a distance from the second etch stop layer 316, while the first conductive layer 322 in the trench capacitor 320B may be in contact with the second etch stop layer 316.

[0032] According to some embodiments, the first passivation structure 310 further includes a filling layer 332 for the capacitor structure 320. The filling layer 332 may extend into and fill the remaining space of the via 328A and / or trench 328B. The filling layer 332 also serves as an isolation layer electrically isolating the capacitor structures 320 from each other. The filling layer 332 may have a material similar to the first passivation layer 314 or the second passivation layer 318. In some embodiments, the filling layer 332 has a flat upper surface.

[0033] According to some embodiments, a conductive via 370 is formed in a first passivation layer 314, a second etch stop layer 316, and a second passivation layer 318. The conductive via 370 may extend through the first etch stop layer 312 to be electrically coupled to a conductive feature 204 of the underlying interconnect structure 250. The conductive via 370 may include a low-resistivity main conductive material 372, such as Cu, W, Ru, Al, Au, Ag, or combinations thereof. The conductive via 370 may also include a barrier layer 374 and / or a seed layer 376 located between the main conductive material 372 and layers adjacent to the conductive via 370. The barrier layer 374 may include metals such as Ti, Ta, Ru, or metal nitrides such as TiN, TaN, or combinations thereof. The thickness of the barrier layer 374 is in the range of about 1 nm to about 10 nm. If the thickness of the barrier layer 374 is less than about 1 nm, the barrier layer 374 may be insufficient to prevent the diffusion of the main conductive material 372. The seed layer 376 may include Cu, Ti, or a composite structure containing Cu and Ti layers.

[0034] A conductive via 370 may also penetrate one of the capacitor structures 320, for example, through the second conductive layer 326, the insulating layer 324, and the first conductive layer 322. Depending on design requirements, the conductive via 370 may penetrate a via capacitor 320A, a trench capacitor 320B, or a hybrid capacitor 320C to be electrically coupled to the via capacitor 320A, the trench capacitor 320B, or the hybrid capacitor 320C. Alternatively, when the conductive via 370 is designed not to be electrically coupled to the active capacitor structure 320 (e.g., 320A, 320B, or 320C), the conductive via 370 may penetrate a dummy MIM structure 320D.

[0035] Figure 4 is a schematic diagram, in plan view, of a region for arranging capacitor structures per unit area of ​​semiconductor device 100 according to some embodiments. Figures 5A, 5B, and 5C respectively show enlarged views of a via capacitor 320A, a trench capacitor 320B, and a hybrid capacitor 320C in the region shown in Figure 4 according to some embodiments. Figure 3 is a corresponding cross-sectional view along section A-A' shown in Figure 4 according to some embodiments. Semiconductor device 100 may include a via region 329A, in which a via 328A is formed for arranging a via capacitor 320A. Semiconductor device 100 may also include a trench region 329B, in which a trench 328B is formed for arranging a trench capacitor 320B. Semiconductor device 100 may also include a via region 329C for arranging conductive vias 370 therein and an isolation region 330 that may be filled with a filling layer 332.

[0036] It has been found that the stress generated by the via capacitor 320A is less than that generated by the trench capacitor 320B. Therefore, in a semiconductor device, the via region 329A can occupy most of the unit area of ​​the semiconductor device 100, while the trench region 329B can be located at the edge of or adjacent to the via region 329A. For example, in the semiconductor device 100 shown in Figure 4, the area occupied by the via region 329A can be larger than the area occupied by the trench region 329B to reduce the stress in the semiconductor device 100, thereby reducing or preventing film cracking or delamination. On the other hand, the width and spacing of the trenches 328B of the trench capacitor 320B are smaller than the width and spacing of the vias 328A of the via capacitor 320A. Therefore, the trench region 329B for the trench capacitor 320B can be arranged at the edge of the via region 329A, for example, in the area near the via region 329C or at the edge of the unit area of ​​the semiconductor device 100. In some embodiments, as shown in Figure 4, a trench region 329B is disposed between a via region 329C and a hole region 329A. In some embodiments, the via region 329C is surrounded by the trench region 329B and / or further surrounded by the hole region 329A. In some embodiments, the via region 329C is jointly surrounded by the trench region 329B and the isolation region 330.

[0037] The presence of the trench capacitor 320B (or hybrid capacitor 320C) can increase the pattern density of the capacitor structure 320. Therefore, the capacitor density and wiring design flexibility of the capacitor structure 320 can be improved. Furthermore, when the trench capacitor 320B occupies a limited area in a given region, it may only generate limited or negligible stress without causing film cracking or delamination problems.

[0038] Referring back to Figure 3, according to some embodiments, a second passivation structure 350 is formed over a first passivation structure 310. The second passivation structure 350 may include a third passivation layer 352 formed over a filler layer 332, a fourth passivation layer 354 formed over the third passivation layer 352, and a dielectric layer 356 formed over the fourth passivation layer 354. In some embodiments, the third passivation layer 352 may be or include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, etc. The fourth passivation layer 354 includes a material different from the third passivation layer 352, such as silicon oxide or glass, including silicate glass, borosilicate glass (BSG), phosphosilate glass (PSG), borosophosphosilate glass (BPSG), combinations thereof, etc. The dielectric layer 356 comprises silica, silicate glass, molding compound, or organic material (e.g., polybenzoxazoles (PBO), polyimide (PI), benzocyclobutene (BCB), other suitable organic polymers, or combinations thereof). The third passivation layer 352 and the fourth passivation layer 354 may be conformal layers. The dielectric layer 356 is thicker than the third passivation layer 352 and the fourth passivation layer 354 and has a flat upper surface. In some embodiments, one of the third passivation layer 352 and the fourth passivation layer 354 may be omitted for cost savings.

[0039] In some embodiments, the conductive via 370 protrudes above the first passivation structure 310 and extends into the second passivation structure 350, although the conductive via 370 may also have a top surface flush with the top surface of the filler layer 332. In embodiments where the conductive via 370 extends into the second passivation structure 350, a third passivation layer 352 and a fourth passivation layer 354 are conformally located on the conductive via 370. In some embodiments, the protrusion of the conductive via 370 is a conductive line, thus the conductive via 370 can serve as a redistribution layer.

[0040] In some embodiments, a bonding structure 360 ​​is formed in the dielectric layer 356. The bonding structure 360 ​​may further penetrate the fourth passivation layer 354 and the third passivation layer 352 to physically couple and / or electrically couple to the conductive via 370. The bonding structure 360 ​​may include Cu or other suitable bonding materials (e.g., Ni, Au, Ag, Pd, Al, Sn). In some embodiments, the bonding structure 360 ​​may also include a barrier layer and / or a seed layer similar to the conductive via 370. Depending on the bonding requirements, the bonding structure 360 ​​may be a bump protruding above the dielectric layer 356 or have a top surface flush with the top surface of the dielectric layer 356. In some embodiments, an additional dielectric layer (e.g., silicon oxide) may be formed above the dielectric layer 356 to provide bonding functionality, and the bonding structure 360 ​​may protrude above this bonding layer 358 or have a top surface flush with the top surface of the bonding layer 358.

[0041] Figures 6 through 12 show cross-sectional views of intermediate stages in the manufacture of a semiconductor device 100 according to some embodiments. In Figure 6, after the device layer 200 and interconnect structure 250 are formed over the substrate 102, a first etch stop layer 312, a first passivation layer 314, a second etch stop layer 316, and a second passivation layer 318 are sequentially formed over the dielectric layer 202 and conductive feature 204. The first etch stop layer 312, the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318 can all be formed by suitable deposition processes, such as CVD, ALD, PVD, PECVD, and combinations thereof. In some embodiments, the first etch stop layer 312, the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318 can be formed in the same deposition machine or the same chamber of the deposition machine to increase production capacity, as this saves transport time between different chambers or deposition machines.

[0042] In Figure 7, according to some embodiments, an anisotropic etching process can be used to form a hole 328A for accommodating a via capacitor 320A and a trench 328B for accommodating a trench capacitor 320B in the second passivation layer 318 and the layer below it. In some embodiments, a patterned mask is formed over the second passivation layer 318. The patterned mask can be a photoresist material, a hard mask (e.g., silicon oxide, TiN, TiO, etc.), or a combination thereof. An etching process can then be performed to transfer the pattern of the patterned mask to the underlying layer. The etching process can be anisotropic etching processes, such as reactive ion etching (RIE) or neutral beam etching (NBE). For example, the etching process may include chemicals (including HBr, NF3, O2, SF6, or combinations thereof) and physical ion bombardment.

[0043] Although via 328A and trench 328B are formed in the same etching process, it has been found that the etching rate for forming trench 328B is faster than that for forming via 328A. In some embodiments, the etching rate for forming trench 328B is approximately three times faster than that for forming via 328A. Therefore, when via 328A is etched to the desired depth, trench 328B may penetrate the second passivation layer 318, the second etch stop layer 316, and the first passivation layer 314, resulting in an unwanted short circuit between trench capacitor 320B and the conductive feature 204 of interconnect structure 250. The presence of the second etch stop layer 316 effectively reduces the etching rate for forming trench 328B, thereby preventing or reducing the frequency at which trench 328B penetrates the first passivation layer 314 and the first etch stop layer 312.

[0044] As shown in Figure 7, according to some embodiments, trench 328B extends through the second etch stop layer 316 and partially enters the first passivation layer 314. In other embodiments, trench 328B rests on the second etch stop layer 316 without extending through it. The presence of the second etch stop layer 316 also reduces the gap G1 between the bottom of the hole 328A and the trench 328B. Therefore, given the thicknesses of the second passivation layer 318 and the first passivation layer 314, the capacitance density of the capacitor structure 320 can be increased because the hole-type capacitor 320A, occupying a relatively large area, can be designed to have a deeper depth due to the reduced gap G1. In some embodiments, during the etching process, the hole 328A can still maintain a certain distance from the second etch stop layer 316 when the trench 328B penetrates it. After forming the hole 328A and the trench 328B, the patterned mask can be removed by, for example, an ashing process or an etching process.

[0045] In Figure 8, according to some embodiments, a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 are formed in trench 328B, hole 328A, and on the top surface of the second passivation layer 318. Specifically, the first conductive layer 322 is conformally formed in trench 328B and hole 328A and above the upper surface of the second passivation layer 318. The first conductive layer 322 may be formed by PVD, CVD, or ALD. The insulating layer 324 is conformally formed above the first conductive layer 322. In some embodiments, the insulating layer 324 is formed by CVD or ALD. Next, the second conductive layer 326 is conformally formed above the insulating layer 324. The second conductive layer 326 may be formed by PVD, CVD, or ALD. In some embodiments, because the width of trench 328B is small, trench 328B may be sealed by the second conductive layer 326 or the insulating layer 324, while hole 328A is not sealed. Therefore, the seam or air gap is formed in the groove 328B, not in the hole 328A. In some embodiments, the hole 328A may also be sealed, for example, through the second conductive layer 326 or when more layers are used in the capacitor structure 320.

[0046] After the formation of the first conductive layer 322, the insulating layer 324, and the second conductive layer 326, an anisotropic etching process can be performed to etch the first conductive layer 322, the insulating layer 324, and the second conductive layer 326, thereby defining the boundary of each capacitor structure 320. Although a single etching process can be used to define the boundary of the capacitor structure 320 (as described above), the pattern of each layer (322, 324, 326) of the capacitor structure 320 can also be defined individually. For example, each layer (322, 324, 326) can be individually patterned through one or more etching processes after its deposition and before the formation of the next layer.

[0047] In Figure 9, according to some embodiments, after forming the capacitor structure 320, a filler layer 332 is formed to cover the capacitor structure 320. In embodiments where the trench 328B and / or the via 328A are not sealed, the filler layer 332 may extend into the trench 328B and / or the via 328A to fill the remaining space in the trench 328B and / or the via 328A. The filler layer 332 may be formed by a suitable deposition process, such as CVD, PECVD, LPCVD, etc., and may undergo a planarization process (e.g., chemical mechanical polishing (CMP)) to planarize the upper surface of the filler layer 332.

[0048] In Figure 10, according to some embodiments, a conductive via 370 is formed in a first etch stop layer 312, a first passivation layer 314, a second etch stop layer 316, a second passivation layer 318, a capacitor structure 320, and a fill layer 332. The conductive via 370 can be electrically coupled to a conductive feature 204 of an interconnect structure 250. The conductive via 370 can be formed through one or more etching processes and by depositing a layer in the opening. The etching process can include anisotropic etching processes, such as RIE or NBE. In some embodiments, a masking layer (e.g., a hard masking layer) can be deposited over the fill layer 332 prior to the etching process. The hard masking layer can include silicon oxide, titanium nitride, aluminum oxide, titanium oxide, or combinations thereof.

[0049] After forming the opening for the conductive via 370, a barrier layer 374, a seed layer 376, and a main conductive material 372 are subsequently formed within the opening. The barrier layer 374 and the seed layer 376 may be conformally deposited, for example, by ALD, CVD, or PVD, within the opening and above the upper surface of the fill layer 332. Next, a photoresist layer is formed over the barrier layer 374 or the seed layer 376 and patterned to expose portions of the seed layer 376 within the opening and their adjacent portions. In some embodiments, plating (e.g., electroplating or electroless plating) or other suitable deposition processes are performed to form the main conductive material 372 over the exposed portions of the seed layer 376. The deposited conductive via 370 may include protrusions located above the upper surface of the fill layer 332. After forming the conductive via 370, the photoresist layer is removed by a suitable process (e.g., wet stripping or ashing), and portions of the seed layer 376 and the barrier layer 374 are removed by a suitable wet etching process. As shown in Figure 3, the protrusion of the conductive via 370 can be retained and covered by the second passivation structure 350. Alternatively, the protrusion of the conductive via 370 can be removed by a planarization process (e.g., CMP), depending on the design requirements of the bonding structure 360.

[0050] In Figure 11, according to some embodiments, a second passivation structure 350 is formed over the first passivation structure 310 and the conductive via 370. The formation of the second passivation structure 350 may include forming a third passivation layer 352 over the upper surface of the filler layer 332 and the conductive via 370, and optionally forming a fourth passivation layer 354 over the third passivation layer 352. The third passivation layer 352 and the fourth passivation layer 354 may be conformally deposited, for example, by CVD, PVD, ALD, or combinations thereof. Next, a dielectric layer 356 is formed over the third passivation layer 352 or the fourth passivation layer 354 (if present). The dielectric layer 356 may be formed by a suitable deposition process, such as CVD, PECVD, LPCVD, MOCVD, spin coating, or combinations thereof. After depositing the dielectric layer 356, a planarization process, such as CMP or mechanical polishing, may be performed. In some embodiments where a bonding layer 358 is required, the bonding layer 358 is deposited on the upper surface of the dielectric layer 356, for example, through CVD, PECVD, LPCVD, ALD, PVD, etc.

[0051] In Figure 12, according to some embodiments, a bonding structure 360 ​​is formed in a dielectric layer 356 (and a bonding layer 358, if present). Forming the bonding structure 360 ​​may include forming an opening through the dielectric layer 356, the fourth passivation layer 354, and the third passivation layer 352 via one or more etching processes to expose a conductive via 370, and then placing or depositing a suitable conductive material in the opening. In some embodiments, a planarization process is performed to planarize the bonding structure 360 ​​so that the upper surface of the bonding structure 360 ​​is flush with the upper surface of the dielectric layer 356 or the upper surface of the bonding layer 358, which may facilitate a direct bonding process.

[0052] Figure 13 shows a cross-sectional view of a semiconductor device 400 according to some embodiments. Semiconductor device 400 is similar to semiconductor device 100, wherein the same reference numerals denote the same elements. In semiconductor device 400, a second etch stop layer 416 may serve as an etch stop layer for both via 328A and trench 328B. In Figure 13, a second passivation layer 418 may have a thickness T3 substantially equal to the desired depth D1 of the via capacitor 320A, although the via capacitor 320A may be manufactured to be larger or shallower than the thickness T3. The thickness T4 of a first passivation layer 414 may be greater than the thickness T3 of the second passivation layer 418 to achieve the goal that the thickness T3 is substantially equal to the desired depth D1 of the via capacitor 320A. In some embodiments, the thickness T4 of the first passivation layer 414 is at least twice the thickness T3 of the second passivation layer 418. Since the second etch stop layer 416 can effectively reduce the etch rate of forming the trench 328B, and the first passivation layer 414 is provided with a sufficiently thick first passivation layer 414, the trench 328B can not penetrate the first passivation layer 414. In some embodiments, the first passivation layer 414, the second etch stop layer 416, and the second passivation layer 418 have the same material as the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318, respectively, and can be formed using a similar method.

[0053] Figure 14 shows a cross-sectional view of a semiconductor device 500 according to some embodiments. Semiconductor device 500 is similar to semiconductor device 400, wherein the same reference numerals denote the same elements. In semiconductor device 500, a second etch stop layer 416 may serve as an etch stop layer for reducing the etch rate of forming vias 328A and trenches 328B. In some embodiments, a third etch stop layer 566 is disposed within a first passivation layer 414 to provide additional protection against trenches 328B penetrating the first passivation layer 414. The third etch stop layer 566 can successfully stop the etching of trenches 328B and allow trenches 328B to fall within the third etch stop layer 566. Alternatively, trenches 328B (or trench capacitors 320B) may still penetrate the third etch stop layer 566, but at a distance from the first etch stop layer 312. The third etch stop layer 566 may be or comprise the same material and thickness as the second etch stop layer 416 and may be formed by a similar method.

[0054] Figure 15 shows a cross-sectional view of a semiconductor device 600 according to some embodiments. Semiconductor device 600 is similar to semiconductor devices 100, 400, or 500, wherein the same reference numerals denote the same elements. In semiconductor device 600, a second etch stop layer 616 may have an opening 616A to allow a conductive via 370 to pass through. The opening 616A of the second etch stop layer 616 is filled by a second passivation layer 318. Therefore, the second etch stop layer 616 can be separated from the conductive via 370 through the second passivation layer 318. The second etch stop layer 616 may comprise a different material than the first passivation layer 314 to have a different etch selectivity compared to the first passivation layer 314. For example, the second etch stop layer 616 may include or may be a high-resistance material, such as silicon carbonitride, silicon carbide, silicon carbonitride oxide, undoped silicon, undoped germanium, undoped silicon germanium, silicon nitride, hafnium oxide, zirconium oxide, or a stacked structure including oxide-nitride-oxide layers (e.g., SiO-SiN-SiO). The second etch stop layer 616 may be formed by a method similar to that used for the second etch stop layer 316.

[0055] Figure 16 shows a cross-sectional view of a semiconductor device 700 according to some embodiments. Semiconductor device 700 is similar to semiconductor devices 100, 400, 500, or 600, wherein the same reference numerals denote the same elements. In semiconductor device 700, a second etch stop layer 716 is or includes a low-resistance material, such as a metallic material or a metal nitride material. In some embodiments, the low-resistance material includes TiN, TaN, W, Ta, Ti, or combinations thereof. The second etch stop layer 716 may have an opening 716A to allow a conductive via 370 to pass through. A second passivation layer 318 may fill the opening 716A. Thus, the second etch stop layer 716 may be spaced from the conductive via 370 through the second passivation layer 318. Furthermore, in addition to the opening 716A, the second etch stop layer 716 also includes the same pattern as the first conductive layer 322 used to define the boundary of the capacitor structure 320. Since the second etch stop layer 716 is in contact with the first conductive layer 322 of the capacitor structure 320, having a pattern corresponding to the first conductive layer 322 can prevent unnecessary short circuits between the capacitor structures 320. For example, as shown in Figure 16, the second etch stop layer 716 includes not only an opening 716A electrically isolated from the conductive via 370, but also an opening 716B electrically isolating the capacitor structures 320 from each other (e.g., isolating via-type capacitor 320A and trench-type capacitor 320B, as shown in Figure 16), wherein openings 716A and 716B are filled by the second passivation layer 318.

[0056] Figure 17 shows a cross-sectional view of a semiconductor device 800 according to some embodiments. Semiconductor device 800 is similar to semiconductor devices 100, 400, 500, 600, or 700, wherein the same reference numerals denote the same elements. In semiconductor device 800, a second etch stop layer 816 is located only below trench capacitor 320B. That is, the second etch stop layer 816 can be used only as an etch stop layer for forming trench 328B. Thus, in some embodiments where via 328A is etched to a deeper depth D3 (e.g., about 400 nm to about 600 nm) below the second etch stop layer 816, the etch rate for forming via 328A is affected by the second etch stop layer 816, thereby reducing the gap G2 between via capacitor 320A and trench capacitor 320B. The gap G2 can be in the range of about 50 nm to about 150 nm, smaller than the depth D3 of via 328A. In some embodiments, the second etch stop layer 816 comprises a high-resistance material, such as silicon carbonitride, silicon carbide, silicon carbonitride oxide, undoped silicon, undoped germanium, undoped silicon germanium, silicon nitride, hafnium oxide, zirconium oxide, or a stacked structure comprising oxide-nitride-oxide layers (e.g., SiO-SiN-SiO). Alternatively, the second etch stop layer 816 is or comprises a low-resistance material, such as a metallic material or a metal nitride material. Low-resistance materials may include TiN, TaN, W, Ta, Ti, or combinations thereof.

[0057] Figure 18 shows a cross-sectional view of a semiconductor package 900 according to some embodiments. In the semiconductor package 900, a semiconductor device 100 is bonded to another semiconductor device 100 via direct bonding. In Figure 18, each semiconductor device 100 may include a bonding structure 360 ​​with its top surface flush with a bonding layer 358. The bonding structures 360 in the semiconductor devices 100 may be bonded via direct contact of a metal-to-metal bond. The bonding layers 358 of the semiconductor devices 100 may be bonded via covalent bonds (e.g., oxide-to-oxide bonds). Although two semiconductor devices 100 are used as examples to illustrate the semiconductor package 900, either semiconductor device 100 may be replaced by semiconductor devices 400, 500, 600, 700, 800, or other suitable semiconductor devices, and may be formed or walked into a capacitor structure 320 in the passivation structure 300. Although not specifically shown in device layer 200 in Figure 1, a through substrate via 984 may be implemented in semiconductor device 100 or other suitable semiconductor device, through substrate 102 to electrically couple device layer 200 to external components.

[0058] Figure 19 shows a cross-sectional view of a semiconductor device 1000 according to some embodiments. In the semiconductor device 1000, a first passivation structure 1350 and a capacitor structure 1320 may be disposed on the back side of the device layer 200 (or the back side of the substrate 102). The capacitor structure 1320 may be similar to the capacitor structure 320 and may be formed by a similar method. The first passivation structure 1350 may be similar to the first passivation structure 310 and may be formed by a similar method. For example, the first passivation structure 1350 and the capacitor structure 1320 may be vertically reversed relative to the first passivation structure 310 and the capacitor structure 320, respectively.

[0059] According to some embodiments, a back-side interconnect structure 1250 may be disposed beneath the first passivation structure 1350 and the capacitor structure 1320 to provide power and / or additional signal connections to the device layer 200. A conductive via 1270 may penetrate the back-side interconnect structure 1250, the capacitor structure 1320, and the first passivation structure 1350 to electrically couple to components in the device layer 200. The back-side interconnect structure 1250 may include conductive features disposed in a dielectric layer, similar to interconnect structure 250. The conductive via 1270 penetrates the first passivation structure 1350 and is physically coupled and / or electrically coupled to the source / drain region 124 in the device layer 200. Furthermore, the back-side interconnect structure 1250 may be formed on the back side of the device layer 200 to provide power and / or additional signal connections to the device layer 200. The back-side interconnect structure 1250 may include power rails 1260, which are conductive lines electrically connecting the source / drain regions 124 in the device layer 200 to a reference voltage, power supply voltage, etc. By placing the power rails on the back side of the semiconductor device 1000 instead of the front side, the following advantages can be achieved. For example, the gate density in the device layer 200 and / or the interconnect density in the interconnect structure 250 can be increased. Furthermore, the back side of the semiconductor device 1000 can accommodate wider power rails, thereby reducing resistance and improving the efficiency of powering the semiconductor device 1000. For example, the width of the power rail 1260 may be at least twice the width of the first layer conductive line 205 of the interconnect structure 250. Placing the capacitor structure 1320 on the back side of the device layer 200 also provides advantages. The capacitor structure 1320 may be electrically coupled to power rails 1260 and / or back conductive vias 1270, which are physically coupled and / or electrically coupled to source / drain regions 124 to regulate the large current supplied from the conductive vias 1270 and / or power rails 1260 before the large current is transmitted to the source / drain regions 124, thereby protecting the devices in device layer 200 (e.g., source / drain regions 124) from damage by large pulses.

[0060] According to some embodiments, a semiconductor device including a capacitor structure is provided. The semiconductor device may include a via capacitor and a trench capacitor formed in a passivation structure above an interconnect structure. The via capacitor includes a layer extending into the via, while the trench capacitor includes a layer extending into the trench. The via capacitor can generate less stress in the semiconductor device, while the trench capacitor can be disposed in a small area. The passivation structure may include an etch stop layer at least located at the location where the trench is to be formed. The etch stop layer can partially or completely resist the etch process for forming the trench. Thus, although the etch rate during trench formation may be greater than the etch rate during via formation, the trench can be located away from the underlying interconnect structure without damaging the underlying interconnect structure when the via reaches its desired depth. Therefore, the semiconductor device can simultaneously include both via capacitors and trench capacitors, improving manufacturing yield. Furthermore, a semiconductor package and a semiconductor device having a back-side interconnect structure including a capacitor structure are also provided.

[0061] In some embodiments, a semiconductor device is provided. The semiconductor device includes: an interconnect structure located above a substrate, wherein the interconnect structure includes conductive features disposed in a dielectric layer; a first passivation layer disposed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; an etch stop layer disposed above the first passivation layer; a second passivation layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from the upper surface of the second passivation layer into the second passivation layer, wherein at least one of the plurality of holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the plurality of trenches includes a first width in a first direction and a second width in a second direction perpendicular to the first direction. The plurality of trenches have a third width less than the first width in an upward direction and a fourth width greater than the second width in a second direction, wherein the plurality of trenches overlap with an etch stop layer in a plan view; a first capacitor structure includes a first conductive layer, a first insulating layer, and a second conductive layer disposed above a second passivation layer and extending into the plurality of trenches, wherein the second conductive layer is located above the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer above the upper surface of the second passivation layer has a curved top surface; and a second capacitor structure includes a third conductive layer, a second insulating layer, and a fourth conductive layer disposed above the second passivation layer and extending into the plurality of trenches. In some embodiments, the bottom of the first conductive layer is located above the etch stop layer, and the bottom of the third conductive layer is located below the etch stop layer. In some embodiments, the third conductive layer is in contact with the etch stop layer, and the first conductive layer is spaced apart from the etch stop layer through the second passivation layer. In some embodiments, the semiconductor device further includes: a conductive via penetrating the second passivation layer, the first passivation layer, and one of the first capacitor structure or the second capacitor structure to electrically couple to a conductive feature of an interconnect structure. In some embodiments, the conductive vias are laterally surrounded by an etch stop layer, and a lateral gap (opening) exists between the conductive vias and the etch stop layer, wherein the lateral gap is filled by a second passivation layer. In some embodiments, the etch stop layer comprises a metallic material or a conductive metal nitride material. In some embodiments, the plurality of holes do not overlap with the etch stop layer in a planar view.

[0062] In some embodiments, a semiconductor device is provided. The semiconductor device includes: a means disposed above a substrate, wherein the means includes a plurality of source / drain features, each of the plurality of source / drain features including a plurality of layers containing the same semiconductor material with different concentrations; a first dielectric layer disposed above the means; an etch stop layer disposed above the first dielectric layer; a second dielectric layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from an upper surface of the second dielectric layer into the second dielectric layer, wherein the plurality of holes are disposed in a first region, the plurality of trenches are disposed in a second region, wherein at least one of the plurality of holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the plurality of trenches includes a third width in the first direction and a fourth width in the second direction, wherein the difference between the first width and the second width is less than the difference between the third width and the fourth width; and a capacitor structure including a first conductive layer, an insulating layer, and a second conductive layer disposed above the upper surface of the second dielectric layer and extending into the plurality of holes and the plurality of trenches, wherein a first occupancy area of ​​the first region is greater than a second occupancy area of ​​the second region. In some embodiments, the bottom of the plurality of trenches is lower than the bottom of the plurality of holes. In some embodiments, the semiconductor device further includes: a conductive via penetrating the capacitor structure, and a second region located between the conductive via and the first region. In some embodiments, the conductive via is laterally surrounded by the first region and the second region. In some embodiments, the bottom of the plurality of trenches is lower than the etch stop layer, and the bottom of the plurality of holes is higher than the etch stop layer. In some embodiments, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer. In some embodiments, the semiconductor device further includes: an insulating fill layer disposed above the capacitor structure and the second dielectric layer; a passivation structure disposed above the insulating fill layer, wherein the conductive via penetrates the insulating layer and includes a protrusion extending in the passivation structure; and a conductive bonding structure disposed in the passivation structure, wherein the conductive bonding structure is exposed from the passivation structure and electrically coupled to the conductive via.

[0063] In some embodiments, a method for forming a semiconductor device is provided. The method includes: forming an interconnect structure over a substrate, wherein the interconnect structure includes conductive features disposed in a dielectric layer; forming a first passivation layer over the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; forming an etch stop layer over the first passivation layer; forming a second passivation layer over the etch stop layer; performing an etching process to form a plurality of holes and a plurality of trenches in the second passivation layer, wherein at least one of the plurality of holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the plurality of trenches includes a third width in the first direction less than the first width and a fourth width in the second direction greater than the second width; and forming a first capacitor structure and a second capacitor structure over the second passivation layer, wherein the first capacitor structure includes a first conductive layer, a first insulating layer and a second conductive layer extending into the plurality of holes, wherein the second conductive layer is disposed over the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer over the second passivation layer has a curved top surface, wherein the second capacitor structure includes a third conductive layer, a second insulating layer and a fourth conductive layer extending into the plurality of trenches, wherein the plurality of trenches overlap with the etch stop layer in a plan view. In some embodiments, the etching process has a first etching rate when forming the plurality of holes and a second etching rate when forming the plurality of trenches, wherein the second etching rate is greater than the first etching rate. In some embodiments, during the etching process, the plurality of holes are at a distance from the etch stop layer when the plurality of trenches penetrate the etch stop layer. In some embodiments, forming the etch stop layer includes: depositing a layer over a first passivation layer; and patterning the layer. In some embodiments, patterning the layer includes removing a first portion of the layer that overlaps with the plurality of holes in a planar view. In some embodiments, the etch stop layer comprises a metallic material or a conductive metal nitride material.

[0064] The foregoing outlines the features of many embodiments to enable those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments disclosed herein to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, and modifications can be made to the embodiments disclosed herein without departing from the spirit and scope of the appended claims.

[0065] 100: Semiconductor devices 102:Substrate 114: Quarantine Area 122: Gate spacer 123: Fin sidewall spacers 124: Source / Drain (S / D) Region 126: Contact Etching Stop Layer 128: Interlayer dielectric layer 136: Gate dielectric layer 138: Gate electrode layer 140: Gate Stacking 142: S / D Contact 144: Silicon layer 200: Device Layer 202: Dielectric layer 204: Conductivity characteristics 205: Conductive wire 206: Conductive via 250: Interconnection Structure 300: Passivation structure 310: First passivation structure 312: First etch stop layer 314: First passivation layer 316: Second etch stop layer 318: Second passivation layer 320: Capacitor Structure 320A: Through-hole capacitor 320B: Trench capacitor 320C: Hybrid capacitor 320D: Virtual MIM Structure 322: First conductive layer 324: Insulation layer 326: Second conductive layer 328A: Hole 328B: Groove 329A: Hole Area 329B: Trench area 329C: Through-hole area 330: Quarantine Area 332: Fill layer 350: Second passivation structure 352: Third passivation layer 354: Fourth passivation layer 356: Dielectric layer 358: Bonding layer 360: Joint structure 370: Conductive Through-hole 372: Main conductive material 374: Barrier Layer 376: Seed layer 400: Semiconductor Devices 414: First passivation layer 416: Second etch stop layer 418: Second passivation layer 500: Semiconductor Devices 566: Third Etching Stop Layer 600: Semiconductor Devices 616: Second etch stop layer 616A: Open 700: Semiconductor Devices 716: Second Etching Stop Layer 716A: Open 716B: Open 800: Semiconductor Device 816: Second etch stop layer 900: Semiconductor Packaging 984:Substrate perforation 1000: Semiconductor Devices 1250: Backside interconnect structure 1260: Power rail 1270: Conductive Through-hole 1320: Capacitor Structure 1350: First passivation structure X, Y, Z: Axes D1: Depth D2: Depth D3: Depth G1: Gap G2: Gap S1: First spacing S2: Second spacing T1: Thickness T2: Thickness T3: Thickness T4: Thickness W1: First width W2: Second width W3: Third width W4: Fourth Width A-A': Cross section

Claims

1. A semiconductor device, comprising: An interconnect structure is located above a substrate, wherein the interconnect structure includes a conductive feature disposed in a dielectric layer; A first passivation layer disposed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; an etch stop layer disposed above the first passivation layer; a second passivation layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from an upper surface of the second passivation layer into the second passivation layer, wherein at least one of the holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the trenches includes a third width in the first direction less than the first width and a fourth width in the second direction greater than the second width, wherein the trenches overlap the etch stop layer in a plan view; a first capacitor structure including a first conductive layer, a first insulating layer, and a second conductive layer disposed above the second passivation layer and extending into the holes, wherein the second conductive layer is located above the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer above the upper surface of the second passivation layer has a curved top surface; And a second capacitor structure, including a third conductive layer, a second insulating layer and a fourth conductive layer disposed above the second passivation layer and extending into the trenches.

2. The semiconductor device as claimed in claim 1, wherein the bottom of the first conductive layer is located above the etch stop layer, and the bottom of the third conductive layer is located below the etch stop layer.

3. The semiconductor device as claimed in claim 1, wherein the third conductive layer is in contact with the etch stop layer, and the first conductive layer is separated from the etch stop layer through the second passivation layer.

4. The semiconductor device as claimed in claim 1 further includes a conductive via penetrating the second passivation layer, the first passivation layer, and one of the first capacitor structure or the second capacitor structure to be electrically coupled to the conductive feature of the interconnect structure.

5. The semiconductor device as claimed in claim 4, wherein the conductive via is laterally surrounded by the etch stop layer and a lateral gap exists between the conductive via and the etch stop layer, wherein the lateral gap is filled by the second passivation layer.

6. The semiconductor device as claimed in claim 5, wherein the etch stop layer comprises a metallic material or a conductive metal nitride material.

7. The semiconductor device as claimed in claim 1, wherein the vias do not overlap with the etch stop layer in the plan view.

8. A semiconductor device, comprising: An apparatus disposed above a substrate, wherein the apparatus includes a plurality of source / drain features, each of the source / drain features including a plurality of layers comprising the same semiconductor material with different concentrations; a first dielectric layer disposed above the apparatus; an etch stop layer disposed above the first dielectric layer; a second dielectric layer disposed above the etch stop layer; a plurality of vias and a plurality of trenches extending from an upper surface of the second dielectric layer into the second dielectric layer, wherein the vias are disposed in a first region, and the trenches are disposed in a second region, wherein at least one of the vias includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the trenches includes a third width in the first direction and a fourth width in the second direction, wherein the difference between the first width and the second width is less than the difference between the third width and the fourth width; And a capacitor structure including a first conductive layer, an insulating layer and a second conductive layer disposed above the upper surface of the second dielectric layer and extending into the holes and trenches, wherein a first occupancy area of ​​the first region is larger than a second occupancy area of ​​the second region.

9. The semiconductor device as claimed in claim 8, wherein the bottom of the trenches is lower than the bottom of the holes.

10. The semiconductor device as claimed in claim 8 further includes a conductive via penetrating the capacitor structure, and the second region is located between the conductive via and the first region.

11. The semiconductor device as claimed in claim 10, wherein the conductive via is laterally surrounded by the first region and the second region.

12. The semiconductor device as claimed in claim 8, wherein the bottom of the trenches is below the etch stop layer and the bottom of the holes is above the etch stop layer.

13. The semiconductor device as described in claim 8, further comprising: An insulating filler layer is disposed above the capacitor structure and the second dielectric layer; a passivation structure is disposed above the insulating filler layer, wherein a conductive via penetrates the insulating layer and includes a protrusion extending in the passivation structure; and a conductive bonding structure is disposed in the passivation structure, wherein the conductive bonding structure is exposed from the passivation structure and electrically coupled to the conductive via.

14. A method of forming a semiconductor device, the method comprising: An interconnect structure is formed over a substrate, wherein the interconnect structure includes a conductive feature disposed in a dielectric layer; A first passivation layer is formed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; an etch stop layer is formed above the first passivation layer; a second passivation layer is formed above the etch stop layer. An etching process is performed to form a plurality of holes and a plurality of trenches in the second passivation layer, wherein at least one of the holes includes a first width in a first direction and a second width in a second direction perpendicular to the first direction, and at least one of the trenches includes a third width in the first direction that is smaller than the first width and a fourth width in the second direction that is larger than the second width; and a first capacitor structure and a second capacitor structure are formed over the second passivation layer, wherein the first capacitor structure includes a first conductive layer, a first insulating layer and a second conductive layer extending into the holes, wherein the second conductive layer is disposed over the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer over the second passivation layer has a curved top surface, wherein the second capacitor structure includes a third conductive layer, a second insulating layer and a fourth conductive layer extending into the trenches, wherein the trenches overlap with the etch stop layer in a planar view.

15. The method of claim 14, wherein the etching process has a first etching rate when forming the holes and a second etching rate when forming the trenches, wherein the second etching rate is greater than the first etching rate.

Images