Semiconductor device structure and methods of forming the same

Abstract

The embodiments disclosed herein provide a semiconductor device structure and a method for forming the same. The structure includes a gate electrode layer disposed above a semiconductor layer, a source / drain region disposed adjacent to the semiconductor layer, an interlayer dielectric (ILD) layer disposed above the source / drain region, a conductive feature disposed in the ILD layer above the drain / source region, a first dielectric layer disposed between the gate electrode layer and the conductive feature, a second dielectric layer different from the first dielectric layer disposed between the first dielectric layer and the gate electrode layer, a contact etch stop layer disposed between the second dielectric layer and the gate electrode layer, and a spacer disposed between the contact etch stop layer and the gate electrode layer.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of integrated circuits, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) generally increases, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) decreases. This reduction typically benefits production efficiency and reduces associated costs. This reduction also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, it is necessary to improve the processing and manufacturing of ICs. [Summary of the Invention]

[0004] None

Implementation Method

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "above," "on," "top," "upper," and the like may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s) or feature(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive symbols used herein may be interpreted similarly accordingly.

[0008] While the embodiments disclosed herein are discussed in relation to nanostructured channel FETs, such as gate all-around (GAA) FETs, such as horizontal gate all-around (HGAA) FETs or vertical gate all-around (VGAA) FETs, some implementations of the present disclosure can be used in other processes and / or other devices, such as planar FETs, fin FETs, and other suitable devices. Those skilled in the art will readily understand that other modifications can be contemplated within the scope of this disclosure. In the case of adapting to a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more optical lithography processes, including dual patterning or multiple patterning processes, can be used to pattern the structure. Generally, dual or multiple patterning processes combine optical lithography with self-alignment processes, allowing for the production of patterns with, for example, smaller pitches than those achievable using a single direct optical lithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are then formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a GAA structure.

[0009] Figures 1 through 13G illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure. It is understood that additional embodiments of the method may provide additional operations before, during, and after the processes shown in Figures 1 through 13G, and some of the operations described below may be replaced or eliminated. The order of operations / processes is not limited and may be interchanged.

[0010] Figures 1 through 6 are perspective views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a stack 104 of semiconductor layers formed over a front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0011] The substrate 101 may include various regions that are doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0012] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices, such as nanostructure channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, any of the semiconductor layers 106, 108 may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0013] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers in the stack of semiconductor layers 104 can be performed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0014] In a later manufacturing stage, the first semiconductor layer 106 or portions thereof may form one or more nanostructure channels of the semiconductor device structure 100. The term nanostructure is used herein to refer to any portion of material having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Thus, the term refers to elongated material portions with circular or substantially circular cross-sections, and includes beam-shaped or strip-shaped material portions, such as cylindrical or substantially rectangular cross-sections. The one or more nanostructure channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0015] Each first semiconductor layer 106 may have a thickness in the range of about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range of about 2 nm to about 50 nm. As shown in Figure 1, three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged for illustrative purposes and are not intended to limit the scope of the claims specifically referenced. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the stack 104 of semiconductor layers, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0016] In Figure 2, the fin structure 112 is formed from a stack 104 of semiconductor layers. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the stack 104 of semiconductor layers using multiple patterning operations including optical lithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The optical lithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process may be used to pattern the photoresist layer to form a masking element. The etching process forms trenches 114 in the unprotected area, penetrating the hard mask layer, the stack 104 of semiconductor layers, and into the substrate 101, thereby leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof.

[0017] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Next, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching-back, is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorinated silica glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0018] In Figure 4, the insulating material 118 is recessed to form an isolation region 120. The recesses in the insulating material 118 expose portions of the fin structures 112, such as the stack 104 of semiconductor layers. The recesses in the insulating material 118 reveal trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or a combination thereof. The top surface of the insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from the substrate 101.

[0019] In Figure 5, one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the spacers 138 may be formed by conformally depositing one or more layers for the spacers 138 and anisotropically etching the one or more layers. In some embodiments, spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be configured along the X direction. In some embodiments, the contact polypitch (CPP) is the minimum center-to-center distance between adjacent sacrificial gate electrode layers 134, ranging from about 35 nm to about 100 nm.

[0020] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The spacer 138 may be made of dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. In some embodiments, the k-value of the spacer 138 may be in the range of about 4 to about 10.

[0021] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as a channel region of the semiconductor device structure 100.

[0022] In Figure 6, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the spacer 138 is recessed above, below, or above the top surface of the isolation region 120. The recess 119 of the portion of the fin structure 112 can be achieved by an etching process (or an isotropic or anisotropic etching process), and the etching process can be selective relative to one or more crystal planes of the substrate 101. The etching process can be dry etching, such as RIE, NBE, or similar, or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0023] Figures 7A, 7B, and 7C are cross-sectional side views of the semiconductor device structure 100 taken along lines AA, BB, and CC of Figure 6, respectively.

[0024] Figures 8A, 8B, and 8C are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments. As shown in Figure 8A, edge portions of each second semiconductor layer 108 (e.g., second semiconductor layers 108-1, 108-2, and 108-3) in the stack of semiconductor layers 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layers 108 forms cavities. In some embodiments, portions of the second semiconductor layers 108 are removed by a selective wet etching process. In cases where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0025] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 may be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, the k-value of the dielectric spacers 144 may be in the range of about 4 to about 10. The dielectric spacers 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), followed by anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers the spacers 144 along the X direction.

[0026] Figures 9A, 9B, and 9C are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along lines AA, BB, and CC of Figure 6, according to some embodiments. As shown in Figures 9A and 9C, a source / drain (S / D) region 146 is formed from a substrate portion 116. The S / D region 146 may be grown vertically and horizontally to form a facet, which may correspond to a crystal plane of the material used for the substrate portion 116. In this disclosure, the source region and drain region are used interchangeably and have substantially the same structure. Furthermore, the source / drain region may refer individually or jointly to a source or drain, depending on the context. The S / D region 146 may be made of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or of Si, SiGe, and Ge for a p-channel FET. For p-channel FETs, p-type dopants, such as boron (B), may also be included in the S / D region 146. The S / D region 146 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0027] Figures 10A, 10B, and 10C are cross-sectional side views, taken along lines AA, BB, and CC of Figure 6, respectively, of one of the various stages of manufacturing the semiconductor device structure 100 according to some embodiments. In Figures 10A, 10B, and 10C, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. CESL 162 may include a nitrogen-containing material, such as silicon nitride, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, CESL 162 has a k value ranging from about 7 to about 10. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material used for the ILD layer 164 may include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the ILD layer 164. The ILD layer 164 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, the k-value of the ILD layer 164 is less than 4, such as from about 2.5 to about 3.5. In some embodiments, after the formation of the ILD layer 164, the semiconductor device structure 100 may be subjected to a thermal treatment to anneal the ILD layer 164.

[0028] After the ILD layer 164 is formed, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in Figures 10A and 10B.

[0029] Figures 11A, 11B, and 11C are cross-sectional side views of one of the various stages of manufacturing a semiconductor device structure 100, taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments. As shown in Figures 11A and 11B, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms openings between spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 134, but without removing the spacer 138, ILD layer 164, or CESL 162.

[0030] The second semiconductor layer 108 can be removed using a selective wet etching process. In cases where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe without substantially affecting the dielectric materials of the Si, spacers 138, and dielectric spacers 144. In one embodiment, a wet etchant can be used to remove the second semiconductor layer 108. Wet etchants include, but are not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), dry etchants such as fluorine-based gases (e.g., F2) or chlorine-based gases (e.g., Cl2), or any suitable isotropic etchant.

[0031] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interfacial layer (IL) 169 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material (such as silicon oxide, silicon nitride), or high-k dielectric material, other suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiN, HfTaO, HfTiO, HbZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive materials, such as polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combinations thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited above the surface of the ILD layer 164. The gate dielectric layer 170 and gate electrode layer 172 formed above the ILD layer 164 are then removed by means of, for example, CMP, until the top surface of the ILD layer 164 is exposed.

[0032] Figures 12A, 12B, and 12C are cross-sectional side views of one of the various stages of manufacturing a semiconductor device structure 100, taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments. As shown in Figures 12B and 12C, an etch stop layer 202 is formed on the ILD layer 164 and the gate structure 174, and another ILD layer 204 is formed on the etch stop layer 202. The etch stop layer 202 may include the same material as CESL 162, and the ILD layer 204 may include the same material as ILD layer 164.

[0033] Figures 13A to 13G are cross-sectional side views taken along line AA of Figure 6 according to some embodiments, showing various stages of manufacturing the semiconductor device structure 100. As shown in Figure 13A, openings 206 are formed in the ILD layer 204, etch stop layer 202, ILD layer 164, and CESL 162 to expose the S / D region 146. The openings 206 may be formed by one or more etching processes, such as dry etching processes, wet etching processes, or combinations thereof. Next, as shown in Figure 13B, a dielectric layer 208 is formed on the exposed surface of the semiconductor device structure 100. The dielectric layer 208 may be a carbon-containing layer having a k value of less than about 4, for example, from about 2.5 to about 3.9. In some embodiments, the dielectric layer 208 comprises SiOC or SiOCN or is made therefrom. In some embodiments, the k-value of dielectric layer 208 is less than the k-value of CESL 162, spacer 138, and dielectric spacer 144. In some embodiments, a cyclic CVD process is used to form dielectric layer 208 in order to retain carbon in dielectric layer 208 during subsequent processes. Furthermore, a cyclic CVD process can form a substantially conformal dielectric layer 208, as shown in Figure 13B.

[0034] In some embodiments, the cyclic CVD process is a cyclic PECVD process, including introducing a first precursor into a processing chamber in which the semiconductor device structure 100 is disposed. The first precursor may include silicon and carbon. In some embodiments, the first precursor includes Si-C-Si bonds, such as Si-C-Si-(CH3)3. In some embodiments, the first precursor includes Si-CH3 bonds, such as methylsilane. In some embodiments, the first precursor is introduced into the processing chamber, and a silicon- and carbon-containing plasma is formed in the processing chamber. The silicon- and carbon-containing material from the plasma bonds to the surface of the semiconductor device structure 100. Next, a cleanup process is performed to remove any first precursor that is not bonded to the surface of the semiconductor device structure 100 from the processing chamber. Then, a second precursor is introduced into the processing chamber. The second precursor may be an oxygen-containing precursor, and an oxygen-containing plasma is formed in the processing chamber. In some embodiments, the oxygen-containing precursor includes O2 gas. In some embodiments, the oxygen-containing precursor also includes nitrogen gas, such as NO2 gas. The oxygen-containing material from the oxygen-containing plasma reacts with silicon- and carbon-containing materials to form a first layer. In some embodiments, the first precursor is selected such that the first layer has no reaction sites for subsequent silicon- and carbon-containing materials. For example, the plasma-excited species of the first precursor (Si-C-Si-(CH3)3 or methylsilane) can react with the plasma-excited species of the second precursor (O2 gas or NO2 gas) to form Si-C-Si-O, Si-CO, Si-C-Si-NO, or Si-C-NO, and the first layer includes SiOC or SiOCN. Introducing the first and second precursors into the processing chamber and forming the first layer is one cycle of a cyclic CVD process.

[0035] This cycle is repeated after another purification process to remove any second precursor that has not reacted with the first precursor from the processing chamber. For example, the first precursor is introduced into the processing chamber, and plasma is formed in the processing chamber. As described above, the first layer does not have reaction sites for the plasma-activated species of the first precursor, and the plasma-activated material in the first precursor is held on the first layer by van der Waals forces. In some embodiments, in order to have a sufficient amount of plasma-activated species of the first precursor on the first layer, the flow rate of the first precursor into the processing chamber can be very high, such as from about 100 standard cubic centimeters per minute (sccm) to about 300 sccm. After another purification process, the second precursor is introduced into the processing chamber, plasma is formed from the second precursor, and a second layer is formed on the first layer. The second layer can be formed in the same manner as the first layer. However, the first layer and the second layer are connected by van der Waals forces. Compared to the ALD process, layers formed by cycling the ALD process have reaction sites for the subsequent introduction of precursors in subsequent cycles of the ALD process, and the layers formed by cycling are bonded by covalent bonds. In some embodiments, the distance between the first and second layers formed by the cyclic CVD process is greater than the distance between the layers formed by the ALD process. As a result, the layers formed by the cyclic CVD process are porous and have a lower k-value. In some embodiments, the dielectric layer 208 and the spacer 138 comprise the same material, such as SiOCN, but because the dielectric layer 208 is more porous, the k-value of the dielectric layer 208 is smaller than the k-value of the spacer 138.

[0036] The cyclic CVD process is repeated one or more times to form additional layers, and the layers formed by the cyclic CVD process form a dielectric layer 208. In other words, the dielectric layer 208 comprises multiple layers formed by multiple cycles of the cyclic CVD process. The number of cycles is based on a predetermined thickness of the dielectric layer 208. In some embodiments, the dielectric layer 208 has a thickness ranging from about 3 nm to about 5 nm, and the number of cycles ranges from about 300 to about 500. After the predetermined thickness of the dielectric layer 208 is reached, a processing process is performed on the dielectric layer 208 to crosslink some or all of the individual layers formed by the cycles of the cyclic CVD process. In some embodiments, the processing process includes exposing the dielectric layer 208 to a hydrogen-containing plasma. Due to the crosslinking of these layers, more Si-C-Si bonds are formed. In some embodiments, the processing process is performed for the duration during which all layers of the dielectric layer 208 are crosslinked. As a result, the concentration of Si-C-Si remains substantially constant throughout the dielectric layer 208. In some embodiments, the processing is performed over a period of time during which the dielectric layer 208 is cross-linked. Therefore, as shown in Figure 13B, the Si-C-Si concentration decreases from the surface of the dielectric layer 208 exposed in the opening 206 to the surface of the dielectric layer 208 adjacent to the gate electrode layer 172. In some embodiments, a higher Si-C-Si concentration results in a higher k-value. Therefore, in some embodiments, the k-value of the dielectric layer 208 varies. For example, the k-value of the dielectric layer 208 decreases from the surface of the dielectric layer 208 exposed in the opening 206 to the surface of the dielectric layer 208 adjacent to CESL 162.

[0037] As shown in Figure 13C, a portion of the dielectric layer 208 formed on the horizontal surface of the semiconductor device structure 100 is removed. In some embodiments, an anisotropic etching process is performed to remove a portion of the dielectric layer 208. Next, an ashing process is performed to remove any byproducts formed during the anisotropic etching process. In some embodiments, the dielectric layer 208 is not formed by the aforementioned cyclic CVD process and processing, and the dielectric layer 206 primarily comprises Si-CH3 bonds rather than Si-C-Si bonds. The ashing process can remove carbon from the Si-CH3 bonds. However, the ashing process does not remove carbon from the Si-C-Si bonds. Therefore, in some embodiments, as a result of the cyclic CVD process and processing, the carbon concentration of the dielectric layer 208 is not affected by the ashing process.

[0038] After the ashing process, the semiconductor device structure 100 may be transferred to another tool or processing chamber for subsequent processes, and the semiconductor device structure 100 may be exposed to air. As a result, the S / D region 146 may be oxidized. For example, an oxide layer may be formed on the S / D region 146. To remove the oxide layer formed on the S / D region 146, an etching process may be performed. The etching process may be any suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the dielectric layer 208 is not formed by a cyclic CVD process and processing process; the carbon in the dielectric layer 208 is removed by an ashing process, and the etching process that removes the oxide layer also removes the dielectric layer. In some embodiments, the dielectric layer 208 is formed by a cyclic CVD process and a processing procedure. Due to the Si-C-Si bonds, the carbon in the dielectric layer 208 is unaffected by the ashing process, and the etching process that removes the oxide portion of the S / D region 146 does not substantially affect the dielectric layer 208. Therefore, the dielectric layer 208 remains between the gate electrode layer 172 and the subsequently formed conductive feature 214 (Figure 13F). The low k-value of the dielectric layer 208 can lead to reduced capacitance and improved alternating current (AC) performance.

[0039] As shown in Figure 13D, a silicon layer 210 is selectively formed on the S / D region 146. In some embodiments, the silicon layer 210 is formed by selectively depositing a metal layer on the S / D region 146 and reacting it with the S / D region 146. For example, a titanium layer may be selectively deposited on the S / D region 146 at a processing temperature of about 400 degrees Celsius, and the titanium layer reacts with the S / D region 146 at the processing temperature to form a TiSi layer. In some embodiments, the dielectric layer 208 is made of SiOC, and no metal layer is formed on the dielectric layer 208. For example, the metal layer is a titanium layer, and TiCl4 is used as a precursor for forming the metal layer. TiCl4 is not formed on the oxide material of the dielectric layer 208. In some embodiments, the dielectric layer 208 is made of SiOCN, and a small amount of metal layer 211 is formed on the dielectric layer 208, as shown in Figure 13D-1. As shown in Figure 13D-1, the metal layer 211 may be a discontinuous layer, and each segment of the metal layer 211 has a thickness ranging from about 0.5 nm to about 1 nm.

[0040] In some embodiments, an incubation delay exists on the dielectric layer 208 when the metal layer is formed. For example, no metal layer grows on the dielectric layer 208 until the metal layer formed on the S / D region 146 reaches about 40 angstroms. Therefore, in some embodiments, the thickness of the metal layer is less than about 40 angstroms to ensure that no metal layer is formed on the dielectric layer 208. As a result, in some embodiments, the silicon layer 210 has a thickness ranging from about 20 angstroms to about 40 angstroms.

[0041] In some embodiments, the dielectric layer 208 comprises SiN, and a metal layer is also formed on the dielectric layer 208. For example, TiCl4 is formed on the nitride material of the dielectric layer 208 to form a titanium layer. As a result, an etching process can be performed to remove the metal layer from the dielectric layer 208. The etching process may damage the silicate layer 210. Therefore, by forming the dielectric layer 208 with SiOC or SiOCN, damage to the silicate layer 210 is minimized.

[0042] As shown in Figure 13E, the metal layer 212 is formed on the silicate layer 210 in a bottom-up manner. In some embodiments, the metal layer 212 comprises fluorine-free tungsten (FFW). After the metal layer 212 is formed, a cleaning process can be performed to remove any metal layer 212 that may have formed on the dielectric layer 208. The metal layer 211 (Figure 13D-1) can also be removed by a cleaning process. The cleaning process can be any suitable cleaning process. In some embodiments, the cleaning process is a wet cleaning process using hot deionized water.

[0043] As shown in Figure 13F, a conductive feature 214 is formed in the opening 206. The conductive feature 214 is electrically connected to the S / D region 146 through the silicon layer 210 and the metal layer 212. The conductive feature 214 may include any conductive material, such as Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, TaN, or combinations thereof, or other suitable materials. The conductive feature 214 may be formed by any suitable process, such as PVD or ECP. Next, as shown in Figure 13G, a planarization process such as CMP is performed to remove the ILD layer 204. As a result, as shown in Figure 13G, the top surface of the conductive feature 214 is substantially coplanar with the top surface of the etch stop layer 202. As described above, in some embodiments, the dielectric layer 208 has a Si-C-Si concentration distribution that decreases in the direction from the conductive feature 214 to the gate electrode layer 172.

[0044] Figure 13G-1 illustrates an embodiment in which a discontinuous metal layer 211 is retained in the structure. In some embodiments, the metal layer 211 and the conductive feature 214 comprise different materials.

[0045] Figure 13G-2 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100, taken along line CC of Figure 6 according to some embodiments. Figure 13G-1 illustrates a semiconductor device structure 100 at the same manufacturing stage as the semiconductor device structure 100 shown in Figure 13G. As shown in Figure 13G-1, conductive features 214 are formed in the ILD layer 164. In some embodiments, conductive features 214 and metal layer 212 comprise the same material, and conductive features 214 and metal layer 212 are considered as a single structure.

[0046] Figures 14A, 14B, 14C, 14D, and 14E are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100, taken along line AA of Figure 6 according to an alternative embodiment. Figure 14A illustrates the semiconductor device structure 100 at the same manufacturing stage as the semiconductor device structure 100 shown in Figure 13D. As shown in Figure 14A, a silicon layer 210 is selectively formed on the S / D region 146. Next, as shown in Figure 14B, a metal layer 220 is formed on the silicon layer 210 and the dielectric layer 208. In some embodiments, the metal layer 220 is formed by a PVD process, and therefore the thickness of the portion of the metal layer 220 formed on the dielectric layer 208 is less than the thickness of the portion of the metal layer 220 formed on the silicon layer 210, as shown in Figure 14B. The metal layer 220 may include any suitable material, such as W, Ru, Co, or Cu.

[0047] Next, as shown in Figure 14C, an etch-back process is performed to remove the portion of the metal layer 220 formed on the dielectric layer 208. The etch-back process can be controlled such that the portion of the metal layer 220 formed on the silicon layer 210 is substantially unaffected. For example, the etch-back process can be an isotropic etching process with low or no bias power. In some embodiments, the etch-back process is a wet etching process including an oxidant and an acid, and no bias power is applied.

[0048] As shown in Figure 14D, a metal layer 212 is formed on the metal layer 220 and the silicate layer 210. In some embodiments, the silicate layer 210 is covered by the metal layer 220, and the metal layer 212 does not contact the silicate layer 210. In some embodiments, the metal layer 212 is selectively formed on the metal layer 220 and then laterally grown over the silicate layer 210. As a result, the thickness of the metal layer 212 can vary. For example, as shown in Figure 14D, the central portion of the metal layer 212 formed over the metal layer 220 may have a thickness greater than the thickness of the edge portion of the metal layer 212 formed over the silicate layer 210. Next, as shown in Figure 14E, a conductive feature 214 is formed in the opening 206, and a planarization process is performed to remove the ILD layer 204.

[0049] Figures 15A, 15B, 15C, and 15D are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100, taken along line AA of Figure 6 according to an alternative embodiment. As shown in Figure 15A, after forming openings 206 in ILD layer 204, etch stop layer 202, ILD layer 164, and CESL 162, a first dielectric layer 230 and a second dielectric layer 232 are formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the first dielectric layer 230 has a low k-value, such as from about 2.5 to about 3.9, and the second dielectric layer 232 is made of a material capable of withstanding subsequent ashing and etching processes. In some embodiments, the first dielectric layer 230 comprises the same material as ILD layer 164. Therefore, the first dielectric layer 230 has a low k-value but can be removed by subsequent ashing and etching processes. The second dielectric layer 232 protects the first dielectric layer 230 from subsequent ashing and etching processes, and the second dielectric layer 232 may have a higher k-value than the first dielectric layer 230. In some embodiments, the second dielectric layer 232 is made of SiN. Although the SiN layer is unaffected by subsequent ashing and etching processes, the k-value of the SiN layer is also high, such as about 6.8. Furthermore, a metal layer for forming the silicon layer 210 may be formed on the SiN layer. Therefore, in some embodiments, the second dielectric layer 232 comprises the same material as the dielectric layer 208 and is formed by the same process as the dielectric layer 208. In some embodiments, the first dielectric layer 230 has a thickness ranging from about 1 nm to 2 nm, and the second dielectric layer 232 has a thickness ranging from 2 nm to 3.5 nm.

[0050] As shown in Figure 15B, portions of the first dielectric layer 230 and the second dielectric layer 232 formed on the horizontal surface are removed. In some embodiments, two anisotropic etching processes are performed to remove portions of the dielectric layers 230 and 232. For example, a first anisotropic etching process is performed to remove portions of the second dielectric layer 232 formed on the horizontal surface, followed by a second anisotropic etching process to remove portions of the first dielectric layer 230 formed on the horizontal surface. Next, an ashing process is performed to remove any byproducts formed during the anisotropic etching process, and an etching process is performed to remove the oxide layer formed on the S / D region 146. As described above, the second dielectric layer 232 is unaffected by the ashing and etching processes.

[0051] As shown in Figure 15C, a silicate layer 210 is selectively formed on the S / D region 146, a metal layer 212 is formed on the silicate layer 210, and a conductive feature 214 is formed on the metal layer 212. In some embodiments, a metal layer 220 (Figure 14C) is first formed on the silicate layer 210, and a metal layer 212 is formed on the metal layer 220. Next, as shown in Figure 15D, a planarization process is performed to remove the ILD layer 204.

[0052] Embodiments of this disclosure provide a semiconductor device structure 100 including a dielectric layer 208 made of a low-k dielectric material (such as SiOC or SiOCN). Some embodiments offer advantages. For example, the dielectric layer 208 is disposed between a gate electrode layer 172 and a conductive feature 214, and capacitance is reduced due to the low k value. Furthermore, the SiOC or SiOCN of the dielectric layer 208 can enable selective deposition of the silica layer 210, thereby reducing the risk of damaging the silica layer 210 when it is formed indiscriminately.

[0053] One embodiment is a semiconductor device structure. The structure includes a gate electrode layer disposed above a semiconductor layer, a source / drain region disposed adjacent to the semiconductor layer, an interlayer dielectric (ILD) layer disposed above the source / drain region, a conductive feature disposed in the ILD layer above the source / drain region, and a first dielectric layer disposed between the gate electrode layer and the conductive feature. The first dielectric layer has a Si-C-Si concentration distribution that decreases in the direction from the conductive feature to the gate electrode layer.

[0054] Another embodiment is a semiconductor device structure. The structure includes a gate electrode layer disposed above a semiconductor layer, a source / drain region disposed adjacent to the semiconductor layer, an interlayer dielectric (ILD) layer disposed above the source / drain region, a conductive feature disposed in the ILD layer above the source / drain region, a first dielectric layer disposed between the gate electrode layer and the conductive feature, a second dielectric layer different from the first dielectric layer disposed between the first dielectric layer and the gate electrode layer, a contact etch stop layer disposed between the second dielectric layer and the gate electrode layer, and a spacer disposed between the contact etch stop layer and the gate electrode layer.

[0055] Another embodiment is a method. The method includes forming source / drain regions, depositing a contact etch stop layer (CESL) over the source / drain regions, depositing an interlayer dielectric (ILD) layer over the CESL, forming openings in the ILD layer and the CESL to expose the source / drain regions, and depositing a dielectric layer in the openings by a cyclic chemical vapor deposition process. The deposition of the dielectric layer includes depositing a first layer in the openings, depositing a second layer on the first layer, wherein the first layer and the second layer are connected by van der Waals forces, and performing a processing step to crosslink the first layer and the second layer. The method further includes removing a portion of the dielectric layer to expose the source / drain regions and selectively forming a silicon layer on the source / drain regions.

[0056] The foregoing summarizes the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The features disclosed herein are best understood by reading them in conjunction with the accompanying drawings from the following detailed description. It should be noted that, in accordance with industry standards, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description. Figures 1, 2, 3, 4, 5, and 6 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 7A, 8A, 9A, 10A, 11A, and 12A are cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line AA of Figure 6 according to some embodiments. Figures 7B, 8B, 9B, 10B, 11B, and 12B are cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB of Figure 6 according to some embodiments. Figures 7C, 8C, 9C, 10C, 11C, and 12C are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figures 13A, 13B, 13C, 13D, 13D-1, 13E, 13F, 13G, and 13G-1 are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 13G-2 is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figures 14A, 14B, 14C, 14D, and 14E are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to alternative embodiments. Figures 15A, 15B, 15C, and 15D are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to an alternative embodiment. [Biomaterial Storage]

[0058] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor device structure comprising: a gate electrode layer disposed above a semiconductor layer; a source / drain region disposed adjacent to the semiconductor layer; an interlayer dielectric layer disposed above the source / drain region; a conductive feature disposed in the interlayer dielectric layer above the source / drain region; and a first dielectric layer disposed between the gate electrode layer and the conductive feature, wherein the first dielectric layer has a Si-C-Si concentration distribution that decreases in a direction from the conductive feature to the gate electrode layer.

2. The semiconductor device structure as described in claim 1 further includes a silicon layer disposed between the source / drain region and the conductive feature.

3. The semiconductor device structure as described in claim 2 further includes a metal layer disposed between the silicate layer and the conductive feature.

4. The semiconductor device structure as described in claim 1, further comprising a second dielectric layer disposed between the first dielectric layer and the gate electrode layer.

5. A semiconductor device structure comprising: a gate electrode layer disposed above a semiconductor layer; a source / drain region disposed adjacent to the semiconductor layer; an interlayer dielectric layer disposed above the source / drain region; a conductive feature disposed in the interlayer dielectric layer above the source / drain region; a first dielectric layer disposed between the gate electrode layer and the conductive feature; a second dielectric layer, different from the first dielectric layer, disposed between the first dielectric layer and the gate electrode layer; a contact etch stop layer disposed between the second dielectric layer and the gate electrode layer; and a spacer disposed between the contact etch stop layer and the gate electrode layer, wherein the first dielectric layer has a Si-C-Si concentration distribution that decreases in a direction from the conductive feature to the second dielectric layer.

6. The semiconductor device structure as claimed in claim 5, wherein the first and second dielectric layers and the contact etch-stop layer are disposed above the source / drain region.

7. The semiconductor device structure as described in claim 6, wherein the spacer is disposed above the semiconductor layer.

8. A method of forming a semiconductor device structure, comprising: forming a source / drain region; depositing a contact etch-stop layer over the source / drain region; depositing an interlayer dielectric layer over the contact etch-stop layer; forming an opening in the interlayer dielectric layer and the contact etch-stop layer to expose the source / drain region; depositing a dielectric layer in the opening by a cyclic chemical vapor deposition process, comprising: depositing a first layer in the opening; depositing a second layer on the first layer, wherein the first layer and the second layer are connected by van der Waals forces; and performing a processing step to crosslink the first layer and the second layer; removing a portion of the dielectric layer to expose the source / drain region; and selectively forming a silicon layer on the source / drain region.

9. The method as described in claim 8, wherein the dielectric layer deposited in the opening by the cyclic chemical vapor deposition process further comprises depositing a third layer on the second layer, wherein the second layer and the third layer are connected by van der Waals force.

10. The method as described in claim 8 further includes performing an ashing process after the removal of the portion of the dielectric layer and before the selective formation of the silica layer.

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