Semiconductor structure and method of forming the same

Abstract

A method includes: forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively; forming a first work function layer, the first work function layer including a first portion and a second portion over the first gate dielectric and the second gate dielectric, respectively; patterning the first work function layer to remove the second portion of the first work function layer; and forming a second work function layer, the second work function layer including the first portion and the second portion over the first gate dielectric and the second gate dielectric, respectively. The method further includes: performing an etching process to etch the second work function layer and a portion of the first portion of the first work function layer to form an opening; and depositing a conductive layer over the second work function layer. The conductive layer fills the opening.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate; and using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise and need to be addressed. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The present invention is best understood by reading it in conjunction with the accompanying drawings from the following detailed description. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration. Figures 1 to 6, 7A, 7B and 8 to 17 illustrate views of the intermediate stages of forming a transistor that cuts a metal boundary region according to some embodiments. Figure 18 illustrates a top view of some transistors according to some embodiments. Figures 19 and 20 illustrate schematic diagrams of circuit regions including and excluding the cut-metal boundary region according to some embodiments. Figure 21 illustrates a view of a fully encircling gate transistor including a cut-metal boundary region according to some embodiments. Figure 22 illustrates the layout of a Static Random-Access Memory (SRAM) cell including a cut-metal boundary region according to some embodiments. Figure 23 illustrates a process flow for forming a transistor including a cut metal boundary region according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, spatial relative terms such as “under,” “below,” “lower,” “overlapping,” “upper,” and similar terms may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element or feature(s). Spatial relative terms are intended to encompass different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0008] Transistors comprising cut-metal-boundary (CMB) regions and methods for forming such transistors are provided. According to some embodiments, p-type and n-type transistors are formed as a stack of gates joined together. A high-k dielectric layer comprising a first portion of the p-type transistor and a second portion of the n-type transistor is cut to form recesses separating the first and second portions. The cutting is performed after the formation of an aluminum-containing material, which serves as the work function layer of the n-type transistor. The subsequently formed adhesive layer and metal-filled regions thus include portions filling the respective recesses to form CMB regions. By forming CMB regions, other diffusion of aluminum into the high-k dielectric of the p-type transistor is reduced, and the adverse reduction of the critical voltage of the p-type transistor is reduced. [, , ]

[0009] The embodiments described herein provide examples to enable the manufacture or use of the subject matter of this disclosure, and those skilled in the art will readily understand the modifications that can be made while remaining within the intended scope of the various embodiments. Similar reference numerals are used throughout the various views and illustrative embodiments to designate similar elements. Although method embodiments may be discussed as being performed in a particular order, other methods may be performed in any logical order. [, , ]

[0010] Figures 1 through 17 illustrate views of intermediate stages in the formation of p-type and n-type transistors according to some embodiments of the present disclosure. The corresponding processes are also schematically reflected in the process flow shown in Figure 22.

[0011] Figure 1 illustrates a perspective view of the initial structure. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type dopants.

[0012] Wafer 10 includes device region 100P where p-type transistors are formed, and device region 100N where n-type transistors are formed. Device region 100P may include well region 21N, which is an n-type region (not shown in Figure 1, see Figure 7B). Device region 100N may also include well region 21P, which is a p-type region (not shown in Figure 1, see Figure 7B). Well regions 21N and 21P can be formed via a placement process. The respective process illustrations are process 202 in process flow 200 as shown in Figure 23.

[0013] Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed to extend from the top surface of substrate 20 into substrate 20. Individual process illustrations are shown as process 204 in process flow 200 as illustrated in Figure 23. The portion of substrate 20 between adjacent STI regions 22 is referred to as semiconductor strip 24, wherein well regions extend into semiconductor strip 24. The top surfaces of semiconductor strip 24 and STI regions 22 may be substantially flush with each other according to some embodiments. The portion of semiconductor substrate 20 below the STI regions 22 is referred to as semiconductor substrate 20 or the bulk portion of a bulk semiconductor substrate.

[0014] Throughout the description, the semiconductor strip 24 in device region 100P is referred to as semiconductor strip 24P, and the semiconductor strip 24 in device region 100N is referred to as semiconductor strip 24N. According to some embodiments, the semiconductor strip 24 is a plurality of portions of the initial substrate 20, and therefore the material of the semiconductor strip 24 is the same as the material of the substrate 20.

[0015] According to an alternative embodiment, semiconductor strip 24 is a replacement strip formed by etching portions of substrate 20 between STI regions 22 to form recesses, and performing an epitaxial process in the recesses to regenerate another semiconductor material. Therefore, semiconductor strips 24P and / or 24N can be formed of semiconductor materials different from those of substrate 20. According to some embodiments, semiconductor strip 24 is formed of silicon-germanium, carbon-doped silicon, or III-V compound semiconductor materials. For example, the top portion of semiconductor strip 24P may contain SiGe, and the top portion of semiconductor strip 24N may contain Si.

[0016] STI region 22 may include a lining oxide (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of substrate 20. The lining oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or similar methods. STI region 22 may also include a dielectric layer above the lining oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or similar methods.

[0017] Referring to Figure 2, the STI region 22 is recessed such that the top portion of the semiconductor strip 24 protrudes above the top surface 22T of the remaining portion of the STI region 22, forming a protruding fin 24'. Individual process illustrations are shown as process 206 in process flow 200 as illustrated in Figure 23. The protruding fins 24' include protruding fins 24'P in device region 100P and protruding fins 24'N in device region 100N. Etching can be performed using a dry etching process, wherein HF and NH3 can be used, for example, as etching gases. Plasma can be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 22 is performed using a wet etching process. For example, the etching chemicals may include HF.

[0018] Referring to Figure 3, a dummy gate stack 30 is formed on the top surface and sidewalls of the (protruding) fin 24'. Individual process illustrations are shown as process 208 in process flow 200 as illustrated in Figure 23. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed of or contain silicon oxide. The dummy gate electrode 34 may be formed, for example, using polycrystalline silicon or amorphous silicon, and may also use other materials. Each of the dummy gate stacks 30 may also include one (or more) hard masking layers 36 above the dummy gate electrode 34. The hard masking layers 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 30 can traverse multiple protruding fins 24' and STI region 22. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 24'.

[0019] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride (SiN), silicon carbonitride (SiCN) or the like, and may have a single-layer structure or a multilayer structure including a plurality of dielectric layers.

[0020] The recessed process is then performed to etch the portion of the protruding fin 24' that is not covered by the dummy gate stack 30 and gate spacer 38, resulting in the structure illustrated in Figure 4. Individual process illustrations are shown as process 210 in process flow 200 illustrated in Figure 23. The recess can be anisotropic, and therefore the portion of the fin 24' directly beneath the dummy gate stack 30 and gate spacer 38 is not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 may be lower than the top surface 22T of the STI region 22. The recess 40 is thus formed between the STI regions 22. The recess 40 is located on the opposite side of the dummy gate stack 30.

[0021] Next, the epitaxial region (source / drain region) 42 is formed by selectively growing semiconductor material from the recess 40, thereby producing the structure shown in Figure 5. Individual process illustrations are shown as process 212 in process flow 200 as illustrated in Figure 23. The source / drain region may individually or collectively refer to the source or drain as described above.

[0022] The source / drain region 42 includes a p-type source / drain region 42P and an n-type source / drain region 42N formed separately via a separation epitaxial process. The p-type source / drain region 42P may include SiGeB, SiB, SiGeIn, SiIn, or similar materials. The n-type source / drain region 42N may include SiP, SiCP, SiAs, SiCAs, or similar materials. After the epitaxial region 42 fully fills the recess 40, the epitaxial region 42 begins to expand horizontally and may form facets.

[0023] Following the epitaxial process, the epitaxial region 42 may be further implanted with p-type or n-type impurities (depending on the conductivity type of the epitaxial region 42) to form source and drain regions, which are also designated by reference numeral 42. According to an alternative embodiment of this disclosure, the implantation process is skipped when the epitaxial region 42 is in-situ doped with p-type or n-type impurities during epitaxy to form source / drain regions. The epitaxial source / source region 42 includes a lower portion formed in the STI region 22 and an upper portion formed above the top surface of the STI region 22.

[0024] Figure 6 illustrates a perspective view of the structure after the formation of the Contact Etch Stop Layer (CESL) 46 and the Inter-Layer Dielectric (ILD) 48. Individual process illustrations are shown as process 214 in process flow 200 as illustrated in Figure 23. According to some embodiments of this disclosure, the CESL 46 may be formed from or comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or similar materials, or combinations thereof. For example, the CESL 46 may be formed using conformal deposition methods such as ALD or CVD. The ILD 48 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 48 can also be formed from oxygen-containing dielectric materials, which can be silicon oxide dielectric materials, such as silicon oxide, phospho-sillicate glass (PSG), boro-sillicate glass (BSG), boron-doped phospho-sillicate glass (BPSG), or similar materials.

[0025] A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, can then be performed to make the top surfaces of the ILD 48, the dummy gate stack 30, and the gate spacer 38 flush.

[0026] Referring to Figure 7A, the dummy gate stack 30 is removed, an operation that can be achieved through multiple etching processes. The individual process diagrams are illustrated as process 216 in process flow 200 as shown in Figure 23. The space left by the removed dummy gate stack 30 is referred to as an opening (or trench) 50. Etching is performed until the protruding fins 24'P and 24'N (see Figure 2) are exposed to the opening 50.

[0027] Figure 7B illustrates a cross-sectional view of the structure in Figure 7A, where the cross-section may be cross-section 7B-7B of Figure 7A. Figure 7A depicts device regions 100P and 100N on the left side of Figure 7B. Transistors to be formed in these device regions can electrically interconnect their gate electrodes. Figure 7B further includes device regions 100P and 100N on the right side of the figure. Transistors to be formed in these device regions can also electrically interconnect their gate electrodes. The interconnect (combined) gate stack to be formed on the left side of Figure 7B will be electrically insulated from the interconnect (combined) gate stack to be formed on the right side of Figure 7B.

[0028] Referring to Figure 8, a gate dielectric 52 is formed. Various process illustrations are shown as process 218 in process flow 200 as illustrated in Figure 23. The gate dielectric 52 includes an interface layer 52A and a high-k dielectric layer 52B. The interface layer 52A may include silicon oxide. According to some embodiments, the interface layer 52A is formed via a deposition process, a thermal oxidation process, a chemical oxidation process, or the like. The high-k dielectric layer 52B may include a high-k dielectric material, such as hafnium oxide, zirconium oxide, lanthanum oxide, and / or the like. The formation process may include conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.

[0029] Referring to Figure 9, a p-type work-function (PWF) layer 54P is formed. The specific process illustration is process 220 in process flow 200 as shown in Figure 23. The P-type work-function layer 54P may have a high work function suitable for forming a PMOS device, which may be between approximately 4.9 eV and approximately 5.2 eV, and may be close to or equal to a band-edge work function of approximately 5.2 eV. For example, the p-type work-function layer 54P may contain TiN, TaN, WCN, MOCN, Pt, Pd, Ni, Au, or similar materials, or combinations thereof. The P-type work-function layer 54P is deposited as a blanket layer and includes portions of device region 100P and device region 100N. The formation process may include conformal deposition processes such as ALD, CVD, or similar methods.

[0030] Referring to Figure 10, an etch mask 56 is formed and patterned. The etch mask 56 may include a photoresist and may have a single-layer, three-layer, or similar structure. The etch mask 56 is alternatively referred to as photoresist 56. A rigid metal mask (not shown) may be present (or absent) beneath the etch mask 56 and above the p-type work function layer 54P. The etch mask 56 may be a conformal layer that covers multiple portions of the p-type work function layer 54P in the p-type device region 100P and exposes multiple portions of the p-type work function layer 54P in the n-type device region 100N.

[0031] Etching process 55 is then performed to etch a metal hard mask (if formed) and a p-type work function layer 54P. The respective process illustration is process 222 in process flow 200 as shown in Figure 23. Therefore, the p-type work function layer 54P is removed from the n-type device region 100N and remains in the p-type device region 100P.

[0032] Referring to Figure 11, the n-type work-function (NWF) layer 54N is deposited via a conformal deposition process such as ALD, CMD, or similar. Individual process illustrations are shown as process 224 in process flow 200 as illustrated in Figure 23. The N-type work-function layer 54N may have a low work function suitable for forming an NMOS device, operating between approximately 4.0 eV and approximately 4.4 eV, and may be a band-edge work function of approximately 4.1 eV. For example, the n-type work-function layer 54N may comprise an aluminum-containing conductive material, such as TiAlC, TiAlN, TaAlC, TaAlN, or similar materials, or combinations thereof.

[0033] The N-type work function layer 54N is deposited as a blanket layer and includes portions of device region 100P and device region 100N. The portion of the n-type work function layer 54N in device region 100P is formed above the p-type work function layer 54P.

[0034] According to these embodiments, the thickness of the p-type work function layer 54P is sufficiently large, for example, greater than about 2 nm or about 3 nm, such that the n-type work function layer 54N is sufficiently far from the channel region of the p-type transistor and has little or no effect on the threshold voltage of the individual p-type transistor. The p-type work function layer 54P thus controls the work function of the individual p-type transistor. Therefore, the portion of the n-type work function layer 54N in the device region 100P is alternatively referred to as an extension of the n-type work function layer 54N. Throughout the description, the p-type work function layer 54P and the n-type work function layer 54N are individually and interconnectedly referred to as work function layer 54.

[0035] Referring to Figure 12, an etch mask 60 is formed and patterned. The etch mask 60 may include a photoresist and may have a single-layer structure, a three-layer structure, or the like. The etch mask 60 is alternatively referred to as photoresist 60. The etch mask 60 covers a portion of the n-type work function layer 54N of both the p-type device region 100P and the n-type device region 100N. The openings 62 in the etch mask 60 are aligned to the boundary region of the p-type device region 100P and its respective adjacent n-type device region 100N.

[0036] Etching process 64 is then performed to etch portions of the n-type work function layer 54N exposed through opening 62. The process is illustrated as process 226 in process flow 200 shown in Figure 23. The etched portion may be located in the boundary region where the n-type device region 100N joins adjacent p-type device regions 100P. Therefore, etching process 64 is referred to as a Cut-Metal-Boundary (CMB) process. The edges of the p-type work function layer 54P may lie directly under and be aligned with opening 62. Thus, after the n-type work function layer 54N is etched, some edges of the p-type work function layer 54P are exposed to opening 62 and are also etched.

[0037] Next, the high-k dielectric layer 52B is etched to expose the interface layer 52A, such that the opening 62 extends into the high-k dielectric layer 52B. According to some embodiments, the etching process can be performed using a chlorine-containing etching gas such as Cl2 or other suitable gases as the etching gas. According to some embodiments, the etching process 64 can be terminated on the interface layer 52A by controlling the ventilation time and / or the etching / ventilation cycle, wherein the interface layer 52A serves as an etching termination layer.

[0038] In the embodiments described above, the p-type work function layer 54P is first deposited, patterned, and removed from the n-type device region 100N, and the n-type work function layer 54N is deposited over the remaining portion of the n-type work function layer 54P. According to alternative embodiments, the deposition order of the p-type work function layer 54P and the n-type work function layer 54N can be reversed. For example, the n-type work function layer 54N can be first deposited, patterned, and removed from the p-type device region 100P, and the p-type work function layer 54P can be deposited over the remaining portion of the n-type work function layer 54N.

[0039] According to some embodiments, a cleaning process may be performed after the etching process to remove the etch mask 60. The resulting structure is illustrated in Figure 13. According to some embodiments, oxygen (O2) and deionized (DI) water may be used to remove polymers generated during the etching process 64.

[0040] According to some embodiments, the width W1 of the opening 62 in the high-k dielectric layer 52 is less than about 200 nm, and can be in the range of about 50 nm to about 200 nm. The width W1 can be in the range of about 20% to about 80% of the fin spacing S1 between the protruding fins on opposite sides of the opening 62.

[0041] According to an alternative embodiment, when the portion of the STI region 22 directly beneath the opening 62 is formed of a material different from that of the interface layer 52A, the etching process 64 may terminate at the STI region 22 instead of at the interface layer 52A. The opening 62 will therefore penetrate the interface layer 52A. According to yet another alternative embodiment, the opening 62 may extend into the STI region 22. According to yet another alternative embodiment, the etching process results in the etching of the n-type work function layer 54N and the p-type work function layer 54P, and terminates on the top surface of the high-k dielectric layer 52B.

[0042] Figures 14 and 15 illustrate the filling of the remaining portion of opening 50 according to some embodiments. Referring to Figure 14, an adhesive layer 68 (also referred to as a barrier layer, as the barrier layer also helps to block interlayer diffusion) is deposited. Individual process illustrations are shown as process 228 in process flow 200 as illustrated in Figure 23. According to some embodiments, the adhesive layer 68 comprises TiN, TaN, or the like. According to some embodiments, the formation process may include conformal deposition processes such as ALD, CVD, or the like.

[0043] Next, as illustrated in Figure 15, a filler metal layer 70 is deposited. Individual process illustrations are shown as process 230 in process flow 200 illustrated in Figure 23. Forming processes may include physical vapor deposition, ALD, CVD, or similar methods, or combinations thereof. The filler metal layer 70 may comprise tungsten, cobalt, aluminum, nickel, or similar materials, or alloys thereof. The filler metal layer 70 is deposited until the entire opening 50 (Figure 7A) is filled.

[0044] A planarization process is then performed, removing the portions of the filler metal layer 70 and adhesive layer 68 above ILD 48 and CESL 46 (Figure 7A). The remaining portion of the work function layer 54 (including the p-type work function layer 54P and the N-type work function layer 54N), along with the overlying adhesive layer 68 and filler metal layer 70, are collectively referred to as gate electrodes 72. Gate electrodes 72 include the gate electrode 72P of the resulting p-type transistor 76P and the gate electrode 72N of the resulting N-type transistor 76N. Gate dielectric 52 and gate electrodes 72 are collectively referred to as gate stack 74. Gate electrode stack 74 includes the gate stack 74P of the p-type transistor 76P and the stack 74N of the N-type transistor 76N.

[0045] According to an alternative embodiment, instead of forming the opening 62 before forming the adhesive layer 68, the opening 62 is formed after forming the adhesive layer 68. Therefore, the adhesive layer 68 is also etched through in the corresponding etching process (except for etching the p-type work function layer 54P and the N-type work function layer 54N). The conductive layer (such as the filler metal layer 70) formed after forming the opening 62 will therefore also penetrate the adhesive layer 68.

[0046] As illustrated in Figure 15, the adhesive layer 68 and the filler metal layer 70 include portions penetrating the p-type work function layer 54P, the n-type work function layer 54N, and the high-k dielectric layer 52B (and within the p-type work function layer 54P, the n-type work function layer 54N, and the high-k dielectric layer 52B) to form a CMB region 78. The CMB region 78 includes sidewalls that contact the sidewalls of the p-type work function layer 54P and the n-type work function layer 54N. The bottom surface of the CMB region 78 may contact the top surface of the interface layer 52A to form a horizontal interface.

[0047] According to an alternative embodiment, the CMB region 78 may penetrate the interface layer 52A to contact the top surface of the STI region 22. According to yet another alternative embodiment, the CMB region 78 may extend into the STI region 22 and include a bottom portion inside the STI region 22.

[0048] Figure 16 illustrates the formation of a cut-metal-gate (CMG) region, a process also known as the CMG process. A separate process illustration is process 232 in process flow 200 as shown in Figure 23. According to some embodiments, the gate stack 74 may be etched to form trenches (occupied by CMG regions 83). The etching process may include one or more anisotropic etching processes.

[0049] According to some embodiments, the STI region 22 may be etched through, exposing the underlying semiconductor substrate 20. According to alternative embodiments, the etching may terminate at any level below the bottom surface of the gate electrode 72, and may terminate at the top surface of the high-k dielectric layer 52B, the top surface of the STI region 22, or any intermediate level between the top and bottom surfaces of the STI region 22.

[0050] The trench is then filled with a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or similar materials, or combinations thereof. This forms the CMB region 82. The CMB region 82 separates the work function layers 54 on opposite sides of the CMB region 82 from each other.

[0051] Figure 17 illustrates a perspective view of the structure shown in Figure 16. It shows a transistor on the left (or right) side of CMB region 82 (Figure 16). Further processes may be performed in subsequent processes, including the formation of a self-aligned gate hard mask to overlap with the gate stack 74. Forming the self-aligned gate hard mask may include an etching process to recess the gate stack 74, filling the recess with a dielectric material, and performing a planarization process to remove the portion of the dielectric material above the top surface of ILD 48. Source / drain silicon layers, source / drain contact plugs, gate contact plugs, and / or similar elements may then be formed to electrically connect to the source / drain region 42 and the gate electrode 72.

[0052] Forming the CMB region 78 has some advantages. As shown in Figure 15, if the CMB region 78 is not formed, the structure at the boundary region of the work function layer 54 can be the same as shown in Figure 11, wherein the n-type work function layer 54N in the device region 100N is laterally close to the p-type work function layer 54P and the high-k dielectric layer 52B in the device region 100P.

[0053] In some embodiments where the n-type work function layer 54N contains aluminum, the aluminum tends to diffuse into the p-type work function layer 54P and the high-k dielectric layer 52B in device region 100P. The diffusion path is marked by arrow 81, as illustrated by example in Figure 11. The diffusion of aluminum from the n-type work function layer 54N into portions of the p-type work function layer 54P and the high-k dielectric layer 52B in device region 100P reduces the threshold voltage tuning capability. For example, the threshold voltage of the p-type transistor may disadvantageously increase by approximately 15 mV to approximately 20 mV. The speed of the p-type transistor may disadvantageously decrease by approximately 1.35% and approximately 1.75%.

[0054] According to some embodiments, by forming the CMB region 78, the lateral diffusion path 81 becomes longer and the diffusion rate is lower. Furthermore, the CMB region 78, including portions of the adhesive layer 68 and the filler metal layer 80, can be dense, thus making it difficult for aluminum to diffuse through the adhesive layer 68 and the filler metal layer 80. This also reduces the diffusion rate. The undesirable increase in the threshold voltage of the p-type transistor is therefore at least reduced or eliminated.

[0055] Figure 18 illustrates a top view of some transistors according to some embodiments. The cross-sectional view shown in Figure 16 is obtained from cross-section 16-16 as shown in Figure 18. Figure 18 illustrates three gate strips parallel to each other and cut by the same CMG region 82. According to alternative embodiments, more or fewer gate strips parallel to each other and cut by the same CMG region 82 may exist.

[0056] As illustrated in Figure 18, the gate stack 74 has an elongated strip shape, which has a longitudinal orientation in the Y direction as illustrated. The gate spacers 38 may form loops, which may or may not be interrupted by the CMG region 83. Each of the high-k dielectric layer 52B, the work function layer 54 (including 54P and 54N), and the adhesive layer 68 includes vertical portions that form interrupted loops interrupted by the CMB region 78.

[0057] CMB region 78 is formed between protruding fins 24'P and 24'N, and extends laterally (in the X direction) beyond the edge of the corresponding edge of the vertical portion of the corresponding work function layer 54, extending into the high-k dielectric layer 52B and the vertical portion of the work function layer 54. In a top view, CMB region 78 may be constrained by individual rings formed by gate spacers 38. On the other hand, CMG region 83 may be cut open and may extend into a plurality of gate stacks.

[0058] According to some embodiments, the CMB region 78 is formed to block the diffusion of aluminum from the n-type transistor to the adjacent p-type transistor. The CMB region 78 works efficiently in embodiments where the n-type transistor is close to its adjacent p-type transistor, wherein the closest fins of the adjacent transistors have a spacing of less than about 100 nm. For embodiments where the spacing between the n-type transistors is larger and diffusion is a less significant concern, the CMB region 78 may not be formed.

[0059] For example, Figure 19 illustrates two groups of transistors. As an example, each group of transistors comprises two p-type transistors and two n-type transistors. In the group on the upper left of the figure (located in device area 86A), the spacing S1 between the fins of the n-type transistors and the fins of their adjacent p-type transistors can be less than about 200 nm or less than about 100 nm. In the group on the upper right of the figure (located in device area 86B), the spacing S2 between the fins of the n-type transistors and the fins of their adjacent p-type transistors is greater than the spacing S1. For example, the spacing S2 can be greater than about 200 nm. The ratio S2 / S1 is greater than 1.0, and can be greater than about 1.5, greater than about 2.0, 5.0, or higher.

[0060] According to some embodiments, the CMB region 78 is formed in the left group and not in the right group. Because the spacing S2 has a high value, aluminum diffusion in the high-k dielectric layer and the p-type work function layer of the p-type transistor is low, and the adverse effect on the critical voltage of the p-type transistor is low. Therefore, the CMB region is not formed.

[0061] Figure 20 illustrates a device die 84 according to some embodiments. Device region 86 includes device regions 86A and 86B. In device region 86A, transistors may be formed smaller and have a smaller pitch S1 (Figure 19). A CMB region 78 is therefore formed in device region 86A to separate adjacent p-type transistors and n-type transistors. Device region 86A may be a logic region having logic circuitry, static random-access memory (SRAM) circuitry, or the like. However, in device region 86B, transistors may be formed larger and have a larger pitch S2 (Figure 19). The CMB region 78 is therefore not formed between adjacent p-type transistors and n-type transistors. According to some embodiments, device region 86A may be an I / O region.

[0062] In the embodiments discussed above, FinFET is illustrated as an example. The concepts of this application can also be applied to any other type of transistor, including but not limited to planar transistors, GAA transistors, complementary field-effect transistors (CFETs), and the like. For example, Figure 21 illustrates the structure forming a p-type transistor and an n-type transistor, wherein their gate electrodes are physically and electrically connected. The CMG region 78 is therefore formed to separate the n-type work function layer 54N from the p-type work function layer 54p of the p-type transistor and a high-k dielectric layer 52B.

[0063] Figure 22 illustrates an example SRAM layout, which includes PMOS and NMOS transistors formed as pull-up (PU) and pull-down (PD) transistors, respectively. The pull-up and pull-down transistors interconnect their gates to form an inverter. Therefore, the CMB region 78 is formed in the gate strip and between the gate electrodes of the pull-up transistor and the gate electrodes of the pull-down transistor.

[0064] The embodiments disclosed herein have several advantageous features. By forming a CMB region in the boundary region of the gate stack of closely positioned transistors, the adverse effects caused by diffusion are reduced. For example, by forming a CMB region to separate the n-type work function layer of an n-type transistor from the p-type work function layer and the high-k dielectric layer of a p-type transistor, the diffusion from aluminum to the p-type work function layer and the high-k dielectric layer of the p-type transistor is reduced. The adverse increase in the threshold voltage of the p-type transistor is reduced. [, , ]

[0065] According to some embodiments of this disclosure, a method includes: forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively; forming a first work function layer, the first work function layer including a first portion and a second portion over the first gate dielectric and the second gate dielectric, respectively; patterning the first work function layer to remove the second portion of the first work function layer; forming a second work function layer, the second work function layer including a first portion and a second portion over the first gate dielectric and the second gate dielectric, wherein the first portion of the second work function layer is further over the first portion of the first work function layer; performing an etching process to etch the second work function layer and a portion of the first portion of the first work function layer to form an opening; and depositing a conductive layer over the second work function layer, wherein the conductive layer fills the opening.

[0066] In one embodiment, forming the first work function layer includes depositing a p-type work function layer, and forming the second work function layer includes depositing an n-type work function layer. In one embodiment, depositing the n-type work function layer includes depositing an aluminum-containing conductive layer. In one embodiment, depositing the conductive layer includes: depositing an adhesive layer; and depositing a filler metal layer over the adhesive layer. In one embodiment, depositing the adhesive layer includes depositing a titanium nitride layer.

[0067] In one embodiment, the adhesive layer partially fills the opening. In another embodiment, the method further includes forming an etch mask including an additional opening, wherein the etch mask is used in the etch process, wherein the additional opening overlaps an edge of the first work function layer, and the second work function layer contacts the edge of the first work function layer, and wherein the opening lies directly beneath the additional opening. In one embodiment, the etch process is performed using an interface layer of the first gate dielectric and the second gate dielectric as an etch stop layer.

[0068] In one embodiment, the first portion of the first work function layer and the first portion of the second work function layer together form multiple portions of a first gate stack of a first transistor, wherein the second portion of the second work function layer forms a portion of a second gate stack of a second transistor. In one embodiment, the method further includes etching the conductive layer and the first work function layer to form a trench; and filling the trench with a dielectric material to form a cut metal gate region.

[0069] According to some embodiments disclosed herein, a structure includes: a first semiconductor region; a first gate dielectric above the first semiconductor region; a first work function layer above the first gate dielectric; a second semiconductor region; a second gate dielectric above the second semiconductor region; a second work function layer above the second gate dielectric; and a conductive layer including: a first portion overlapping the first work function layer; a second portion overlapping the second work function layer; and an intermediate portion joining the first portion to the second portion, wherein the intermediate portion contacts a first edge of the first work function layer and a second edge of the second work function layer, and wherein the intermediate portion substantially contacts the first gate dielectric.

[0070] In one embodiment, the conductive layer comprises a titanium nitride layer. In one embodiment, the first work function layer comprises a p-type work function layer, and the second work function layer comprises an n-type work function layer. In one embodiment, the second work function layer contains aluminum. In one embodiment, the structure further comprises an extension of the second work function layer overlapping the first work function layer, wherein the extension further lies beneath the first portion of the conductive layer.

[0071] In one embodiment, the first work function layer and the second work function layer are respectively contained in a first transistor and a second transistor. In one embodiment, the first semiconductor region is separated from the second semiconductor region by a spacing, and the intermediate portion of the conductive layer has a width in the range of about 20% to about 80% of the spacing. In one embodiment, the conductive layer includes an adhesive layer and a filler metal layer above the adhesive layer.

[0072] According to some embodiments disclosed herein, a structure includes: a p-type transistor comprising a first semiconductor fin, a first gate dielectric above the first semiconductor fin, and a first work function layer above the first gate dielectric; an n-type transistor comprising a second semiconductor fin, a second gate dielectric above the second semiconductor fin, wherein the first gate dielectric and the second gate dielectric comprise an interface layer, a high-k dielectric layer above the interface layer, and a second work function layer above the first gate dielectric; and a combined gate electrode comprising a first gate electrode of the p-type transistor and a second gate electrode of the n-type transistor, wherein the combined gate electrode includes a portion in solid contact with the first work function layer, the second work function layer, and the interface layer.

[0073] In one embodiment, the portion of the combined gate electrode contacts multiple edges of multiple portions of the high-k dielectric layer on the opposite side of that portion of the combined gate electrode.

[0074] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0075] 10: Wafer 20:Substrate 21N: Well area 21P: Well Area 22T: Top surface 22: Quarantine Zone 24'N: Protruding fins 24'P: Prominent fins 24': Protruding fins 24N: Semiconductor strip 24P: Semiconductor strip 24: Semiconductor strips 30: Dummy gate stack 32: Dummy gate dielectric 34: Dummy gate electrode 36: Rigid masking layer 38: Gate spacer 40: concave part 42: Epitaxial Region (Source / Drain Region) 42N: n-type source / drain region 42P: p-type source / drain region 46: Contact Etching Termination Layer (CESL) 48: Interlayer Dielectric (ILD) 50: Opening / Groove 52A: Interface Layer 52B: High-k dielectric layer 52: Gate Dielectric 54N: N-type work function layer 54P: p-type work function (PWF) layer 54: Work Function Layer 55: Etching Process 56: Etching Mask / Photoresist 60: Etching mask / photoresist 62: Opening 64: Etching Process 68: Adhesive layer 70: Filler metal layer 72N: Gate electrode 72P: Gate electrode 72: Gate electrode 74N: Stacked 74P: Gate Stack 74: Gate electrode stacking 76N: N-type transistor 76P:p type transistor 78: Cut Metal Boundary (CMB) Zone 80: Filler metal layer 81: Arrow / Lateral diffusion path 82: Cut Metal Boundary (CMB) Zone 83: Cut Metal Gate (CMG) Region 84: Device Grain 86A: Unit Area 86B: Device Area 100N: Equipment Area 100P: Device Area 200: Manufacturing Process 202: Process 204: Process 206: Manufacturing Process 208: Process 210: Manufacturing Process 212: Manufacturing Process 214: Manufacturing Process 216: Manufacturing Process 218: Manufacturing Process 220: Process 222: Manufacturing Process 224: Manufacturing Process 226: Manufacturing Process 228: Manufacturing Process 230: Process 232: Manufacturing Process S1: Fin spacing S2: Spacing W1: Width

Claims

1. A method of forming a semiconductor structure, comprising: forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively; forming a first work function layer, the first work function layer including a first portion and a second portion over the first gate dielectric and the second gate dielectric, respectively; patterning the first work function layer to remove the second portion of the first work function layer; forming a second work function layer, the second work function layer including a first portion and a second portion over the first gate dielectric and the second gate dielectric, wherein the first portion of the second work function layer is further over the first portion of the first work function layer; performing an etching process to etch the second work function layer and a portion of the first portion of the first work function layer to form an opening; and depositing a conductive layer over the second work function layer, wherein the conductive layer fills the opening; etching the conductive layer and the first work function layer to form a trench; and filling the trench with a dielectric material to form a cleaved metal gate region.

2. The method as described in claim 1, wherein forming the first work function layer comprises depositing a p-type work function layer, and forming the second work function layer comprises depositing an n-type work function layer.

3. The method as described in claim 1, wherein depositing the conductive layer comprises: depositing an adhesive layer; and depositing a filler metal layer over the adhesive layer.

4. The method as described in claim 1, wherein the first portion of the first power function layer and the first portion of the second power function layer together form a plurality of portions of a first gate stack of a first transistor, and wherein the second portion of the second power function layer forms a portion of a second gate stack of a second transistor.

5. The method as described in claim 1, further comprising the steps of: forming an etch mask including an additional opening, wherein the etch mask is used for the etch process, wherein the additional opening overlaps with an edge of the first work function layer, and the second work function layer contacts the edge of the first work function layer, and wherein the opening lies directly beneath the additional opening.

6. A semiconductor structure comprising: a first semiconductor region; a first gate dielectric over the first semiconductor region; a first work function layer over the first gate dielectric; a second semiconductor region; a second gate dielectric over the second semiconductor region; a second work function layer over the second gate dielectric; and a conductive layer comprising: a first portion overlapping the first work function layer; a second portion overlapping the second work function layer; and an intermediate portion joining the first portion to the second portion, wherein the intermediate portion contacts a first edge of the first work function layer and a second edge of the second work function layer, and wherein the intermediate portion substantially contacts the first gate dielectric.

7. The semiconductor structure as claimed in claim 6, further comprising an extension of the second work function layer overlapping the first work function layer, wherein the extension further lies beneath the first portion of the conductive layer.

8. The semiconductor structure as claimed in claim 6, wherein the first work function layer and the second work function layer are respectively contained in a first transistor and a second transistor.

9. A semiconductor structure comprising: a p-type transistor, including: a first semiconductor fin; a first gate dielectric above the first semiconductor fin; and a first work function layer above the first gate dielectric; an n-type transistor, including: a second semiconductor fin; a second gate dielectric above the second semiconductor fin, wherein the first gate dielectric and the second gate dielectric include an interface layer and a high-k dielectric layer above the interface layer; and a second work function layer above the first gate dielectric; and a combined gate electrode including a first gate electrode of the p-type transistor and a second gate electrode of the n-type transistor, wherein the combined gate electrode includes a portion in solid contact with the first work function layer, the second work function layer, and the interface layer.

10. The semiconductor structure as claimed in claim 9, wherein the portion of the combined gate electrode substantially contacts multiple edges of multiple portions of the high-k dielectric layer on multiple opposite sides of the portion of the combined gate electrode.

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