Pixel circuit and display device including the same

Abstract

This disclosure relates to a pixel circuit and a display device including the pixel circuit. The pixel circuit may include a driving transistor for generating current, and a first light-emitting element and a second light-emitting element electrically connected in parallel or series with the driving transistor. The first light-emitting element and the second light-emitting element may be alternately driven by the current generated by the driving transistor.

Description

[Technical Field]

[0001] This disclosure relates to a pixel circuit and a display device including the pixel circuit. [Previous Technology]

[0002] Various flat panel display devices, such as liquid crystal display devices and electroluminescent display devices, are well known. Electroluminescent display devices can use light-emitting elements arranged in each pixel to emit light on their own without backlighting, thereby displaying input images. The light-emitting elements of electroluminescent display devices can be classified into organic light-emitting elements and inorganic light-emitting elements according to the material of the light-emitting layer.

[0003] Recently, display devices using inorganic light-emitting diodes (LEDs) as pixel-level light-emitting elements have attracted much attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect organic materials from moisture, and compared to organic light-emitting diodes (OLEDs), they offer higher reliability and a longer lifespan. Furthermore, LEDs have a fast start-up speed, excellent luminous efficiency, and are impact-resistant.

[0004] In the case of micro-LEDs, defective sub-pixels may appear due to poor transmission of the micro-LEDs. Without an LED binning process, micro-LED chips on the wafer can be transferred onto a substrate using a donor substrate, forming pixel circuits on the substrate. Contact failures may occur between the micro-LEDs transferred onto the substrate, or the brightness characteristics of the micro-LEDs may become uneven. Defective sub-pixels identified during the electrical and optical inspection of the pixels before product shipment may become black spots. To eliminate dark spot defects, two sub-pixels can be set for each color within a pixel. For example, each pixel can contain two red sub-pixels, two green sub-pixels, and two blue sub-pixels. If a pixel consists of six sub-pixels in this way, it is difficult to increase the resolution of the display panel, and transparency cannot be increased due to low light transmittance. [Summary of the Invention]

[0005] This disclosure aims to address the aforementioned needs and / or problems.

[0006] This disclosure provides a pixel circuit that can reduce dark spot defects and facilitate the realization of high-resolution display devices and transparent display devices, as well as a display device including the pixel circuit.

[0007] The purpose of this disclosure is not limited to those mentioned above, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] The pixel circuit according to an embodiment of this disclosure may include a driving transistor to generate current; and first and second light-emitting elements electrically connected to the driving transistor in parallel or series. The first and second light-emitting elements may be alternately driven by current from the driving transistor.

[0009] A display device according to an embodiment of the present disclosure may include: a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits arranged on a display panel; a data driving circuit connected to the data lines; and a gate driving circuit connected to the gate lines. Each pixel circuit may include: a driving transistor configured to generate current; and first and second light-emitting elements electrically connected in parallel or series with the driving transistor. The first and second light-emitting elements may be alternately driven by current from the driving transistor.

[0010] According to the embodiments disclosed herein, a pixel circuit capable of driving light-emitting elements with high efficiency and high brightness to improve their lifespan and achieve low-power operation can be realized, as well as a display device including the pixel circuit.

[0011] According to one embodiment of this specification, by connecting two light-emitting elements in series and / or in parallel to a sub-pixel and driving the light-emitting elements alternately, the number of sub-pixels disposed in a pixel can be reduced, and pixels that become dark spots can be minimized, thereby improving the process optimization and yield of the display panel.

[0012] This disclosure provides a pixel structure suitable for realizing high-resolution display devices and transparent display devices, which is achieved by minimizing dark spot defects and increasing pixel density.

[0013] The effects of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand from the description of the claims that other effects are not mentioned.

Implementation Method

[0015] The advantages and features of this disclosure, as well as the methods for implementing these advantages and features, will become apparent with reference to the exemplary examples set forth in detail herein together with the drawings. This disclosure should not be construed as being limited to the exemplary examples disclosed below, and may be implemented in various different forms. Therefore, these exemplary examples are presented to make this disclosure sufficiently complete and to assist those skilled in the art in fully understanding the scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims and their equivalents.

[0016] The shapes, sizes, proportions, angles, and numbers disclosed in the drawings to illustrate the embodiments of this disclosure are merely examples, and therefore, the details shown in the drawings do not constitute a limitation on this disclosure. Throughout the specification, similar reference numerals refer to similar elements. Furthermore, in the description of this disclosure, unnecessary details of related prior art that would obscure the essential points of this disclosure are omitted.

[0017] Here, unless the word "only" is used, when "including," "having," or "contains" is used in the text, another part may be added. Unless otherwise stated, terms in the singular form may include plural cases.

[0018] Although not explicitly stated, the components are interpreted as including the usual error range.

[0019] When using terms such as “above,” “over,” “below,” “connected or coupled,” “cross,” “intersecting,” etc. to describe the positional relationship or interconnection between two components, one or more other components may be inserted between them unless “immediately” or “directly” is used.

[0020] When using terms such as “after,” “following,” “next,” “before,” “previously,” “before this,” etc. to describe a temporal sequence, the temporal relationship may not be continuous on a time basis unless “immediately” or “directly” is used.

[0021] The terms “first”, “second”, etc. can be used to distinguish the components, but the function or structure of the components is not limited by the ordinal number or name of the components.

[0022] The following embodiments can be combined or integrated with each other in part or in whole, and can be linked and operated in a variety of technical ways. These embodiments can be performed independently or in conjunction with each other.

[0023] The pixel circuit of a display device may include multiple transistors. A transistor is a three-electrode element comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow out from the source. The drain is the electrode from which charge carriers flow out of the transistor. In a transistor, charge carriers flow from the source to the drain. In an N-type channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, so electrons can flow from the source to the drain. N-type channel transistors have a current direction from the drain to the source. In the case of a P-type channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, so holes can flow from the source to the drain. In a P-type channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the present invention is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0024] The gate signal oscillates between the gate turn-on voltage and the gate turn-off voltage. The transistor turns on in response to the gate turn-on voltage and turns off in response to the gate turn-off voltage. In the case of an N-channel transistor, the gate turn-on voltage can be the gate high voltage VGH, and the gate turn-off voltage can be the gate low voltage VGL. In the case of a P-channel transistor, the gate turn-on voltage can be the gate low voltage VGL, and the gate turn-off voltage can be the gate high voltage VGH.

[0025] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0026] Referring to Figures 1 and 2, the display device according to the present disclosure embodiment may include a display panel 100 and a display panel driving circuit for writing pixel data into the pixels of the display panel 100.

[0027] The substrate of the display panel 100 may be a plastic substrate, a thin glass substrate, or a metal substrate, but this disclosure is not limited thereto. The display panel 100 may be a rectangular panel having a length in the X-axis direction (or a first direction), a width in the Y-axis direction (or a second direction), and a thickness in the Z-axis direction (or a third direction), but this disclosure is not limited thereto. For example, at least a portion of the display panel 100 may have curved edges.

[0028] The display panel 100 can be a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in transparent display devices that display images on a screen and make real objects visible outside the display panel. The display panel 100 can be manufactured as a flexible display panel. Furthermore, the display panel 100 can be manufactured as an extendable, stretchable panel.

[0029] The display area AA of the display panel 100 includes a pixel array for displaying input images. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and multiple pixels 101 arranged in a matrix. The display panel 100 may further include multiple power lines that are commonly connected to the pixels 101. These power lines are commonly connected to the pixels 101 to provide a constant voltage required to drive the pixels 101. These power lines may be implemented as long strip conductors extending along a first direction or a second direction, or as a mesh conductor formed by electrically connecting conductors in the first direction and conductors in the second direction.

[0030] Each of the pixels 101 may contain a red subpixel, a green subpixel, and a blue subpixel for color implementation. In the following description, "pixel" may be interpreted as "subpixel". One subpixel may be arranged within a pixel 101 for each color.

[0031] Each sub-pixel may include a pixel circuit and two light-emitting elements (e.g., micro LEDs) electrically connected to this pixel circuit. The pixel circuit may include an internal compensation circuit or be connected to an external compensation circuit. When the sub-pixel is connected to an external compensation circuit, the display panel 100 may further include multiple sensing lines connected to the sub-pixel. The internal compensation circuit may be embedded in the pixel circuit of each sub-pixel to sample the threshold voltage of the driving transistor of each sub-pixel and compensate the gate-source voltage of the driving transistor through the threshold voltage. The external compensation circuit can sense the electrical characteristics of the driving transistor (e.g., threshold voltage and mobility) and modulate the pixel data (digital data) of the input image through the deviation (or change) of the electrical characteristics of the driving transistor, thereby compensating for the deviation (or change) of the electrical characteristics of the driving transistor in each pixel in real time.

[0032] The pixel array comprises multiple pixel lines L(1) to L(N). Here, N is a natural number greater than or equal to 2. Each of the pixel lines L(1) to L(N) comprises a column of pixels arranged along the gate line direction (X-axis direction) in the pixel array of the display panel 100. Multiple pixels arranged in a column of pixel lines may share a gate line 103. Pixels arranged in the row direction (Y-axis direction) along the data line direction may share the same data line 102. A horizontal period is the time obtained by dividing a frame period by the total number of pixel lines L(1) to L(N).

[0033] The display device may include a power supply omitted in Figure 1. This power supply uses a DC-DC converter to generate a constant voltage (or DC) required to drive the pixel array and display panel driving circuitry of the display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power supply can adjust the level of the input voltage from the host system 200 to output a constant voltage, such as a gamma reference voltage, gate low voltage, gate high voltage, pixel drive voltage, pixel ground voltage (hereinafter referred to as "ground voltage"), pixel reference voltage (hereinafter referred to as "reference voltage"), etc. The gamma reference voltage is applied to the data driver 110. The dynamic range of the data voltage output by the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest grayscale voltage and the lowest grayscale voltage.

[0034] Gate high voltage and gate low voltage are applied to a level offset device omitted in FIG1 and to gate driver 120. Constant voltages such as pixel drive voltage, ground voltage, and reference voltage are applied to pixel 101 through a power supply line connected to pixel 101. The reference voltage can be interpreted as the initialization voltage. The pixel drive voltage can be applied to display panel 100 from the main power supply of host system 200. In this case, the power supply does not need to output pixel drive voltage.

[0035] Under the control of the timing controller 130, the display panel driving circuit writes the pixel data of the input image into the pixels of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0036] In at least one embodiment, the display panel driving circuit may further include a selector 140. The display panel 100 may also have multiple selection signal lines that apply the selection signal output from the selector 140 to the sub-pixels. These selection signal lines may be connected together to the sub-pixels.

[0037] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. The touch sensor driver is omitted in Figure 1. The data driver 110 and the touch sensor driver may be embedded in a single integrated circuit (IC). The timing controller 130, power supply, level offset, etc., may be further integrated into the integrated circuit.

[0038] The data driver 110 can receive pixel data of the input image as a digital signal from the timing controller 130 and output a data voltage. The data driver 110 can convert the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (DAC) and output a data voltage. The gamma reference voltage can be divided into gamma compensation voltages applied to a specific gray level of the DAC by the voltage divider circuit of the data driver 110. The DAC can generate a data voltage as a gamma compensation voltage corresponding to the gray level value of the pixel data. The data voltage output from the DAC can be output to the data line 102 through the output buffer of the data output channel of the data driver 110.

[0039] The external compensation circuit may include: multiple sensing channels embedded in the data driver 110 that convert the voltage of the sensing line into digital data and transmit the digital data to the timing controller 130, and compensation logic circuitry embedded in the timing controller 130. Each sensing channel may include an analog-to-digital converter (ADC). The compensation logic circuitry may select a compensation value based on the sensing value received from the sensing channel of the data driver 110, add or multiply the selected compensation value with the pixel data of the input image, and transmit the result to the data driver 110, thereby compensating for the degradation of the driving transistors and / or light-emitting elements of each sub-pixel.

[0040] The gate driver 120 may be formed together with the thin-film transistor array and wires of the pixel array in the display panel 100. The gate driver 120 may be disposed in the non-display area NA outside the display area AA in the display panel 100, or at least a portion of the gate driver 120 may be disposed within the display area AA. For example, as shown in FIG2, the gate driver 120 may be embedded within the display area AA. In this case, the pixel circuit and light-emitting element of the pixel 101 may overlap with the circuit of the gate driver 120 in the Z-axis direction of the display panel 100.

[0041] The gate driver 120 can be disposed in the left non-display area NA or the right non-display area NA outside the display area AA in the display panel 100, and provides a gate signal to the gate line 103 using a single-feed method. In the single-feed method, the gate signal is applied to one end of the gate line. The gate driver 120 can be disposed in the left non-display area NA and the right non-display area NA in the display panel 100, so as to apply the gate signal to the gate line 103 through a single-feed method or a dual-feed method. In the dual-feed method, the gate signal is applied to both ends of the gate line 103 simultaneously. At least some circuitry of the gate driver 120 can be disposed within the display area AA.

[0042] Gate driver 120 may include a shift register and / or edge triggers for outputting pulses of gate signals under the control of timing controller 130 and causing them to shift. Gate driver 120 may output multiple gate signals with different waveforms. In this case, gate driver 120 may include multiple gate drivers that output different gate signals. Gate signals may include scan signals and light-emitting signals (referred to as "light-emitting signals"). In this case, gate driver 120 may include gate drivers that sequentially output multiple scan signals and gate drivers that sequentially output multiple light-emitting signals.

[0043] Among the two light-emitting elements arranged in each sub-pixel, the light-emitting element to be driven or turned on can be selected by the output signal of the gate driver 120 or the selector 140. The gate driver 120 can output a second light-emitting signal and a third light-emitting signal, thereby selecting the light-emitting element to be driven in each sub-pixel of the pixel line unit under the control of the timing controller 130. In this case, the gate driver 120 may further include a gate driver that sequentially outputs a second light-emitting signal and a gate driver that sequentially outputs a third light-emitting signal.

[0044] Under the control of the timing controller 130, the selector 140 can globally select the light-emitting element to be driven or turned on for the entire display area AA between the two light-emitting elements set in each sub-pixel.

[0045] Timing controller 130 receives pixel data of the input image and timing signals synchronized with the pixel data from host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The vertical synchronization signal Vsync indicates a frame period containing one pulse generated per frame period. The pulses of the horizontal synchronization signal Hsync and the data enable signal DE can be a horizontal period (1H). Timing controller 130 can determine a frame period (or a vertical period) and a horizontal period by counting the data enable signal DE. In this case, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. Timing controller 130 can determine the frame period to which the current frame period belongs by counting the rising or falling edges of the pulses in the start pulses of the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE or the gate timing signal.

[0046] The timing controller 130 can control the gate driver 120 or the selector 140 based on subpixel mapping data, wherein the subpixel mapping data is configured with the position information of the first light-emitting element and the second light-emitting element that are determined to be defective during the detection process in each subpixel. This subpixel mapping data is stored in memory accessible through the timing controller 130. A subpixel becomes a dark spot only when both of its configured light-emitting elements are defective, and if either light-emitting element can be driven, the subpixel can be driven normally.

[0047] The timing controller 130 can control the operating timing of the data driver 110, the gate driver 120, and the selector 140 based on the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE received from the host system 200. The timing control signal output from the timing controller 130 can be applied to the gate driver 120 and / or the selector 140 through a level offset.

[0048] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100, and can transmit the image signal and timing control signal together to the timing controller 130.

[0049] As shown in Figure 3, the display device can be implemented as a tiled display (TD), wherein multiple display panels are combined on the same plane to provide a wide screen.

[0050] Referring to Figure 3, the widescreen video wall display TD includes multiple display panels PNL1 to PNL4 disposed on the XY plane. When the non-display area NA of the outer edge of each of the display panels PNL1 to PNL4 is minimized, widescreen images can be reproduced without visible seams between adjacent display panels PNL1 to PNL4. The gate driver 120 can be embedded in the display area AA of the display panels PNL1 to PNL4 to minimize the non-display area NA around the display panels PNL1 to PNL4.

[0051] These display panels 100 can be assembled on a plane such that the distance D1 between the outermost pixels 101 adjacent to each other at the boundary between adjacent display panels PNL1 to PNL4 is substantially the same as the distance D2 between adjacent pixels 101 within the display area AA of each display panel PNL1 to PNL4. Therefore, the distances D1 and D2 between pixels 101 are the same throughout the entire widescreen display area of ​​the splicing display TD, thus making the seam area invisible.

[0052] In the following description, the first selection signal and the second light emission signal can be interpreted as the first control signal. The second selection signal and the third light emission signal can be interpreted as the second control signal.

[0053] Figures 4A and 4B are circuit diagrams illustrating a pixel circuit according to a first embodiment of the present invention.

[0054] Referring to Figures 4A and 4B, the pixel circuit may include a first light-emitting element MLD, a second light-emitting element RLD, a driving transistor DR, multiple switching transistors M1, M2 and M3, and a compensation circuit 300. The driving transistor DR and the switching transistors M1, M2 and M3 can be implemented using P-type channel transistors, but this disclosure is not limited thereto.

[0055] Each of the first light-emitting element MLD and the second light-emitting element RLD may include an anode electrode, a cathode electrode, and a light-emitting layer. The first light-emitting element MLD and the second light-emitting element RLD may be light-emitting elements, such as, but not limited to, OLEDs and micro-LEDs. The micro-LED chip may be implemented in a lateral structure or a flip-chip structure. One of the first light-emitting element MLD and the second light-emitting element RLD may be interpreted as a main light-emitting element, and the other may be interpreted as a backup light-emitting element.

[0056] The first light-emitting element MLD and the second light-emitting element RLD can be connected in parallel to the driving transistor DR via switching transistors M1, M2, and M3. The driving transistor DR generates a current for driving the first light-emitting element MLD and the second light-emitting element RLD in response to the gate-source voltage. The gate-source voltage of the driving transistor DR can change in response to the data voltage Vdata of the pixel data applied to the gate electrode of the driving transistor DR. Therefore, the current flowing through the driving transistor DR can change with the data voltage Vdata. The light-emitting elements MLD and RLD can be driven to emit light by the current provided by the driving transistor DR. The driving transistor DR may include: a gate to which the data voltage Vdata is applied, a first electrode to which the pixel driving voltage EVDD is applied, and a second electrode connected to the first electrode of the third switching transistor M3.

[0057] The first switching transistor M1 can be connected between the third switching transistor M3 and the anode electrode of the first light-emitting element MLD. The first switching transistor M1 can be turned on in response to the gate turn-on voltage (e.g., gate low voltage VGL) of the first selection signal SEM, and can be turned off in response to the gate turn-off voltage (e.g., gate high voltage VGH) of the first selection signal SEM. As shown in FIG4A, when the first switching transistor M1 and the third switching transistor M3 are turned on, the first light-emitting element MLD can be electrically connected to the driving transistor DR, thereby driving the first light-emitting element MLD.

[0058] The second switching transistor M2 can be connected between the third switching transistor M3 and the anode electrode of the second light-emitting element RLD. The second switching transistor M2 can be turned on in response to the gate turn-on voltage of the second selection signal SER, and can be turned off in response to the gate turn-off voltage of the second selection signal SER. As shown in FIG4B, when the second switching transistor M2 and the third switching transistor M3 are turned on, the second light-emitting element RLD can be electrically connected to the driving transistor DR, thereby driving the second light-emitting element RLD.

[0059] The third switching transistor M3 can be connected between the driving transistor DR and the first switching transistor M1 and the second switching transistor M2. The third switching transistor M3 can be turned on in response to the gate conduction voltage of the light emission signal EM, and can be turned off in response to the gate conduction voltage of the light emission signal EM. When the third switching transistor M3 is turned on, the driving transistor DR can be electrically connected to the first switching transistor M1 or the second switching transistor M2.

[0060] The compensation circuit 300 can be connected to the data line to which the data voltage Vdata is applied and the gate line to which gate signals SCAN1, SCAN2 and an EM signal are applied. The compensation circuit 300 may include multiple transistors and one or more capacitors. The compensation circuit 300 can transmit the data voltage Vdata to the gate of the driving transistor DR. The compensation circuit 300 can sample the threshold voltage of the driving transistor DR at the capacitor and compensate the gate voltage of the driving transistor DR by the threshold voltage of the driving transistor DR.

[0061] Figures 5A and 5B are circuit diagrams illustrating a pixel circuit according to a second embodiment of the present invention. In this embodiment, the same content as in the first embodiment described above will not be described again.

[0062] Referring to Figures 5A and 5B, the driving transistor DR, the third switching transistor M3, the first light-emitting element MLD, and the second light-emitting element RLD can be connected in series between the pixel driving voltage EVDD and the ground voltage EVSS.

[0063] The first light-emitting element MLD may include: an anode electrode connected to the second electrode of the third switching transistor M3, and a cathode electrode connected to the anode electrode of the second light-emitting element RLD. The second light-emitting element RLD may include: an anode electrode connected to the cathode electrode of the first light-emitting element MLD, and a cathode electrode to which a ground voltage EVSS is applied.

[0064] The first switching transistor MOSFET MOS can be connected between the two ends of the second light-emitting element RLD. The first switching transistor MOS can be turned on in response to the gate turn-on voltage of the first selection signal SEM, and turned off in response to the gate turn-off voltage of the first selection signal SEM. When the first switching transistor MOS is turned on, the two ends of the second light-emitting element RLD are short-circuited. At this time, as shown in FIG5A, the current from the driving transistor DR flows to the first light-emitting element MLD, thereby driving the first light-emitting element MLD, and simultaneously putting the second light-emitting element RLD in a short-circuited off state.

[0065] The second switching transistor MOS transistor MO2 can be connected between the two ends of the first light-emitting element MLD. The second switching transistor MOS transistor MO2 can be turned on in response to the gate turn-on voltage of the second selection signal SER, and can be turned off in response to the gate turn-off voltage of the second selection signal SER. When the second switching transistor MOS transistor MO2 is turned on, the two ends of the first light-emitting element MLD can be short-circuited. At this time, as shown in FIG5B, the current from the driving transistor DR flows to the second light-emitting element RLD, so that the second light-emitting element RLD can be driven, while the first light-emitting element MLD is in the off state with its two ends short-circuited.

[0066] The third switching transistor M3 can be turned on in response to the gate turn-on voltage of the light-emitting signal EM, or turned off in response to the gate turn-off voltage of the light-emitting signal EM. When the third switching transistor M3 is turned on, the second electrode of the driving transistor DR can be electrically connected to the anode electrode of the first light-emitting element MLD. The third switching transistor M3 may include a gate electrode to which the light-emitting signal EM is applied, a first electrode connected to the second electrode of the driving transistor DR, and a second electrode connected to the anode electrode of the first light-emitting element MLD and the first electrode of the second switching transistor M02.

[0067] Figure 6 is a circuit diagram showing in detail an example of the compensation circuit shown in Figures 4A and 4B.

[0068] Referring to Figure 6, the pixel driving voltage EVDD, the ground voltage EVSS, and the reference voltage Vref can be applied to the pixel circuit. The pixel driving voltage EVDD, the ground voltage EVSS, and the reference voltage Vref can be set to, but are not limited to, 10V, 0V, and 2V, respectively.

[0069] The data voltage Vdata, gate signals SCAN1 and SCAN2, light emission signal EM, and selection signals SEM and SER can be input to the pixel circuit. The data voltage Vdata can be a voltage with a dynamic range between 0V and 10V, but this disclosure is not limited to this. For the gate signals SCAN1 and SCAN2, the light emission signal EM, and the selection signals SEM and SER, the gate high voltage VGH and the gate low voltage VGL can be set to 15V and -8V respectively, but this does not constitute a limitation of this disclosure.

[0070] The driving transistor DR may include a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3. The first node n1 may be connected to a power line to which a pixel driving voltage EVDD is applied.

[0071] The first switching transistor M1 may include: a first electrode connected to the fourth node n4, a gate electrode connected to the first selection signal line S1 to which the first selection signal SEM is applied, and a second electrode connected to the anode electrode of the first light-emitting element MLD. The second switching transistor M2 may include: a first electrode connected to the fourth node n4, a gate electrode connected to the second selection signal line S2 to which the second selection signal SER is applied, and a second electrode connected to the anode electrode of the second light-emitting element RLD.

[0072] The first light-emitting element MLD may include: an anode electrode connected to the second electrode of the first switching transistor M1, and a cathode electrode connected to a power line to which a ground voltage EVSS is applied. The second light-emitting element RLD may include: an anode electrode connected to the second electrode of the second switching transistor M2, and a cathode electrode connected to a power line to which a ground voltage EVSS is applied.

[0073] The third switching transistor M3 may include a first electrode connected to the third node n3, a gate electrode connected to the third gate line GL3 to which the light emission signal EM is applied, and a second electrode connected to the fourth node n4.

[0074] The compensation circuit 300 may include a capacitor Cst and a fourth switching transistor M4 to an eighth switching transistor M8.

[0075] Capacitor Cst can be connected between the second node n2 and the fifth node n5 to suppress changes in the gate-source voltage of the driving transistor DR until the next data voltage is input. For example, the gate-source voltage of the driving transistor DR can be maintained by capacitor Cst for approximately one frame period.

[0076] A fourth switching transistor M4 may be connected between a data line DL to which a data voltage Vdata is applied and a fifth node n5. The data voltage Vdata is output from the data driver 110. The fourth switching transistor M4 may be turned on in response to a gate low voltage VGL of the first scan signal SCAN1 and turned off in response to a gate high voltage VGH of the first scan signal SCAN1. When the fourth switching transistor M4 is turned on, the data line DL may be electrically connected to the fifth node n5. The fourth switching transistor M4 may include a first electrode connected to the data line DL, a gate electrode connected to the first gate line GL1 to which the first scan signal SCAN1 is applied, and a second electrode connected to the fifth node n5.

[0077] The fifth switching transistor M5 can be connected between the second node n2 and the third node n3. The fifth switching transistor M5 can be turned on in response to the gate low voltage VGL of the first scan signal SCAN1, and can be turned off in response to the gate high voltage VGH of the first scan signal SCAN1. When the fifth switching transistor M5 is turned on, the second node n2 can be electrically connected to the third node n3. The fifth switching transistor M5 may include a first electrode connected to the second node n2, a gate electrode connected to the first gate line GL1, and a second electrode connected to the third node n3.

[0078] The sixth switching transistor M6 can be connected between the power supply line to which the reference voltage Vref is applied and the fifth node n5. The sixth switching transistor M6 can be turned on in response to the gate low voltage VGL of the light emission signal EM and turned off in response to the gate high voltage VGH of the light emission signal EM. When the sixth switching transistor M6 is turned on, the reference voltage Vref can be applied to the fifth node n5. The sixth switching transistor M6 may include: a first electrode connected to the fifth node n5, a gate electrode connected to the third gate line GL3 to which the light emission signal EM is applied, and a second electrode to which the reference voltage Vref is applied.

[0079] A seventh switching transistor M7 may be connected between the second node n2 and a power line to which a reference voltage Vref is applied. The seventh switching transistor M7 may be turned on in response to a gate low voltage VGL of the second scan signal SCAN2, and may be turned off in response to a gate high voltage VGH of the second scan signal SCAN2. When the seventh switching transistor M7 is turned on, the reference voltage Vref may be applied to the second node n2. The seventh switching transistor M7 may include: a first electrode connected to the second node n2, a gate electrode connected to the second gate line GL2 to which the second scan signal SCAN2 is applied, and a second electrode to which the reference voltage Vref is applied.

[0080] The eighth switching transistor M8 can be connected between the data line DL, to which the data voltage Vdata is applied, and the fifth node n5. The eighth switching transistor M8 can be turned on in response to the gate low voltage VGL of the second scan signal SCAN2, and can be turned off in response to the gate high voltage VGH of the second scan signal SCAN2. When the eighth switching transistor M8 is turned on, the data line DL can be electrically connected to the fifth node n5. The eighth switching transistor M8 may include: a first electrode connected to the data line DL, a gate electrode connected to the second gate line GL2, and a second electrode connected to the fifth node n5.

[0081] Figure 7 is a circuit diagram showing in detail one example of the compensation circuit shown in Figures 5A and 5B. In this embodiment, descriptions that are substantially the same as or overlap with those shown in Figures 5A and 6 will be omitted.

[0082] Referring to Figure 7, the driving transistor DR may include: a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0083] The first light-emitting element MLD may include: an anode electrode connected to the fourth node n4, and a cathode electrode connected to the fifth node n05. The second light-emitting element RLD may include: an anode electrode connected to the fifth node n05, and a cathode electrode connected to a power line to which a ground voltage EVSS is applied.

[0084] The first switching transistor M01 may include: a first electrode connected to the fifth node n05, a gate electrode connected to the first selection signal line S1 to which the first selection signal SEM is applied, and a second electrode connected to the cathode electrode of the second light-emitting element RLD. The second switching transistor M02 may include: a first electrode connected to the fourth node n4, a gate electrode connected to the second selection signal line S2 to which the second selection signal SER is applied, and a second electrode connected to the fifth node n05.

[0085] The third switching transistor M3 may include: a first electrode connected to the third node n3, a gate electrode connected to the third gate line GL3 to which the light emission signal EM is applied, and a second electrode connected to the fourth node n4.

[0086] Capacitor Cst can be connected between the second node n2 and the sixth node n06. The fourth switching transistor M4 can be connected between the data line DL, to which the data voltage Vdata is applied, and the sixth node n06. When the fourth switching transistor M4 is turned on, the data line DL is electrically connected to the sixth node n06. The fourth switching transistor M4 may include a first electrode connected to the data line DL, a gate electrode connected to the first gate line GL1 to which the first scan signal SCAN1 is applied, and a second electrode connected to the sixth node n06.

[0087] The fifth switching transistor M5 can be connected between the second node n2 and the third node n3. When the fifth switching transistor M5 is turned on, the second node n2 can be electrically connected to the third node n3.

[0088] The sixth switching transistor M6 can be connected between a power supply line to which a reference voltage Vref is applied and the sixth node n06. When the sixth switching transistor M6 is turned on, the reference voltage Vref can be applied to the sixth node n06. The sixth switching transistor M6 may include a first electrode connected to the sixth node n06, a gate electrode connected to the third gate line GL3 to which a light emission signal EM is applied, and a second electrode to which the reference voltage Vref is applied.

[0089] The seventh switching transistor M7 can be connected between the second node n2 and the power line to which the reference voltage Vref is applied. When the seventh switching transistor M7 is turned on, the reference voltage Vref can be applied to the second node n2.

[0090] The eighth switching transistor M8 can be connected between the data line DL and the sixth node n06. When the eighth switching transistor M8 is turned on, the data line DL can be electrically connected to the sixth node n06. The eighth switching transistor M8 may include: a first electrode connected to the data line DL, a gate electrode connected to the second gate line GL2, and a second electrode connected to the sixth node n06.

[0091] The pixel circuits shown in Figures 4A to 7 can be driven during the initialization phase, sampling phase, holding phase and emission phase during a single frame period.

[0092] Figure 8 is a waveform diagram showing the input signal of the pixel circuit shown in Figures 4A to 7.

[0093] Referring to Figures 6 to 8, the initialization phase can be performed during the first period Pi. During the first period Pi, the voltage of the second scan signal SCAN2 is the gate low voltage VGL, and the voltages of the first scan signal SCAN1 and the light emission signal EM are the gate high voltage VGH. Accordingly, during the first period Pi, the seventh transistor M7 and the eighth transistor M8 can be turned on, while the third transistor M3 to the sixth transistor M6 can be turned off. During the first period Pi, the first transistors M1, M01 and the second transistors M2, M02 can be turned on in response to the voltages of the first selection signal SEM and the second selection signal SER, but since the third transistor M3 is in the off state, the light emission elements MLD and RLD will not emit light.

[0094] During the first cycle Pi, the reference voltage Vref can be applied to the second node n2, so that the gate voltage of the driving transistor DR is initialized to the reference voltage Vref.

[0095] During the first cycle Pi, the data voltage Vdata(N-1) of the previous pixel line (e.g., the (N-1)th pixel line) is applied to the data line DL, and then the data voltage Vdata(N) of the current pixel line is applied to the data line DL. The data voltage Vdata(N) can be applied to the fifth node n5 shown in FIG6 and the sixth node n06 shown in FIG7 through the eighth switching transistor M8.

[0096] The sampling phase can be performed during the second cycle Ps. During the second cycle Ps, the voltage of the first scan signal SCAN1 is the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the light emission signal EM are the gate high voltage VGH. Therefore, during the second cycle Ps, the fourth switching transistor M4 and the fifth switching transistor M5 can be turned on, while the third switching transistor M3 and the sixth to eighth switching transistors M6 to M8 can be turned off. During the second cycle Ps, the first switching transistors M1, M01 and the second switching transistors M2, M02 can be turned on in response to the voltages of the first selection signal SEM and the second selection signal SER, but the light emission elements MLD and RLD do not emit light because the third switching transistor M3 is in the off state.

[0097] The driving transistor DR can be in the on state when entering the second cycle Ps and can be turned off when the turn-off condition (Vs-Vg)+Vth<0 is reached. Here, Vs-Vg is the voltage difference between the voltage Vs of the first node n1 and the voltage Vg of the second node n2. At the end of the second cycle Ps, the voltage of the second node n2 can be EVDD + Vth. At the end of the second period Ps, the voltages of the fifth node n5 shown in Figure 6 and the sixth node n06 shown in Figure 7 can be the data voltage Vdata(N). Therefore, in the second cycle Ps, the data voltage Vdata(N) after compensation by the critical voltage Vth of the driving transistor DR can be stored in the capacitor Cst.

[0098] Simultaneously, after the eighth switching transistor M8 is turned on and the data line DL is connected to the fifth node n5 shown in Figure 6 or the sixth node n06 shown in Figure 7, the fourth switching transistor M4 can be turned on and the data line DL can be connected to the fifth node n5 shown in Figure 6 or the sixth node n06 shown in Figure 7. For example, the eighth switching transistor M8 can apply a data voltage Vdata(N) to the fifth node n5 or the sixth node n06 connected to one electrode of the capacitor Cst during the initialization phase, which is the same as the data voltage Vdata(N) applied to one electrode of the capacitor Cst during the sampling phase. This avoids the driving transistor DR from being unable to be driven or generating a critical voltage sampling error during the sampling phase. If the eighth switching transistor M8 is not present, the voltage at node n5 or n06 connected to one electrode of the capacitor Cst will change due to the previous state of the sampling phase, thereby increasing the voltage at the second node n2 through capacitive coupling, which may cause the driving transistor DR to fail to drive properly.

[0099] The holding phase can be performed during the third cycle Ph. During the third cycle Ph, the voltages of the first scan signal SCAN1, the second scan signal SCAN2, and the light emission signal EM can all be the gate high voltage VGH. Accordingly, during the third cycle Ph, the voltage of capacitor Cst will remain in its previous state.

[0100] The light-emitting phase can be performed during the fourth cycle, Pem. During the fourth cycle, Pem, the voltage of the light-emitting signal EM can be the gate low voltage VGL, and the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 can be the gate high voltage VGH. Therefore, during the fourth cycle, Pem, the third and sixth switching transistors M3 are turned on, while the fourth, fifth, seventh, and eighth switching transistors M4, M5, M7, and M8 are turned off. During the fourth cycle, Pem, the driving transistor DR can generate current in response to the gate-source voltage and can alternately drive the selected light-emitting elements MLD and RLD in response to the selection signals SEM and SER.

[0101] During the fourth cycle Pem, the voltages of the fifth node n5 shown in Figure 6 and the sixth node n06 shown in Figure 7 can be changed to the reference voltage Vref, and the voltage of the second node n2, which is in a floating state, can change with this voltage variation. During the fourth cycle Pem, the current (Ids) flowing through the driven light-emitting elements MLD and RLD is as follows:

[0102] Here, Vgs is the gate-source voltage of the driving transistor DR. It is a constant value determined by the mobility (μ), channel capacitance (Cox), channel width (W), and channel length (L) of the driving transistor DR. Vth is the critical voltage of the driving transistor DR.

[0103] As can be seen from the foregoing, the critical voltage Vth of the driving transistor DR can be used to compensate the light-emitting elements MLD and RLD during the light-emitting stage, so that they are not affected by the change of the critical voltage Vth, and they are not affected by the RC delay or IR voltage drop of the pixel driving voltage EVDD during driving.

[0104] Figures 9A and 9B are schematic diagrams illustrating a method of alternately driving a first light-emitting element and a second light-emitting element in the pixel circuit shown in Figures 4A to 7. The first light-emitting element and the second light-emitting element can be alternately driven by a first selection signal SEM and a second selection signal SER.

[0105] Referring to Figures 9A and 9B, the voltage of the first selection signal SEM and the voltage of the second selection signal SER can be generated as inverted waveforms, thereby generating voltages that are inverted to each other.

[0106] As shown in Figure 9A, the voltages of the first selection signal SEM and the second selection signal SER can be periodically alternated and reversed according to N (N is a natural number) frame periods (e.g., one frame period). For example, during the first frame period OFR, the voltage of the first selection signal SEM can be the gate turn-on voltage (e.g., gate low voltage VGL), and the voltage of the second selection signal SER can be the gate turn-on voltage (e.g., gate high voltage VGH). Next, during the second frame period EFR, the voltage of the second selection signal SER can be the gate low voltage VGL, and the voltage of the first selection signal SEM can be the gate high voltage VGH. The first frame period OFR can be an odd frame period, and the second frame period EFR can be an even frame period. In this case, the first light-emitting element MLD can be driven to emit light during the first frame period OFR, and the second light-emitting element RLD can be driven to emit light during the second frame period EFR. Therefore, even if one of the first light-emitting element MLD and the second light-emitting element RLD of a particular sub-pixel cannot be driven due to a defect, the corresponding sub-pixel can still be driven normally.

[0107] As shown in Figure 9B, the voltages of the first selection signal SEM and the second selection signal SER can be alternately reversed once or multiple times during the fourth period Pem of the emission phase within a single frame period. For example, the voltage of the first selection signal SEM can be reversed multiple times within the fourth period Pem of a specific frame period, while the voltage of the second selection signal SER is reversed with the opposite phase to that of the first selection signal SEM. In this case, the first light-emitting element MLD and the second light-emitting element RLD can be driven alternately to emit light within the fourth period Pem. Therefore, even if one of the first light-emitting element MLD and the second light-emitting element RLD of a specific sub-pixel cannot be driven due to a defect, the corresponding sub-pixel can still be driven normally.

[0108] Figure 10 shows a circuit diagram of one of the pixel circuits in the third embodiment of this disclosure. In this embodiment, descriptions that are repeated in the foregoing embodiments will be omitted.

[0109] Referring to FIG10, this pixel circuit may include a first light-emitting element MLD, a second light-emitting element RLD, a driving transistor DR, multiple switching transistors M11 and M12, and a compensation circuit 300. The driving transistor DR and the switching transistors M11 and M12 may be implemented as P-type channel transistors, but this disclosure is not limited thereto.

[0110] The first light-emitting element MLD and the second light-emitting element RLD can be connected in parallel to the driving transistor DR through switching transistors M11 and M12. The driving transistor DR may include a gate to which a data voltage Vdata is applied, a first electrode to which a pixel driving voltage EVDD is applied, and a second electrode connected to the anode electrode of the light-emitting elements MLD and RLD.

[0111] The first switching transistor M11 and the second switching transistor M12 can respond to the light emission signals EM2 and EM3 output from the gate driver 120 being turned on / off.

[0112] The first switching transistor M11 can be connected between the driving transistor DR and the anode electrode of the first light-emitting element MLD. The first switching transistor M11 can be turned on in response to the gate turn-on voltage (e.g., gate low voltage VGL) of the second light-emitting signal EM2, and can be turned off in response to the gate turn-off voltage (e.g., gate high voltage VGH) of the second light-emitting signal EM2. When the first switching transistor M11 is turned on, the first light-emitting element MLD can be electrically connected to the driving transistor DR, so that the first light-emitting element MLD can be driven.

[0113] The second switching transistor M12 can be connected between the driving transistor DR and the anode electrode of the second light-emitting element RLD. The second switching transistor M12 can be turned on in response to the gate turn-on voltage of the third light-emitting signal EM3, and can be turned off in response to the gate turn-off voltage of the third light-emitting signal EM3. When the second switching transistor M12 is turned on, the second light-emitting element RLD can be electrically connected to the driving transistor DR, thereby driving the second light-emitting element RLD.

[0114] FIG11 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure. In this embodiment, descriptions overlapping with the foregoing embodiments will be omitted.

[0115] Referring to Figure 11, the driving transistor DR, the first light-emitting element MLD, and the second light-emitting element RLD can be connected in series between the pixel driving voltage EVDD and the ground voltage EVSS.

[0116] The first light-emitting element MLD may include an anode electrode connected to the second electrode of the driving transistor DR, and a cathode electrode connected to the anode electrode of the second light-emitting element RLD. The second light-emitting element RLD may include an anode electrode connected to the cathode electrode of the first light-emitting element MLD and a cathode electrode to which a ground voltage EVSS is applied.

[0117] The first switching transistor M21 can be connected in parallel across the two ends of the second light-emitting element RLD. The first switching transistor M21 can be turned on in response to the gate turn-on voltage of the second light-emitting signal EM2, and can be turned off in response to the gate turn-off voltage of the second light-emitting signal EM2. When the first switching transistor M21 is turned on, the two ends of the second light-emitting element RLD can be short-circuited. At this time, current flows from the driving transistor DR into the first light-emitting element MLD, thereby enabling the first light-emitting element MLD to be driven, while the second light-emitting element RLD can be in the off state with its two ends short-circuited.

[0118] The second switching transistor M22 can be connected in parallel across the first light-emitting element MLD. The second switching transistor M22 can be turned on in response to the gate turn-on voltage of the third light-emitting signal EM3, and can be turned off in response to the gate turn-off voltage of the third light-emitting signal EM3. When the second switching transistor M22 is turned on, the two ends of the first light-emitting element MLD can be short-circuited. At this time, current flows from the driving transistor DR into the second light-emitting element RLD, thereby enabling the second light-emitting element RLD to be driven, while the first light-emitting element MLD can be in the off state with its two ends short-circuited.

[0119] Figure 12 is a circuit diagram showing in detail one example of the compensation circuit illustrated in Figure 10. In this embodiment, descriptions that are repeated in the foregoing embodiments will be omitted.

[0120] Referring to Figure 12, a pixel driving voltage EVDD, a ground voltage EVSS, and a reference voltage Vref can be applied to the pixel circuit. Data voltage Vdata and gate signals (first scan signal SCAN1, second scan signal SCAN2, first light emission signal EM1, second light emission signal EM2, and third light emission signal EM3) can be input to the pixel circuit.

[0121] The driving transistor DR may include a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3. The first node n1 may be connected to a power line to which a pixel driving voltage EVDD is applied.

[0122] The first switching transistor M11 may include a first electrode connected to the third node n3, a gate electrode connected to the fourth gate line GL4 to which the second light-emitting signal EM2 is applied, and a second electrode connected to the anode electrode of the first light-emitting element MLD. The second switching transistor M12 may include a first electrode connected to the third node n3, a gate electrode connected to the fifth gate line GL5 to which the third light-emitting signal EM3 is applied, and a second electrode connected to the anode electrode of the second light-emitting element RLD.

[0123] The first light-emitting element MLD may include an anode electrode connected to the second electrode of the first switching transistor M11, and a cathode electrode connected to a power line to which a ground voltage EVSS is applied. The second light-emitting element RLD may include an anode electrode connected to the second electrode of the second switching transistor M12, and a cathode electrode connected to a power line to which a ground voltage EVSS is applied.

[0124] The compensation circuit 300 may include a capacitor Cst and a third switching transistor M13 to a seventh switching transistor M17. The capacitor Cst may be connected between the second node n2 and the fourth node n14.

[0125] A third switching transistor M13 may be connected between a data line DL to which a data voltage Vdata is applied and a fourth node n14. The third switching transistor M13 may be turned on in response to a gate low voltage VGL of the first scan signal SCAN1 and turned off in response to a gate high voltage VGH of the first scan signal SCAN1. When the third switching transistor M13 is turned on, the data line DL may be electrically connected to the fourth node n14. The third switching transistor M13 may include a first electrode connected to the data line DL, a gate electrode connected to the first gate line GL1 to which the first scan signal SCAN1 is applied, and a second electrode connected to the fourth node n14.

[0126] A fourth switching transistor M14 may be connected between the second node n2 and the third node n3. The fourth switching transistor M14 may be turned on in response to a gate low voltage VGL of the first scan signal SCAN1, and may be turned off in response to a gate high voltage VGH of the first scan signal SCAN1. When the fourth switching transistor M14 is turned on, the second node n2 may be electrically connected to the third node n3. The fourth switching transistor M14 may include a first electrode connected to the second node n2, a gate electrode connected to the first gate line GL1, and a second electrode connected to the third node n3.

[0127] The fifth switching transistor M15 can be connected between the power line to which the reference voltage Vref is applied and the fourth node n14. The fifth switching transistor M15 can be turned on in response to the gate low voltage VGL of the first light emission signal EM1, and can be turned off in response to the gate high voltage VGH of the first light emission signal EM1. When the fifth switching transistor M15 is turned on, the reference voltage Vref can be applied to the fourth node n14. The fifth switching transistor M15 may include a first electrode connected to the fourth node n14, a gate electrode connected to the third gate line GL3 to which the first light emission signal EM1 is applied, and a second electrode to which the reference voltage Vref is applied.

[0128] The sixth switching transistor M16 can be connected between the second node n2 and the power line to which the reference voltage Vref is applied. The sixth switching transistor M16 can be turned on in response to the gate low voltage VGL of the second scan signal SCAN2, and can be turned off in response to the gate high voltage VGH of the second scan signal SCAN2. When the sixth switching transistor M16 is turned on, the reference voltage Vref can be applied to the second node n2. The sixth switching transistor M16 may include a first electrode connected to the second node n2, a gate electrode connected to the second gate line GL2 to which the second scan signal SCAN2 is applied, and a second electrode to which the reference voltage Vref is applied.

[0129] The seventh switching transistor M17 can be connected between the data line DL, to which the data voltage Vdata is applied, and the fourth node n14. The seventh switching transistor M17 can be turned on in response to the gate low voltage VGL of the second scan signal SCAN2, and can be turned off in response to the gate high voltage VGH of the second scan signal SCAN2. When the seventh switching transistor M17 is turned on, the data line DL can be electrically connected to the fourth node n14. The seventh switching transistor M17 may include a first electrode connected to the data line DL, a gate electrode connected to the second gate line GL2, and a second electrode connected to the fourth node n14.

[0130] Figure 13 is a circuit diagram showing in detail an example of the compensation circuit shown in Figure 11. In this embodiment, descriptions that are substantially the same as or overlap with those in the foregoing embodiments are omitted.

[0131] Referring to Figure 13, the driving transistor DR may include a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0132] The first light-emitting element MLD may include an anode electrode connected to the third node n3 and a cathode electrode connected to the fourth node n24. The second light-emitting element RLD may include an anode electrode connected to the fourth node n24 and a cathode electrode connected to a power line to which a ground voltage EVSS is applied.

[0133] The first switching transistor M21 may include a first electrode connected to the fourth node n24, a gate electrode connected to the fourth gate line GL4 to which the second light-emitting signal EM2 is applied, and a second electrode connected to the cathode electrode of the second light-emitting element RLD. The second switching transistor M22 may include a first electrode connected to the third node n3, a gate electrode connected to the fifth gate line GL5 to which the third light-emitting signal EM3 is applied, and a second electrode connected to the fourth node n24.

[0134] Capacitor Cst may be connected between the second node n2 and the fifth node n25. A third switching transistor M13 may be connected between the data line DL, to which a data voltage Vdata is applied, and the fifth node n25. When the third switching transistor M13 is turned on, the data line DL may be electrically connected to the fifth node n25. The third switching transistor M13 may include a first electrode connected to the data line DL, a gate electrode connected to the first gate line GL1 to which a first scan signal SCAN1 is applied, and a second electrode connected to the fifth node n25.

[0135] The fourth switching transistor M14 can be connected between the second node n2 and the third node n3. When the fourth switching transistor M14 is turned on, the second node n2 can be electrically connected to the third node n3.

[0136] The fifth switching transistor M15 can be connected between the power supply line for which the reference voltage Vref is applied and the fifth node n25. When the fifth switching transistor M15 is turned on, the reference voltage Vref can be applied to the fifth node n25. The fifth switching transistor M15 may include a first electrode connected to the fifth node n25, a gate electrode connected to the third gate line GL3 for which the first light emission signal EM1 is applied, and a second electrode for which the reference voltage Vref is applied.

[0137] The sixth switching transistor M16 can be connected between the second node n2 and the power line to which the reference voltage Vref is applied. When the sixth switching transistor M16 is turned on, the reference voltage Vref can be applied to the second node n2.

[0138] The seventh switching transistor M17 can be connected between the data line DL and the fifth node n25. When the seventh switching transistor M17 is turned on, the data line DL can be electrically connected to the fifth node n25. The seventh switching transistor M17 may include a first electrode connected to the data line DL, a gate electrode connected to the second gate line GL2, and a second electrode connected to the fifth node n25.

[0139] The pixel circuit illustrated in Figures 10 to 13 can be driven in the initialization stage, sampling stage, holding stage and light emission stage within one frame period.

[0140] Figure 14 is a waveform diagram illustrating the input signal of the pixel circuit shown in Figures 10 to 13. In Figure 14, "OFR" represents the first frame period and "EFR" represents the second frame period.

[0141] Referring to Figures 12 to 14, the initialization phase can be performed during the first cycle Pi. During the first cycle Pi, the voltage of the second scan signal SCAN2 can be the gate low voltage VGL, and the voltages of the first scan signal SCAN1 and the light emission signals EM1, EM2, and EM3 can be the gate high voltage VGH. Accordingly, during the first cycle Pi, the sixth switching transistor M16 and the seventh switching transistor M17 can be turned on, while the first switching transistor M11 or M21, the second switching transistor M12 or M22, the third switching transistor M13, the fourth switching transistor M14, and the fifth switching transistor M15 can be in the off state.

[0142] During the first cycle Pi, the reference voltage Vref can be applied to the second node n2 to initialize the gate voltage of the driving transistor DR to the reference voltage Vref.

[0143] During the first period Pi, the data voltage Vdata(N-1) of the previous pixel column (e.g., the (n-1)th pixel column) can be applied to the data line DL, and then the data voltage Vdata(N) of the current pixel line is applied to the data line DL. The data voltage Vdata(N) can be applied to the fourth node n14 shown in FIG12 and the fifth node n25 shown in FIG13 through the seventh switching transistor M17.

[0144] During the initialization phase, the seventh switching transistor M17 can apply the same data voltage Vdata(N) as the data voltage Vdata(N) applied to the fourth node n14 and the fifth node n25 connected to one electrode of capacitor Cst during the sampling phase to the fourth node n14 and the fifth node n25.

[0145] The sampling phase can be performed during the second cycle Ps. During the second cycle Ps, the voltage of the first scan signal SCAN1 can be the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the light emission signals EM1, EM2 and EM3 can be the gate high voltage VGH. Accordingly, during the second cycle Ps, the third switching transistor M13 and the fourth switching transistor M14 can be turned on, while the first switching transistor M11 or M21, the second switching transistor M12 or M22, and the fifth switching transistor M15 to the seventh switching transistor M17 can be turned off.

[0146] During the second cycle Ps, the data voltage Vdata(N) compensated by the threshold voltage Vth of the driving transistor DR can be stored in the capacitor Cst.

[0147] A holding phase can be performed during the third cycle Ph. During the third cycle Ph, the voltages of the first scan signal SCAN1, the second scan signal SCAN2, and the first light emission signal EM1 can be the gate high voltage VGH. Therefore, during the third cycle Ph, the voltage of capacitor Cst can maintain its previous state.

[0148] The light-emitting phase can be performed during the fourth cycle Pem. During the fourth cycle Pem, the voltage of the first light-emitting signal EM1 can be the gate low voltage VGL, and the voltage of the first scan signal SCAN1 and the second scan signal SCAN2 can be the gate high voltage VGH. Therefore, during the fourth cycle Pem, the fifth switching transistor M15 can be turned on, while the third switching transistor M13, the fourth switching transistor M14, the sixth switching transistor M16, and the seventh switching transistor M17 can be turned off. During the fourth cycle Pem, the driving transistor DR can generate current in response to the gate source voltage, and the selected light-emitting elements MLD and RLD can be alternately driven in response to the second light-emitting signal EM2 and the third light-emitting signal EM3. When the second light-emitting signal EM2 is at the gate low voltage VGL, the first light-emitting element MLD can be turned on and can emit light in response to the current generated by the driving transistor DR. When the third light-emitting signal EM3 is at the gate low voltage VGL, the second light-emitting element RLD can be turned on and can be driven to emit light in response to the current generated by the driving transistor DR.

[0149] During the light emission stage, the light emission elements MLD and RLD can be compensated by the threshold voltage Vth of the driving transistor DR, so that the light emission elements MLD and RLD are not affected by the change of the threshold voltage Vth, and can be driven without being affected by the RC delay or IR drop of the pixel driving voltage EVDD.

[0150] Figures 15A and 15B illustrate a method for alternately driving the first light-emitting element and the second light-emitting element in the pixel circuit shown in Figures 10 to 13. The first light-emitting element MLD and the second light-emitting element RLD can be driven alternately in response to the second light-emitting signal EM2 and the third light-emitting signal EM3.

[0151] Referring to Figures 15A and 15B, the voltages of the second light-emitting signal EM2 and the third light-emitting signal EM3 can be generated as inverted waveforms so that they are voltages that are inversely related to each other.

[0152] As shown in Figure 15A, the voltages of the second light-emitting signal EM2 and the third light-emitting signal EM3 can be alternately reversed over a period of N frame cycles (e.g., 1 frame cycle). For example, during the first frame cycle OFR, the voltage of the second light-emitting signal EM2 can be the gate-on voltage (e.g., gate low voltage VGL), while the voltage of the third light-emitting signal EM3 can be the gate-off voltage (e.g., gate high voltage VGH). Next, during the second frame cycle EFR, the voltage of the third light-emitting signal EM3 can be the gate low voltage VGL, while the voltage of the second light-emitting signal EM2 can be the gate high voltage VGH. In this case, the first light-emitting element MLD can be driven to emit light during the first frame cycle OFR, and the second light-emitting element RLD can be driven to emit light during the second frame cycle EFR. Accordingly, even if one of the first light-emitting element MLD and the second light-emitting element RLD of a particular sub-pixel cannot be driven due to a defect, the corresponding sub-pixel can still be driven normally.

[0153] As shown in Figure 15B, the voltages of the second light-emitting signal EM2 and the third light-emitting signal EM3 can be alternately reversed once or multiple times during the fourth period Pem. For example, during the fourth period Pem of a specific frame period, the voltage of the second light-emitting signal EM2 can be reversed multiple times, while the voltage of the third light-emitting signal EM3 can be reversed to be out of phase with the second light-emitting signal EM2. In this case, the first light-emitting element MLD and the second light-emitting element RLD can be alternately driven to emit light during the fourth period Pem. Accordingly, even if one of the first light-emitting element MLD and the second light-emitting element RLD of a specific sub-pixel cannot be driven due to a defect, the corresponding sub-pixel can still be driven normally.

[0154] Figure 16 is a circuit diagram showing the pixel circuit according to the fifth embodiment of the present disclosure.

[0155] Referring to Figure 16, the pixel circuit may include a first light-emitting element MLD, a second light-emitting element RLD, a driving transistor DR, a first switching transistor M31, a second switching transistor M32, a third switching transistor M33, and a compensation circuit 400. The driving transistor DR, the first switching transistor M31, the second switching transistor M32, the third switching transistor M33, and transistors M34 to M38 of the compensation circuit 400 may be implemented using, but are not limited to, P-type channel transistors.

[0156] The first light-emitting element MLD and the second light-emitting element RLD can be connected in parallel with the driving transistor DR, and can be connected in parallel with the power line to which the pixel driving voltage EVDD is applied through the first switching transistor M31 and the second switching transistor M32.

[0157] The driving transistor DR may include a first electrode connected to a first node n31, a gate electrode connected to a second node n32, and a second electrode connected to a third node n33. The first light-emitting element MLD may include an anode electrode connected to the second electrode of the first switching transistor M31 and a cathode electrode connected to the first node n31. The second light-emitting element RLD may include an anode electrode connected to the second electrode of the second switching transistor M32 and a cathode electrode connected to the first node n31.

[0158] The first switching transistor M31 and the second switching transistor M32 can be turned on / off according to the selection signals SEM and SER shown in Figures 8, 9A, and 9B. Furthermore, the first switching transistor M31 and the second switching transistor M32 can be turned on / off according to the light emission signals EM1 and EM2 shown in Figures 14, 15A, and 15B. The selection signals SEM and SER can be output from the selector 140. The light emission signals EM1 and EM2 can be output from the gate driver 120. In Figure 16, the light emission signals EM2 and EM3 are omitted. The third switching transistor M33 can be turned on / off in response to the light emission signal EM output from the gate driver 120.

[0159] A first switching transistor M31 may be connected between a power line to which a pixel driving voltage EVDD is applied and a first light-emitting element MLD. The first switching transistor M31 may be turned on in response to a gate turn-on voltage (e.g., a gate low voltage VGL of a first selection signal SEM or a second light-emitting signal EM2) and turned off in response to a gate turn-off voltage (e.g., a gate high voltage VGH of a first selection signal SEM or a second light-emitting signal EM2). When the first switching transistor M31 is turned on, the pixel driving voltage EVDD may be applied to the anode electrode of the first light-emitting element MLD. The first switching transistor M31 may include: a first electrode to which the pixel driving voltage EVDD is applied, a gate electrode to which the first selection pixel SEM or the second light-emitting signal EM2 is applied, and a second electrode connected to the anode electrode of the first light-emitting element MLD.

[0160] The second switching transistor M32 can be connected between the power line to which the pixel driving voltage EVDD is applied and the second light-emitting element RLD. The second switching transistor M32 can be turned on in response to the gate low voltage VGL of the second selection signal SER or the third light-emitting signal EM3, and can be turned off in response to the gate high voltage VGH of the second selection signal SER or the third light-emitting signal EM3. When the second switching transistor M32 is turned on, the pixel driving voltage EVDD can be applied to the anode electrode of the second light-emitting element RLD. The second switching transistor M32 may include a first electrode to which the pixel driving voltage EVDD is applied, a gate electrode to which the second selection signal SER or the third light-emitting signal EM3 is applied, and a second electrode connected to the anode electrode of the second light-emitting element RLD.

[0161] The third switching transistor M33 can be connected between the driving transistor DR and the power line to which the ground voltage EVSS is applied. The third switching transistor M33 can be turned on in response to the gate low voltage VGL of the light emission signal EM and turned off in response to the gate high voltage VGH of the light emission signal EM. When the third switching transistor M33 is turned on, the second electrode of the driving transistor DR can be connected to the power line to which the ground voltage EVDD is applied. The third switching transistor M33 may include a first electrode connected to the third node n33, a gate electrode to which the light emission signal EM is applied, and a second electrode to which the ground voltage EVSS is applied.

[0162] The compensation circuit 400 can be connected to a data line to which a data voltage Vdata is applied and a gate line to which gate signals (first scan signal SCAN1, second scan signal SCAN2, and light emission signal EM) are applied. The compensation circuit 400 may include a fourth switching transistor M34 to a ninth switching transistor M39 and capacitors C1 and C2. The compensation circuit 400 can sample the threshold voltage of the driving transistor DR in capacitors C1 and C2, and then use the threshold voltage of the driving transistor DR to compensate the gate voltage of the driving transistor DR.

[0163] The first capacitor C1 can be connected between the second node n32 and the fourth node n34. The second capacitor C2 can be connected between the first node n31 and the second node n32.

[0164] The fourth switching transistor M34 can be connected between the data line DL, to which the data voltage Vdata is applied, and the fourth node n34. The fourth switching transistor M34 can be turned on in response to the gate low voltage VGL of the first scan signal SCAN1, and can be turned off in response to the gate high voltage VGH of the first scan signal SCAN1. When the fourth switching transistor M34 is turned on, the data line DL can be electrically connected to the fourth node n34. The fourth switching transistor M34 may include a first electrode connected to the data line DL, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the fourth node n34.

[0165] A fifth switching transistor M35 may be connected between the second node n32 and the third node n33. The fifth switching transistor M35 may be turned on in response to a gate low voltage VGL of the first scan signal SCAN1, and may be turned off in response to a gate high voltage VGH of the first scan signal SCAN1. When the fifth switching transistor M35 is turned on, the second node n32 may be electrically connected to the third node n33. The fifth switching transistor M35 may include a first electrode connected to the second node n32, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the third node n33.

[0166] The sixth switching transistor M36 can be connected between the power supply line to which the reference voltage Vref is applied and the fourth node n34. The sixth switching transistor M36 can be turned on in response to the gate low voltage VGL of the light emission signal EM and turned off in response to the gate high voltage VGH of the light emission signal EM. When the sixth switching transistor M36 is turned on, the reference voltage Vref can be applied to the fourth node n34. The sixth switching transistor M36 may include a first electrode connected to the fourth node n34, a gate electrode to which the light emission signal EM is applied, and a second electrode to which the reference voltage Vref is applied.

[0167] The seventh switching transistor M37 can be connected between the second node n32 and the power line to which the reference voltage Vref is applied. The seventh switching transistor M37 can be turned on in response to the gate low voltage VGL of the second scan signal SCAN2, and can be turned off in response to the gate high voltage VGH of the second scan signal SCAN2. When the seventh switching transistor M37 is turned on, the reference voltage Vref can be applied to the second node n32. The seventh switching transistor M37 may include a first electrode connected to the second node n32, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode to which the reference voltage Vref is applied.

[0168] The eighth switching transistor M38 can be connected between the data line DL, to which the data voltage Vdata is applied, and the fourth node n34. The eighth switching transistor M38 can be turned on in response to the gate low voltage VGL of the second scan signal SCAN2, and can be turned off in response to the gate high voltage VGH of the second scan signal SCAN2. When the eighth switching transistor M38 is turned on, the data line DL can be electrically connected to the fourth node n34. The eighth switching transistor M38 may include a first electrode connected to the data line DL, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the fourth node n34.

[0169] The ninth switching transistor M39 can be connected between the power line to which the pixel driving voltage EVDD is applied and the first node n31. The ninth switching transistor M39 can be turned on in response to the gate low voltage VGL of the first scan signal SCAN1 and turned off in response to the gate high voltage VGH of the first scan signal SCAN1. When the ninth switching transistor M39 is turned on, the power line to which the pixel driving voltage EVDD is applied is electrically connected to the first node n31, thereby preventing the first light-emitting element MLD and the second light-emitting element RLD from being driven. The ninth switching transistor M39 may include a first electrode connected to the power line to which the pixel driving voltage EVDD is applied, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the first node n31.

[0170] FIG17 is a circuit diagram illustrating a pixel circuit according to a sixth embodiment of the present disclosure. In this embodiment, descriptions that are substantially the same as or repeat the descriptions of the foregoing embodiments shown in FIG16 may be omitted. For example, the descriptions of the third switching transistor M33 and the compensation circuit 400 are omitted.

[0171] Referring to FIG17, the first light-emitting element MLD and the second light-emitting element RLD may be connected in series between the power line to which the pixel driving voltage EVDD is applied and the first node n31. The first light-emitting element MLD may include an anode electrode connected to the power line to which the pixel driving voltage EVDD is applied, and a cathode electrode connected to the anode electrode of the second light-emitting element RLD. The second light-emitting element RLD may include an anode electrode connected to the cathode electrode of the first light-emitting element MLD and a cathode electrode connected to the first node n31.

[0172] The first switching transistor M41 and the second switching transistor M42 can be turned on / off in response to the first selection signal SEM and the second selection signal SER shown in Figures 9A and 9B. In addition, the first switching transistor M41 and the second switching transistor M42 can also be turned on / off in response to the light emission signals EM2 and EM3 shown in Figures 15A and 15B.

[0173] The first switching transistor M41 may include a first electrode connected to the anode electrode of the second light-emitting element RLD, a gate electrode to which a first selection signal SEM or a second light-emitting signal EM2 is applied, and a second electrode connected to the cathode electrode of the second light-emitting element RLD. The second switching transistor M42 may include a first electrode connected to the anode electrode of the first light-emitting element MLD, a gate electrode to which a second selection signal SER or a third light-emitting signal EM3 is applied, and a second electrode connected to the cathode electrode of the first light-emitting element MLD.

[0174] The pixel circuit can be connected to an external compensation circuit via the sensing line SL shown in Figures 18 and 19.

[0175] Figure 18 is a circuit diagram showing the pixel circuit according to the seventh embodiment of the present disclosure.

[0176] Referring to Figure 18, the pixel circuit may include a first light-emitting element MLD, a second light-emitting element RLD, a driving transistor DR, a capacitor Cst, and multiple switching transistors M51 to M54. The first switching transistor M51 and the second switching transistor M52 can be implemented using P-type channel transistors, but this disclosure is not limited thereto. The driving transistor DR, the third switching transistor M53, and the fourth switching transistor M54 can be implemented using N-type channel transistors, but this disclosure is not limited thereto.

[0177] The first light-emitting element MLD and the second light-emitting element RLD can be connected in parallel to the driving transistor DR through the first switching transistor M51 and the second switching transistor M52.

[0178] The driving transistor DR may include a first electrode connected to a first node n51, a gate electrode connected to a second node n52, and a second electrode connected to a third node n53. A pixel driving voltage EVDD may be applied to the first node n51. A capacitor Cst may be connected between the second node n52 and the third node n53.

[0179] The first light-emitting element MLD may include an anode electrode connected to the second electrode of the first switching transistor M51, and a cathode electrode to which a ground voltage EVSS is applied. The second light-emitting element RLD may include an anode electrode connected to the second electrode of the second switching transistor M52, and a cathode electrode to which a ground voltage EVSS is applied.

[0180] The first switching transistor M51 and the second switching transistor M52 can be turned on / off in response to the selection signals SEM and SER shown in Figures 9A and 9B. In addition, the first switching transistor M51 and the second switching transistor M52 can also be turned on / off in response to the light emission signals EM2 and EM3 shown in Figures 15A and 15B.

[0181] The first switching transistor M51 can be turned on in response to a gate turn-on voltage (e.g., the gate low voltage VGL of the first selection signal SEM or the second light emission signal EM2) and turned off in response to a gate turn-off voltage (e.g., the gate high voltage VGH of the first selection signal SEM or the second light emission signal EM2). When the first switching transistor M51 is turned on, the second electrode of the driving transistor DR can be connected to the anode electrode of the first light-emitting element MLD. The first switching transistor M51 may include a first electrode connected to the third node n53, a gate electrode for applying the first selection signal SEM or the second light emission signal EM2, and a second electrode connected to the anode electrode of the first light-emitting element MLD.

[0182] The second switching transistor M52 can be turned on in response to a gate turn-on voltage (e.g., the gate low voltage VGL of the second selection signal SER or the third light-emitting signal EM3), and can be turned off in response to a gate turn-off voltage (e.g., the gate high voltage VGH of the second selection signal SER or the third light-emitting signal EM3). When the second switching transistor M52 is turned on, the second electrode of the driving transistor DR can be connected to the anode electrode of the second light-emitting element RLD. The second switching transistor M52 may include a first electrode connected to the third node n53, a gate electrode for applying the second selection signal SER or the third light-emitting signal EM3, and a second electrode connected to the anode electrode of the second light-emitting element RLD.

[0183] A third switching transistor M53 may be connected between a data line DL to which a data voltage Vdata is applied and a second node n52. The third switching transistor M53 may be turned on in response to a gate turn-on voltage (e.g., the gate high voltage VGH of the first scan signal SCAN) and turned off in response to a gate turn-off voltage (e.g., the gate low voltage VGL of the first scan signal SCAN). When the third switching transistor M53 is turned on, the data line DL may be electrically connected to the second node n52. The third switching transistor M53 may include a first electrode connected to the data line DL, a gate electrode connected to the first gate line GL1 to which the first scan signal SCAN is applied, and a second electrode connected to the second node n52.

[0184] A fourth switching transistor M54 may be connected between the third node n53 and the sensing line SL. An external compensation circuit may be connected to the sensing line SL. The sensing line SL may be initialized when a reference voltage Vref is applied. The fourth switching transistor M54 may be turned on in response to a gate turn-on voltage (e.g., the gate high voltage VGH of the second scan signal SEN) and turned off in response to a gate turn-off voltage (e.g., the gate low voltage VGL of the second scan signal SEN). The pulse of the second scan signal SEN may be generated in the same phase as the pulse of the first scan signal SCAN. When the fourth switching transistor M54 is turned on, the sensing line SL may be electrically connected to the third node n53. The fourth switching transistor M54 may include a first electrode connected to the third node n53, a gate electrode connected to the second gate line GL2 to which the second scan signal SEN is applied, and a second electrode connected to the sensing line SL.

[0185] FIG19 is a circuit diagram illustrating a pixel circuit according to an eighth embodiment of the present disclosure. In this embodiment, the descriptions of the embodiments shown in FIG18 will not be substantially the same or overlapping. For example, the driving transistor DR, the third switching transistor M53, and the fourth switching transistor M54 will not be described.

[0186] Referring to FIG19, the first light-emitting element MLD and the second light-emitting element RLD can be connected in series between the third node n53 and the power line to which the ground voltage EVSS is applied. The first light-emitting element MLD may include an anode electrode connected to the third node n53 and a cathode electrode connected to the fourth node n54. The second light-emitting element RLD may include an anode electrode connected to the fourth node n54 and a cathode electrode connected to the power line to which the ground voltage EVSS is applied.

[0187] The first switching transistor M61 and the second switching transistor M62 can be turned on / off in response to the selection signals SEM and SER shown in Figures 9A and 9B. In addition, the first switching transistor M61 and the second switching transistor M62 can also be turned on / off in response to the light emission signals EM2 and EM3 shown in Figures 15A and 15B.

[0188] The first switching transistor M61 may include a first electrode connected to the anode electrode of the second light-emitting element RLD, a gate electrode to which a first selection signal SEM or a second light-emitting signal EM2 is applied, and a second electrode connected to the cathode electrode of the second light-emitting element RLD. The second switching transistor M62 may include a first electrode connected to the anode electrode of the first light-emitting element MLD, a gate electrode to which a second selection signal SER or a third light-emitting signal EM3 is applied, and a second electrode connected to the cathode electrode of the first light-emitting element MLD.

[0189] One or more embodiments disclosed herein may be described as follows.

[0190] According to one or more embodiments of the present invention, a pixel circuit may include a driving transistor configured to generate current; and a first light-emitting element and a second light-emitting element connected in parallel or in series with the driving transistor. The first light-emitting element and the second light-emitting element are alternately driven by the current from the driving transistor.

[0191] According to one or more embodiments of the present invention, the pixel circuit may further include: a first switching transistor; a second switching transistor; and a third switching transistor. The first and second light-emitting elements may be connected in parallel with the driving transistor through the first switching transistor, the second switching transistor, and the third switching transistor.

[0192] According to one or more embodiments of this disclosure, a first switching transistor may be connected between a third switching transistor and the anode electrode of a first light-emitting element, and may be turned on in response to a first control signal applied to the gate electrode of the first switching transistor. A second switching transistor may be connected between the third switching transistor and the anode electrode of a second light-emitting element, and may be turned on in response to a second control signal applied to the gate of the second switching transistor. When turned on in response to a third control signal applied to the gate of the third switching transistor, the third switching transistor may electrically connect a driving transistor to the first or second switching transistor.

[0193] According to one or more embodiments of this disclosure, the pixel circuit may further include: a first switching transistor, a second switching transistor, and a third switching transistor. The first light-emitting element and the second light-emitting element may be connected in series to the driving transistor via the third switching transistor. The first switching transistor may be connected between the two ends of the second light-emitting element and may be turned on in response to a first control signal applied to the gate electrode of the first switching transistor. The second switching transistor may be connected between the two ends of the first light-emitting element and may be turned on in response to a second control signal applied to the gate electrode of the second switching transistor. When turned on in response to a third control signal applied to the gate electrode of the third switching transistor, the third switching transistor may electrically connect the driving transistor to the anode electrode of the first light-emitting element.

[0194] According to one or more embodiments of the present disclosure, the driving transistor may include a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node.

[0195] According to one or more embodiments of the present invention, the pixel circuit may further include: a first switching transistor, including a first electrode connected to a fourth node, a gate electrode to which a first control signal is applied, and a second electrode connected to an anode electrode of a first light-emitting element; a second switching transistor, including a first electrode connected to a fourth node, a gate electrode to which a second control signal is applied, and a second electrode connected to an anode electrode of a second light-emitting element; a third switching transistor, including a first electrode connected to a third node, a gate electrode to which a light-emitting signal is applied, and a second electrode connected to a fourth node; and a fourth switching transistor, including a first electrode connected to a data line to which a data voltage is applied, and a gate electrode to which a first scan signal is applied. The first light-emitting element may include an anode electrode connected to the second electrode of the first switch transistor and a cathode electrode to which a first scan signal is applied, and a second electrode connected to the third node; a sixth switch transistor may include a first electrode connected to the fifth node, a gate electrode to which a light-emitting signal is applied, and a second electrode to which a reference voltage is applied; a seventh switch transistor may include a first electrode connected to the second node, a gate electrode to which a second scan signal is applied, and a second electrode to which a reference voltage is applied; an eighth switch transistor may include a first electrode connected to a data line, a gate electrode to which a second scan signal is applied, and a second electrode connected to the fifth node; and a capacitor connected between the second node and the fifth node. The first light-emitting element may include an anode electrode connected to the second electrode of the first switch transistor and a cathode electrode to which a ground voltage is applied. The second light-emitting element may include an anode electrode connected to the second electrode of the second switch transistor and a cathode electrode to which a ground voltage is applied.

[0196] According to one or more embodiments of this disclosure, the pixel circuit may further include: a first switching transistor, including a first electrode connected to a fifth node, a gate electrode to which a first control signal is applied, and a second electrode connected to a cathode electrode of a second light-emitting element; a second switching transistor, including a first electrode connected to a fourth node, a gate electrode to which a second control signal is applied, and a second electrode connected to a fifth node; a third switching transistor, including a first electrode connected to a third node, a gate electrode to which a light-emitting signal is applied, and a second electrode connected to a fourth node; a fourth switching transistor, including a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to a cathode electrode of a second light-emitting element. A second electrode connected to the sixth node; a fifth switching transistor, including a first electrode connected to the second node, a gate electrode to which a first scan signal is applied, and a second electrode connected to the third node; a sixth switching transistor, including a first electrode connected to the sixth node, a gate electrode to which a light emission signal is applied, and a second electrode to which a reference voltage is applied; a seventh switching transistor, including a first electrode connected to the second node, a gate electrode to which a second scan signal is applied, and a second electrode to which a reference voltage is applied; an eighth switching transistor, including a first electrode connected to a data line, a gate electrode to which a second scan signal is applied, and a second electrode connected to the sixth node; and a capacitor connected between the second node and the sixth node. A first light-emitting element may include an anode electrode connected to the fourth node and a cathode electrode connected to the fifth node. A second light-emitting element may include an anode electrode connected to the fifth node and a cathode electrode to which a ground voltage is applied.

[0197] According to one or more embodiments of this disclosure, the pixel circuit may further include: a first switching transistor, including a first electrode connected to a third node, a gate electrode to which a first control signal is applied, and a second electrode connected to the anode electrode of the first light-emitting element; and a second switching transistor, including a first electrode connected to the third node, a gate electrode to which a second control signal is applied, and a second electrode connected to the anode electrode of the second light-emitting element. The first light-emitting element may include an anode electrode connected to the second electrode of the first switching transistor and a cathode electrode to which a ground voltage is applied. The second light-emitting element may include an anode electrode connected to the second electrode of the second switching transistor and a cathode electrode to which a ground voltage is applied.

[0198] According to one or more embodiments of this disclosure, the pixel circuit may further include: a first switching transistor, including a first electrode connected to a fourth node, a gate electrode to which a first control signal is applied, and a second electrode connected to a cathode electrode of a second light-emitting element; and a second switching transistor, including a first electrode connected to a third node, a gate electrode to which a second control signal is applied, and a second electrode connected to the fourth node. The first light-emitting element may include an anode electrode connected to the third node and a cathode electrode connected to the fourth node. The second light-emitting element may include an anode electrode connected to the fourth node and a cathode electrode to which a ground voltage is applied.

[0199] According to one or more embodiments of this disclosure, the pixel circuit further includes: a first switching transistor, including a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first control signal is applied, and a second electrode connected to the anode electrode of the first light-emitting element; and a second switching transistor, including a first electrode to which a pixel driving voltage is applied, a gate electrode to which a second control signal is applied, and a second electrode connected to the anode electrode of the second light-emitting element. The first light-emitting element may include an anode electrode connected to the second electrode of the first switching transistor and a cathode electrode connected to the first node. The second light-emitting element may include an anode electrode connected to the second electrode of the second switching transistor and a cathode electrode connected to the first node.

[0200] According to one or more embodiments of this disclosure, the pixel circuit further includes: a first switching transistor comprising a first electrode connected to the anode electrode of the second light-emitting element, a gate electrode to which a first control signal is applied, and a second electrode connected to the cathode electrode of the second light-emitting element; and a second switching transistor comprising a first electrode connected to the anode electrode of the first light-emitting element, a gate electrode to which a second control signal is applied, and a second electrode connected to the cathode electrode of the first light-emitting element. The first light-emitting element and the second light-emitting element are connected in series between a power line to which a pixel driving voltage is applied and a first node.

[0201] According to one or more embodiments of the present invention, the pixel circuit further includes: a first capacitor connected between the second node and the fourth node; a second capacitor connected between the first node and the second node; a third switching transistor including a first electrode connected to the third node, a gate electrode to which a light emission signal is applied, and a second electrode to which a ground voltage is applied; a fourth switching transistor including a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to the fourth node; a fifth switching transistor including a first electrode connected to the second node, a gate electrode to which the first scan signal is applied, and a second electrode connected to the fourth node. The second electrode is connected to the third node; the sixth switching transistor includes a first electrode connected to the fourth node, a gate electrode to which a light emission signal is applied, and a second electrode to which a reference voltage is applied; the seventh switching transistor includes a first electrode connected to the second node, a gate electrode to which a second scan signal is applied, and a second electrode to which a reference voltage is applied; the eighth switching transistor includes a first electrode connected to a data line, a gate electrode to which a second scan signal is applied, and a second electrode connected to the fourth node; and the ninth switching transistor includes a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to the first node.

[0202] According to one or more embodiments of this disclosure, a frame period may include a first period, a second period following the first period, a third period following the second period, and a fourth period following the third period. During the first period, the voltage of the second scan signal may be a gate-on voltage, and the voltages of the first scan signal and the light-emitting signal may be gate-off voltages. During the second period, the voltage of the first scan signal may be a gate-on voltage, and the voltages of the second scan signal and the light-emitting signal may be gate-off voltages. During the third period, the voltages of the first scan signal, the second scan signal, and the light-emitting signal may be gate-off voltages. During the fourth period, the voltage of the light-emitting signal may be a gate-on voltage, and the voltages of the first scan signal and the second scan signal may be gate-off voltages. Each of the switching transistors may be turned on in response to the gate-on voltage and turned off in response to the gate-off voltage.

[0203] According to one or more embodiments of this disclosure, the pixel circuit further includes: a first switching transistor, including a first electrode connected to a third node, a gate electrode to which a first control signal is applied, and a second electrode connected to the anode electrode of a first light-emitting element; a second switching transistor, including a first electrode connected to a third node, a gate electrode to which a second control signal is applied, and a second electrode connected to the anode electrode of a second light-emitting element; a third switching transistor, including a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to a second node; and a fourth switching transistor, including a first electrode connected to a third node, a gate electrode to which a second scan signal is applied, and a second electrode connected to a sensing line. The first light-emitting element may include an anode electrode connected to the second electrode of the first switching transistor and a cathode electrode to which a ground voltage is applied. The second light-emitting element may include an anode electrode connected to the second electrode of the second switching transistor and a cathode electrode to which a ground voltage is applied.

[0204] According to one or more embodiments of this disclosure, the pixel circuit further includes: a first switching transistor, comprising a first electrode connected to the anode electrode of the second light-emitting element, a gate electrode for applying a first control signal, and a second electrode connected to the cathode electrode of the second light-emitting element; a second switching transistor, comprising a first electrode connected to the anode electrode of the first light-emitting element, a gate electrode for applying a second control signal, and a second electrode connected to the cathode electrode of the first light-emitting element; a third switching transistor, comprising a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to a second node; and a fourth switching transistor, comprising a first electrode connected to a third node, a gate electrode to which a second scan signal is applied, and a second electrode connected to a sensing line. The first light-emitting element may include an anode electrode connected to the third node and a cathode electrode connected to the fourth node. The second light-emitting element may include an anode electrode connected to the fourth node and a cathode electrode connected to a power line to which a ground voltage is applied.

[0205] According to one or more embodiments of the present disclosure, the voltages of the first and second control signals can be periodically reversed according to a frame period of N (N is a natural number), or can be reversed periodically within a light emission cycle of one frame period.

[0206] According to one or more embodiments of the present invention, the voltages of the first and second control signals alternately reverse periodically with a frame period.

[0207] According to one or more embodiments of the present invention, a display device may include: a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits arranged thereon; a data driving circuit connected to the data lines; and a gate driving circuit connected to the gate lines. Each of the pixel circuits may include: a driving transistor configured to generate current; and first and second light-emitting elements electrically connected to the driving transistor in parallel or series. The first and second light-emitting elements may be alternately driven by current from the driving transistor.

[0208] According to one or more embodiments of this disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, deformable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers, laptop personal computers, mini-notebooks, workstations, navigation devices, vehicle navigation devices, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, electronic signage devices, gaming devices, laptops, monitors, cameras, camcorders, and home appliances, etc. Furthermore, the display device according to one or more embodiments of this disclosure can also be applied to organic light-emitting devices or inorganic light-emitting devices.

[0209] The purpose to be achieved by this disclosure, the means to achieve that purpose, and the effects of this disclosure described above are not essential technical features for specifying the scope of the patent application. Therefore, the interpretation of the scope of the patent application should not be limited to the detailed description of this disclosure.

[0210] Although the embodiments disclosed herein have been described in more detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be implemented in many different forms without departing from the technical spirit of this disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical spirit of this disclosure. The scope of the technical spirit of this disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not constitute a limitation on this disclosure. [Simplified Explanation of the Diagram]

[0014] For those skilled in the art, the foregoing and other objects, features and advantages of this disclosure will become more apparent from the detailed description of its exemplary embodiments with reference to the accompanying drawings, in which: FIG1 is a block diagram illustrating a display device according to an embodiment of this disclosure; FIG2 is a schematic diagram illustrating an example of a gate driver disposed in a display area of ​​a display panel; FIG3 is a schematic diagram illustrating an example of a video wall display; FIG4A and FIG4B are circuit diagrams illustrating a pixel circuit according to a first embodiment of this disclosure; FIG5A and FIG5B are circuit diagrams illustrating a pixel circuit according to a second embodiment of this disclosure; FIG6 is a circuit diagram illustrating in detail an example of a compensation circuit shown in FIG4A and FIG4B; FIG7 is a circuit diagram illustrating in detail an example of a compensation circuit shown in FIG5A and FIG5B; FIG8 is a waveform diagram of the input signal of the pixel circuit shown in FIG4A to FIG7; FIG9A and FIG9B are schematic diagrams illustrating a method of alternately driving the first and second light-emitting elements in the pixel circuit shown in FIG4A to FIG7; FIG10 is a circuit diagram illustrating a pixel circuit according to a third embodiment of this disclosure. Figure 11 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure; Figure 12 is a circuit diagram showing in detail an example of the compensation circuit shown in Figure 10; Figure 13 is a circuit diagram showing in detail an example of the compensation circuit shown in Figure 11; Figure 14 is a waveform diagram showing the input signal of the pixel circuit shown in Figures 10 to 13; Figures 15A and 15B are schematic diagrams of a method for alternately driving the first and second light-emitting elements in the pixel circuit shown in Figures 10 to 13; Figure 16 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present disclosure; Figure 17 is a circuit diagram showing a pixel circuit according to a sixth embodiment of the present disclosure; Figure 18 is a circuit diagram showing a pixel circuit according to a seventh embodiment of the present disclosure; and Figure 19 is a circuit diagram showing a pixel circuit according to an eighth embodiment of the present disclosure.

Claims

1. A pixel circuit comprising: a single driving transistor configured to generate a current; and a first light-emitting element and a second light-emitting element electrically connected in parallel or in series to a common terminal of the single driving transistor, wherein the first light-emitting element and the second light-emitting element are alternately driven by the current from the single driving transistor.

2. The pixel circuit as claimed in claim 1 further comprises: a first switching transistor; a second switching transistor; and a third switching transistor, wherein the first light-emitting element and the second light-emitting element are connected in parallel to the single driving transistor via the first switching transistor, the second switching transistor, and the third switching transistor, wherein the first switching transistor is connected between the third switching transistor and an anode electrode of the first light-emitting element, and is turned on in response to a first control signal applied to a gate electrode of the first switching transistor, wherein the second switching transistor is connected between the third switching transistor and an anode electrode of the second light-emitting element, and is turned on in response to a second control signal applied to a gate electrode of the second switching transistor, and wherein when the third switching transistor is turned on in response to a third control signal applied to a gate electrode of the third switching transistor, the third switching transistor electrically connects the single driving transistor to the first switching transistor or the second switching transistor.

3. The pixel circuit as claimed in claim 1 further comprises: a first switching transistor; a second switching transistor; and a third switching transistor, wherein the first light-emitting element and the second light-emitting element are connected in series to the single driving transistor via the third switching transistor, wherein the first switching transistor is connected between the two ends of the second light-emitting element and is turned on in response to a first control signal applied to one gate electrode of the first switching transistor; wherein the second switching transistor is connected between the two ends of the first light-emitting element and is turned on in response to a second control signal applied to one gate electrode of the second switching transistor, and wherein when the third switching transistor is turned on in response to a third control signal applied to one gate electrode of the third switching transistor, the third switching transistor electrically connects the single driving transistor to one anode electrode of the first light-emitting element.

4. The pixel circuit as claimed in claim 1, wherein the single driving transistor includes a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node.

5. The pixel circuit as described in claim 4 further comprises: a plurality of switching transistors, the switching transistors including: A first switching transistor includes a first electrode connected to a fourth node, a gate electrode to which a first control signal is applied, and a second electrode connected to an anode electrode of the first light-emitting element; a second switching transistor includes a first electrode connected to the fourth node, a gate electrode to which a second control signal is applied, and a second electrode connected to an anode electrode of the second light-emitting element; a third switching transistor includes a first electrode connected to the third node, a gate electrode to which a light-emitting signal is applied, and a second electrode connected to the fourth node; a fourth switching transistor includes a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to a fifth node; a fifth switching transistor includes a first electrode connected to the second node, a gate electrode to which the first scan signal is applied, and a second electrode connected to the third node. The fifth node has a second electrode; a sixth switching transistor, including a first electrode connected to the fifth node, a gate electrode to which the light emission signal is applied, and a second electrode to which a reference voltage is applied; a seventh switching transistor, including a first electrode connected to the second node, a gate electrode to which a second scan signal is applied, and a second electrode to which the reference voltage is applied; an eighth switching transistor, including a first electrode connected to the data line, a gate electrode to which the second scan signal is applied, and a second electrode connected to the fifth node; and a capacitor connected between the second node and the fifth node, wherein the first light-emitting element includes an anode electrode connected to the second electrode of the first switching transistor and a cathode electrode to which a ground voltage is applied, and wherein the second light-emitting element includes an anode electrode connected to the second electrode of the second switching transistor and a cathode electrode to which the ground voltage is applied.

6. The pixel circuit as described in claim 4 further comprises: a plurality of switching transistors, the switching transistors including: A first switching transistor includes a first electrode connected to a fifth node, a gate electrode to which a first control signal is applied, and a second electrode connected to a cathode electrode of the second light-emitting element; a second switching transistor includes a first electrode connected to a fourth node, a gate electrode to which a second control signal is applied, and a second electrode connected to the fifth node; a third switching transistor includes a first electrode connected to a third node, a gate electrode to which a light-emitting signal is applied, and a second electrode connected to the fourth node; a fourth switching transistor includes a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to a sixth node; a fifth switching transistor includes a first electrode connected to the second node, a gate electrode to which the first scan signal is applied, and a second electrode connected to the fifth node. The third node includes a second electrode; a sixth switching transistor, comprising a gate electrode connected to a first electrode of the sixth node, to which the light emission signal is applied, and a second electrode to which a reference voltage is applied; a seventh switching transistor, comprising a gate electrode connected to a first electrode of the second node, to which a second scan signal is applied, and a second electrode to which the reference voltage is applied; an eighth switching transistor, comprising a first electrode connected to the data line, a gate electrode to which the second scan signal is applied, and a second electrode connected to the sixth node; and a capacitor connected between the second node and the sixth node, wherein the first light-emitting element comprises an anode electrode connected to the fourth node and a cathode electrode connected to the fifth node, and wherein the second light-emitting element comprises a cathode electrode connected to the anode electrode of the fifth node and to which a ground voltage is applied.

7. The pixel circuit as claimed in claim 4 further comprises: a first switching transistor, including a first electrode connected to the third node, a gate electrode to which a first control signal is applied, and a second electrode connected to an anode electrode of the first light-emitting element; and a second switching transistor, including a first electrode connected to the third node, a gate electrode to which a second control signal is applied, and a second electrode connected to an anode electrode of the second light-emitting element; wherein the first light-emitting element includes an anode electrode connected to the second electrode of the first switching transistor and a cathode electrode to which a ground voltage is applied, and wherein the second light-emitting element includes an anode electrode connected to the second electrode of the second switching transistor and a cathode electrode to which the ground voltage is applied.

8. The pixel circuit as claimed in claim 4 further comprises: a first switching transistor including a first electrode connected to a fourth node, a gate electrode to which a first control signal is applied, and a second electrode connected to a cathode electrode of the second light-emitting element; and a second switching transistor including a first electrode connected to a third node, a gate electrode to which a second control signal is applied, and a second electrode connected to the fourth node, wherein the first light-emitting element includes an anode electrode connected to the third node and a cathode electrode connected to the fourth node, and wherein the second light-emitting element includes a cathode electrode connected to the anode electrode of the fourth node and to which a ground voltage is applied.

9. The pixel circuit as described in claim 4 further includes a plurality of switching transistors, the switching transistors comprising: A first switching transistor includes a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first control signal is applied, and a second electrode connected to an anode electrode of the first light-emitting element; and a second switching transistor includes a first electrode to which the pixel driving voltage is applied, a gate electrode to which a second control signal is applied, and a second electrode connected to an anode electrode of the second light-emitting element, wherein the first light-emitting element includes an anode electrode connected to the second electrode of the first switching transistor and a cathode electrode connected to the first node, and wherein the second light-emitting element includes an anode electrode connected to the second electrode of the second switching transistor and a cathode electrode connected to the first node.

10. The pixel circuit as claimed in claim 9, further comprising: a first capacitor connected between the second node and a fourth node; and a second capacitor connected between the first node and the second node; and the switching transistors further comprising: A third switching transistor includes a first electrode connected to the third node, a gate electrode to which a light emission signal is applied, and a second electrode to which a ground voltage is applied; a fourth switching transistor includes a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to the fourth node; a fifth switching transistor includes a first electrode connected to the second node, a gate electrode to which the first scan signal is applied, and a second electrode connected to the third node; a sixth switching transistor includes a first electrode connected to the fourth node, a gate electrode to which a light emission signal is applied, and a second electrode to which a ground voltage is applied. The transistor includes a gate electrode for the light emission signal and a second electrode for which a reference voltage is applied; a seventh switching transistor includes a first electrode connected to the second node, a gate electrode for which a second scan signal is applied, and a second electrode for which the reference voltage is applied; an eighth switching transistor includes a first electrode connected to the data line, a gate electrode for which the second scan signal is applied, and a second electrode connected to the fourth node; and a ninth switching transistor includes a first electrode for which a pixel driving voltage is applied, a gate electrode for which the first scan signal is applied, and a second electrode connected to the first node.

11. The pixel circuit as described in claim 4 further comprises a plurality of switching transistors, the switching transistors including: A first switching transistor includes a first electrode connected to an anode electrode of the second light-emitting element, a gate electrode to which a first control signal is applied, and a second electrode connected to a cathode electrode of the second light-emitting element; and a second switching transistor includes a first electrode connected to an anode electrode of the first light-emitting element, a gate electrode to which a second control signal is applied, and a second electrode connected to a cathode electrode of the first light-emitting element, wherein the first light-emitting element and the second light-emitting element are connected in series between a power line to which a pixel driving voltage is applied and the first node.

12. The pixel circuit as claimed in claim 11 further comprises: a first capacitor connected between the second node and a fourth node; and a second capacitor connected between the first node and the second node; and the switching transistors further comprise: A third switching transistor includes a first electrode connected to the third node, a gate electrode to which a light emission signal is applied, and a second electrode to which a ground voltage is applied; a fourth switching transistor includes a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to the fourth node; a fifth switching transistor includes a first electrode connected to the second node, a gate electrode to which the first scan signal is applied, and a second electrode connected to the third node; a sixth switching transistor includes a first electrode connected to the fourth node, a gate electrode to which a light emission signal is applied, and a gate electrode to which a ground voltage is applied. A seventh switching transistor includes a gate electrode for receiving the light emission signal and a second electrode for receiving a reference voltage; a seventh switching transistor includes a first electrode connected to the second node, a gate electrode for receiving a second scan signal, and a second electrode for receiving the reference voltage; an eighth switching transistor includes a first electrode connected to the data line, a gate electrode for receiving the second scan signal, and a second electrode connected to the fourth node; and a ninth switching transistor includes a first electrode for receiving a pixel driving voltage, a gate electrode for receiving the first scan signal, and a second electrode connected to the first node.

13. The pixel circuit as described in any of claims 5, 6, 10, and 12, wherein: A frame cycle includes a first cycle, a second cycle following the first cycle, a third cycle following the second cycle, and a fourth cycle following the third cycle; during the first cycle, the voltage of the second scan signal is a gate-on voltage, and the voltage of the first scan signal and the voltage of the light-emitting signal are gate-off voltages; during the second cycle, the voltage of the first scan signal is the gate-on voltage, and the voltage of the second scan signal and the voltage of the light-emitting signal are the gate-off voltages; during the third cycle, the voltage of the first scan signal, the voltage of the second scan signal, and the voltage of the light-emitting signal are the gate-off voltages; during the fourth cycle, the voltage of the light-emitting signal is the gate-on voltage, and the voltage of the first scan signal and the voltage of the second scan signal are the gate-off voltages; and each of the switching transistors is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage.

14. The pixel circuit as claimed in claim 4 further comprises: a first switching transistor including a first electrode connected to the third node, a gate electrode to which a first control signal is applied, and a second electrode connected to an anode electrode of the first light-emitting element; a second switching transistor including a first electrode connected to the third node, a gate electrode to which a second control signal is applied, and a second electrode connected to an anode electrode of the second light-emitting element; a third switching transistor including a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to the second node; and a fourth switching transistor including a first electrode connected to the third node, a gate electrode to which a second control signal is applied, and a second electrode connected to a sensing line, wherein the first light-emitting element includes an anode electrode connected to the second electrode of the first switching transistor and a cathode electrode to which a ground voltage is applied, and wherein the second light-emitting element includes an anode electrode connected to the second electrode of the second switching transistor and a cathode electrode to which the ground voltage is applied.

15. The pixel circuit as claimed in claim 4 further comprises: a first switching transistor, including a first electrode connected to an anode electrode of the second light-emitting element, a gate electrode to which a first control signal is applied, and a second electrode connected to a cathode electrode of the second light-emitting element; a second switching transistor, including a first electrode connected to an anode electrode of the first light-emitting element, a gate electrode to which a second control signal is applied, and a second electrode connected to a cathode electrode of the first light-emitting element; a third switching transistor, including a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to the second node; and a fourth switching transistor, including a first electrode connected to the third node, a gate electrode to which a second scan signal is applied, and a second electrode connected to a sensing line, wherein the first light-emitting element includes an anode electrode connected to the third node and a cathode electrode connected to the fourth node, and wherein the second light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to a power line to which a ground voltage is applied.

16. The pixel circuit as described in any one of claims 2, 3, 5 to 12, 14 and 15, wherein the voltage of the first control signal and the voltage of the second control signal alternately reverse periodically for one of N (N is a natural number) frame periods, or alternately reverse during one emission period within one frame period.

17. The pixel circuit as described in any one of claims 2, 3, 5 to 12, 14 and 15, wherein the voltage of the first control signal and the voltage of the second control signal alternately reverse periodically over one frame period.

18. A display device comprising: a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits arranged thereon; a data driving circuit connected to the data lines; and a gate driving circuit connected to the gate lines, wherein each of the pixel circuits comprises: a single driving transistor configured to generate a current; and a first light-emitting element and a second light-emitting element electrically connected in parallel or in series to a common terminal of the single driving transistor, and wherein the first light-emitting element and the second light-emitting element are alternately driven by the current from the single driving transistor.

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