Semiconductor device and methods of formation

Abstract

During the nanosheet release process, the nanostructure channels of a nanostructured transistor are etched to remove sacrificial nanostructure layers between the nanostructure channels. The etching of the nanostructure channels is controlled to improve the efficiency of the etching process, thereby removing impurities from the central portion of the nanostructure channels. More specifically, parameters such as etching temperature and / or pressure are controlled to counteract high energy barriers and increase etchant adsorption. Therefore, the uniformity of material removal rate on the nanostructure channels during the etching process is improved, resulting in nanostructure channels with a substantially uniform surface profile. The techniques described herein can reduce the channel resistance of nanostructured transistors, thereby improving their performance.

Description

Technical Field

[0001] none Prior Technology

[0002] With advancements in semiconductor device manufacturing and the shrinking of technology processing node sizes, transistors may be affected by the short-channel effect (SCE), such as hot carrier degradation, barrier reduction, and quantum confinement. Furthermore, as the gate length of transistors decreases to accommodate smaller technology nodes, source / drain (S / D) electron tunneling increases, which raises the transistor's cutoff current (the current flowing through the transistor channel when the transistor is in the cutoff configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors (such as nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates to overcome the short-channel effect at smaller technology nodes. Nanostructure transistors offer a high-efficiency structure that experiences reduced short-channel effects and enhanced carrier mobility compared to other types of transistors. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various features disclosed herein can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figures 1A to 1C are schematic diagrams illustrating exemplary implementations of the fin boundary customization process described herein. Figure 2 is a schematic diagram of the exemplary dummy gate structure formation process described in this article. Figure 3 is a schematic diagram illustrating an exemplary implementation of the source / drain groove formation process described herein. Figures 4A and 4B are schematic diagrams illustrating exemplary implementations of the internal spacer formation process described herein. Figure 5 is a schematic diagram illustrating an exemplary implementation of the source / drain region formation process described in this paper. Figure 6 is a schematic diagram illustrating an exemplary implementation of the interlayer dielectric layer formation process described herein. Figures 7A to 7C are schematic diagrams illustrating exemplary implementations of the nanosheet release process described herein. Figures 8A and 8B are schematic diagrams illustrating exemplary implementations of the gate formation process described herein. Figure 9 is a schematic diagram of an embodiment of the semiconductor device described herein. Figure 10 is a flowchart of an exemplary process related to forming the semiconductor structure described herein. Implementation

[0005] The following disclosure provides numerous different embodiments or implementations for achieving various features of the provided object. Specific embodiments of components and arrangements are described below to simplify this disclosure. Of course, these are merely embodiments and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] Some nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors) include an internal spacer between the source / drain regions and the gate structure. This internal spacer provides various process and / or performance advantages, such as electrical isolation between the source / drain regions and the gate structure, and / or protection of the source / drain regions from etching during gate replacement operations to replace the sacrificial nanostructure layer with the gate structure.

[0008] However, the process of removing sacrificial nanostructure layers between nanostructure channels to create vacancies for the gate structure can be challenging and may result in high impurity content within the nanostructure channels. For example, due to the high energy barrier that needs to be overcome during etching, impurities may remain in parts of the nanostructure channels after the sacrificial nanostructure layers are removed. Impurities in the nanostructure channels can trap electrons, leading to an unnecessarily increased channel resistance and thus degrading the performance of the nanostructure transistor.

[0009] In some embodiments described herein, the nanostructure channels of a nanostructured transistor are etched during a nanosheet release process to remove sacrificial nanostructure layers between the nanostructure channels. The etching of the nanostructure channels is controlled to improve the efficiency of the etching process, thereby removing impurities from the central portion of the nanostructure channels. More specifically, parameters such as etching temperature and / or pressure are controlled to counteract high energy barriers and increase etchant adsorption. Therefore, the uniformity of material removal rate on the nanostructure channels during the etching process is improved, resulting in nanostructure channels with a substantially uniform surface profile. The techniques described herein can reduce the channel resistance of the nanostructured transistor, thereby improving its performance.

[0010] Figures 1A through 1C are schematic diagrams of an exemplary embodiment 100 of the fin-bound process described herein. Exemplary embodiment 100 includes embodiments of forming fin-shaped structures and associated shallow trench isolation (STI) regions for a semiconductor device 105 described herein. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors. Exemplary embodiment 100 includes embodiments of forming fin-shaped structures and associated STI regions for the transistors of the semiconductor device 105.

[0011] Figures 1A through 1C illustrate perspective views of the semiconductor device 105 and cross-sectional views along section AA in the perspective views, respectively. As shown in Figure 1A, the processing of the semiconductor device 105 is performed together with the semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0012] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes vertically alternating layers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 located above the semiconductor substrate 110. The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown in Figure 1A is an example, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of this disclosure.

[0013] The sacrificial nanostructure layer 120 enables the definition of vertical distances between adjacent nanostructure channels formed by the nanostructure channel layer 125 and serves as a berthing layer for the subsequently formed gate structure of the transistor of the semiconductor device 105, these berthing layers being formed around the nanostructure channels. The sacrificial nanostructure layer 120 includes a first material composition, and the nanostructure channel layer 125 includes a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the sacrificial nanostructure layer 120 may include silicon germanium (SiGe), and the nanostructure channel layer 125 may include silicon (Si). This enables the selective etching of the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 depending on the type of etchant used (e.g., the sacrificial nanostructure layer 120 can be etched without etching the nanostructure channel layer 125, and the nanostructure channel layer 125 can be etched without etching the sacrificial nanostructure layer 120).

[0014] One or more types of deposition tools can be used to deposit and / or grow alternating layers of the stack 115 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 110. For example, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be grown by epitaxial growth using deposition tools, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0015] As shown in a close-up view of a portion of layer stack 115 in Figure 1A, mixing may occur between two or more nanostructure layers in layer stack 115. For example, mixing may occur between sacrificial nanostructure layer 120 and a vertically adjacent nanostructure channel layer 125. Mixing can result in the diffusion of silicon (Si) and / or germanium (Ge) between sacrificial nanostructure layer 120 and nanostructure channel layer 125. In some cases, mixing layer 130 is a portion of nanostructure channel layer 125 near the interface between nanostructure channel layer 125 and sacrificial nanostructure layer 120, which contains impurities in the form of diffused germanium (Ge) from sacrificial nanostructure layer 120. Therefore, mixing layer 130 may include silicon (Si) regions where germanium (Ge) has diffused.

[0016] One or more mask layers may be formed on the layer stack 115 (e.g., using one or more deposition tools). The mask layers may include a hard mask (HM) layer 135, a capping layer 140, an oxide layer 145, and / or a nitride layer 150. The mask layers may be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0017] As shown in Figure 1B, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 155 extending over the semiconductor substrate 110. The fin structure 155 may extend in the semiconductor device 105 along the x-direction and may be aligned in the semiconductor device 105 along the y-direction. The fin structure 155 includes a portion 160 of the layer stack 115 located directly above and / or on the fin portion 165 above the semiconductor substrate 110. The fin structure 155 may be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on the patterns formed in the one or more masking layers. One or more masking layers may be patterned using lithography techniques (including dual patterning techniques or multiple patterning techniques). The semiconductor substrate 110 may be etched using an etching tool based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0018] As further shown in Figure 1B, some fin structures 155 can be formed with different widths for different types of nanostructure transistors. For example, a first subset of fin structures 155a can be formed for p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset of fin structures 155b can be formed for n-type nanostructure transistors (e.g., n-type nanostructure transistor (NMOS) nanostructure transistors). As another example, the first subset of fin structures 155a can be formed for nanostructure transistors operating at lower voltages, and the second subset of fin structures 155b can be formed for nanostructure transistors operating at higher voltages.

[0019] As shown in Figure 1C, a pad 170 and an STI region 175 are formed between adjacent fin portions 165 of the fin structure 155. The pad 170 and the STI region 175 may each include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluorosilicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials.

[0020] A deposition tool can be used (e.g., using ALD or another conformal deposition technique) to conformally deposit the liner 170, and a dielectric layer can be deposited on the liner 170 (e.g., using CVD, PVD, ALD, and / or another suitable deposition technique) such that the dielectric layer completely fills the space between the fin structures 155 and extends above the top of the fin structures 155. A planarization or polishing operation (e.g., chemical mechanical planarization, CMP) can then be performed using a planarization tool to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of the nitride layer 150. The nitride layer 150 serves as a CMP termination layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form the STI region 175 such that the top surface of the STI region 175 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0021] As described above, Figures 1A through 1C are provided as embodiments. Other embodiments may differ from those described with respect to Figures 1A through 1C.

[0022] Figure 2 is a schematic diagram of an exemplary embodiment 200 of the dummy gate formation process described herein. Exemplary embodiment 200 includes an embodiment of a dummy gate structure 205 forming a nanostructure transistor of a semiconductor device 105. In some embodiments, the operations described in connection with exemplary embodiment 200 are performed after the processes described in connection with Figures 1A to 1C.

[0023] Figure 2 illustrates a perspective view of a semiconductor device 105, on which a dummy gate structure 205 is formed. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed above a portion of the fin structure 155 and a portion of the STI region 175. The dummy gate structure 205 extends in the x-direction and is aligned in the y-direction such that it is approximately perpendicular to the fin structure 155. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in subsequent processing stages of the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess, wherein the source / drain regions of the nanostructured transistor are formed in the fin structure 155.

[0024] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 located above and / or on the gate electrode layer 210, a spacer layer 220 located on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 located below the gate electrode layer 210. The gate electrode layer 210 includes polycrystalline silicon (polycrystalline silicon or PO) or other materials. The hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer of silicon dioxide (SiO2) or other materials) and a nitride layer formed above the oxide layer (e.g., a pad nitride layer of silicon nitride such as Si3N4 or other materials). The spacer layer 220 includes silicon carbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiOx, such as SiO2), silicon nitride (e.g., SixNy, such as Si3N4), high dielectric constant (high k) dielectric material (e.g., dielectric material with a dielectric constant greater than about 3.9) and / or other suitable materials.

[0025] The layer of the dummy gate structure 205 can be formed using various semiconductor processing techniques, such as depositing the layer of the dummy gate structure 205, patterning the layer of the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor processing techniques.

[0026] Figure 2 further illustrates the reference sections used in the subsequent figures described herein. Section AA lies in the xz plane (referred to as the y-cut) and spans the fin structure 155 in the source / drain region of the semiconductor device 105. Section BB lies in the yz plane perpendicular to section AA (referred to as the x-cut) and spans the dummy gate structure 205 along the underlying fin structure 155. Section CC lies in the xz plane parallel to section AA and perpendicular to section BB, and along the dummy gate structure 205. For clarity, these reference sections will be referenced in subsequent figures. In some figures, for ease of depiction, component symbols for some components or features may be omitted to avoid obscuring other components or features.

[0027] As described above, Figure 2 is provided as an embodiment. Other embodiments may differ from those described with respect to Figure 2.

[0028] Figure 3 is a schematic diagram of an exemplary embodiment 300 of the source / drain trench formation process described herein. Exemplary embodiment 300 includes an embodiment of a source / drain trench 305 forming source / drain regions for a nanostructured transistor in a semiconductor device 105. Figure 3 is illustrated from multiple perspectives shown in Figure 2, including the perspective of section AA and section BB in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 300 are performed after the processes described in conjunction with Figures 1A through 2.

[0029] As shown in sections AA and BB of Figure 3, the source / drain groove 305 is formed through portion 160 of the fin structure 155 during the etching operation. The source / drain groove 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using etching tools and may be referred to as a strained source / drain (SSD) etching operation. In some implementations, the etching operation includes the use of plasma etching technology, wet chemical etching technology, and / or another type of etching technology.

[0030] The source / drain grooves 305 also extend into a portion of the fin portion 165 of the fin structure 155. This results in the formation of a mesa region 310 in the fin structure 155. The sidewall of the portion of each source / drain groove 305 located below the layer stack 115 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as the base) refers to the region of the fin portion 165 of the fin structure 155 in which a nanostructure channel is defined from the nanostructure channel layer 125. The nanostructure channel 315 extends between adjacent source / drain grooves 305 and is located below the dummy gate structure 205 between adjacent source / drain grooves 305.

[0031] The nanostructure channel 315 includes a silicon-based nanostructure (e.g., a nanosheet or nanowire) and serves as a semiconductor channel for the nanostructure transistor of the semiconductor device 105. In some embodiments, the nanostructure channel 315 may include silicon germanium (SiGe) or another silicon-based material. The nanostructure channel 315 is arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructure channel 315 is vertically aligned or stacked above the semiconductor substrate 110.

[0032] As described above, Figure 3 is provided as an example. Other embodiments may differ from those described with reference to Figure 3.

[0033] Figures 4A and 4B are schematic diagrams of an exemplary embodiment 400 of the internal spacer formation process described herein. Exemplary embodiment 400 includes an example of forming internal spacers between the ends of nanostructured channels 315 exposed in source / drain recesses 305. Figures 4A and 4B are illustrated from the viewpoint of section BB in Figure 2, respectively. In some embodiments, the operations described in conjunction with exemplary embodiment 400 are performed after the processes described in conjunction with Figures 1A through 3.

[0034] As shown in section BB of Figure 4A, in one or more first etch operations, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain grooves 305 are etched laterally (e.g., in the x-direction approximately parallel to the length of the sacrificial nanostructure layer 120) to form cavities 405 between the ends of the sacrificial nanostructure layer 120 exposed in the source / drain grooves 305. Specifically, the ends of the sacrificial nanostructure layer 120 located below the dummy gate structure 205 can be etched laterally via the source / drain grooves 305 using an etching tool to form cavities 405 between the ends of the nanostructure channels 315.

[0035] In embodiments where the sacrificial nanostructure layer 120 is silicon-germanium (SiGe) and the nanostructure channel 315 is silicon (Si), the sacrificial nanostructure layer 120 is etched in one or more first etch operations using a wet etchant (such as a mixed solution including hydrogen peroxide (H2O2), acetic acid (CH3COOH), and / or hydrogen fluoride (HF)), followed by rinsing with water (H2O). The mixed solution and water can be provided to the source / drain recess 305 to etch the sacrificial nanostructure layer 120 in the source / drain recess 305. In some embodiments, the mixed solution etching and water rinsing are repeatedly cyclically used to form the cavity 405.

[0036] As shown in Figure 4B, an inner spacer 410 is formed in the cavity 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The inner spacer 410 serves to reduce parasitic capacitance in the nanostructure transistor and prevent the source / drain regions (subsequently formed in the source / drain recess 305) from being etched during a nanosheet release operation to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The inner spacer 410 includes silicon nitride (SixNy), silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbide (SiOCN), and / or other dielectric materials.

[0037] To form the inner spacer 410, a dielectric material layer can be deposited in the cavity 405 along the sidewalls and bottom surface of the source / drain recesses using a deposition tool. CVD, PVD, ALD, and / or another deposition technique can be used to deposit the dielectric material layer. Excess material of the dielectric material layer is then removed from the source / drain recesses using an etching tool, leaving the remaining portion corresponding to the inner spacer 410 in the cavity 405. In some embodiments, the etching operation may cause the surface of the inner spacer 410 facing the source / drain recesses 305 to bend or recess. In some embodiments, the surface of the inner spacer 410 facing the source / drain recesses 305 is approximately flat, such that the surface of the inner spacer 410 and the surface of the end of the nanostructure channel 315 are approximately flat and flush.

[0038] As described above, Figures 4A and 4B are provided as embodiments. Other embodiments may differ from those described with respect to Figures 4A and 4B.

[0039] Figure 5 is a schematic diagram of an exemplary embodiment 500 of the source / drain region formation process described herein. Exemplary embodiment 500 includes an embodiment for forming the source / drain regions of a nanostructured transistor of a semiconductor device 105. Figure 5 is illustrated from multiple perspectives shown in Figure 2, including the perspective of section AA and section BB in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 500 are performed after the processes described in conjunction with Figures 1A through 4B.

[0040] As shown in cross-sections AA and BB in Figure 5, the source / drain groove 305 is filled with one or more layers of material to form a source / drain region within the source / drain groove 305. For example, a deposition tool can be used to deposit a buffer region 505 at the bottom of the source / drain groove 305, and the deposition tool can deposit a source / drain region 510 on the buffer region 505 in the source / drain groove 305. In some embodiments, a deposition tool can be used to deposit a capping layer 515 on the source / drain region 510 in the source / drain groove 305.

[0041] Buffer region 505 may include silicon (Si), boron-doped silicon (Si:B), or other dopants and / or other materials. Buffer region 505 may be located between source / drain region 510 and mesa region 310, which is adjacent to buffer region 505, to reduce, minimize, and / or prevent dopant migration and / or current leakage from source / drain region 510 to adjacent mesa region 310, which could otherwise lead to short-channel effects in semiconductor device 105. Therefore, buffer region 505 can improve the performance and / or yield of semiconductor device 105.

[0042] Depending on the context, "source / drain region" may refer to either the source or the drain individually, or collectively. The source / drain region 510 may be located on opposite sides of the dummy gate structure 205, such that the nanostructure channel 315 beneath the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510. Each source / drain region 510 includes silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge), etc.), n-type materials (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Therefore, the semiconductor device 105 may include a p-type metal-oxide semiconductor (PMOS) nanostructure transistor (including a p-type source / drain region 510), an n-type metal-oxide semiconductor (NMOS) nanostructure transistor (including an n-type source / drain region 510), and / or other types of nanostructure transistors.

[0043] One or more layers of the source / drain region 510 may be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool may epitaxially grow a first layer (referred to as L1) of the source / drain region 510 over a relevant buffer region 505 (referred to as L0), and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 510 over the first layer. The first layer may include lightly doped silicon (e.g., boron (B), phosphorus (P), and / or another dopant) and may serve as a shielding layer to reduce short-channel effects in the semiconductor device 105 and reduce dopant extrusion or migration to the nanostructure channel 315. The second layer may include heavily doped silicon or heavily doped silicon-germanium. A second layer may be included to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0044] The capping layer 515 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or other materials. Prior to contact formation, during semiconductor processing operations of the semiconductor device 105, the capping layer 515 may be included to reduce dopant diffusion and protect the underlying source / drain regions 510. Furthermore, the capping layer 515 may facilitate the formation of metal-semiconductor (e.g., silicate) alloys.

[0045] As described above, Figure 5 is provided as an example. Other embodiments may differ from those described with reference to Figure 5.

[0046] Figure 6 is a schematic diagram of an exemplary embodiment 600 of the interlayer dielectric (ILD) formation process described herein. Figure 6 is illustrated from multiple perspectives shown in Figure 2, including the perspective of section AA and section BB in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 600 are performed after the processes described in conjunction with Figures 1A through 5.

[0047] As shown in cross-sections AA and BB in Figure 6, a dielectric layer 605 is formed above the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damage to the source / drain region 510 during the gate replacement process and / or to prevent damage to the source / drain region 510 to replace the dummy gate structure 205. The dielectric layer 605 may be referred to as an ILD0 layer or another ILD layer.

[0048] In some implementations, a contact etch stop layer (CESL) is conformally deposited over the source / drain region 510 (e.g., using a deposition tool) prior to the formation of the dielectric layer 605. Alternatively, the capping layer 515 may be a CESL. The dielectric layer 605 is then formed on the CESL. The CESL provides a mechanism to terminate the etching process when forming contacts or vias in the source / drain region 510. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or components. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may include or may be silicon nitride (SixNy), silicon carbonitride (SiCN), carbonitride (CN), silicon oxynitride (SiON), silicon carbide (SiCO), or combinations thereof, etc. The CESL may be deposited using deposition processes such as ALD, CVD, or other deposition techniques.

[0049] As described above, Figure 6 is provided as an example. Other embodiments may differ from those described with reference to Figure 6.

[0050] Figures 7A through 7C are schematic diagrams of an exemplary embodiment 700 of the nanosheet release process described herein. The nanosheet release process (e.g., a silicon-germanium (SiGe) release process) is a process for removing the remainder of the sacrificial nanostructure layer 120 from between the nanostructure channels 315 of the semiconductor device 105. The nanosheet release process may be performed as part of a replacement gate (RPG) process, which replaces the dummy gate structure 205 with a high-k / metal gate structure (e.g., a replacement gate structure) of the nanostructure transistor of the semiconductor device 105. Figures 7A through 7C are illustrated from the viewpoint of section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the operations described in conjunction with Figures 1A through 6.

[0051] Figure 7A illustrates another configuration of the semiconductor device 105, different from the configuration shown in Figure 6. Figure 7A illustrates a first spacer layer 220a and a second spacer layer 220b located on opposite sides of the dielectric layer 605, instead of spacer layer 220. Like spacer layer 220, the first spacer layer 220a and the second spacer layer 220b comprise silicon carbide (SiOC), nitrogen-free SiOC, or other suitable materials. The first spacer layer 220a and the second spacer layer 220b may comprise the same or different materials. In some embodiments, the second spacer layer 220b is a spacer pad, while the first spacer layer 220a is a bulk spacer.

[0052] A dummy gate removal operation can be performed prior to the nanosheet removal process. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removing the dummy gate structure 205 leaves an opening (or groove) between the dielectric layers 605 and provides a channel for the nanosheet removal process to access the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 can be removed in one or more etching operations. Such etching operations may include plasma etching, wet chemical etching, and / or another type of etching technique.

[0053] The nanosheet release process may include performing an etching operation to laterally etch the sacrificial nanostructure layer 120, thereby removing the sacrificial nanostructure layer 120 from between vertically adjacent nanostructure channels 315. The etching operation further etches exposed portions of the vertically adjacent nanostructure channels 315 to create nanostructure channels 315 with a substantially uniform surface profile. As described above and explained in more detail below, parameters such as temperature and / or pressure are controlled during the etching operation to counteract high energy barriers and increase etchant adsorption at the central portion of the nanostructure channel 315. The central portion of the nanostructure channel 315 is defined relative to the x-direction (e.g., along the length of the nanostructure channel 315 between opposing first source / drain regions 510a and second source / drain regions 510b). Therefore, during the etching process, the uniformity of material removal rate on the nanostructure channel 315 (e.g., along the length of the nanostructure channel 315, between adjacent sets of adjacent inner spacers 410 in the first source / drain region 510a and the second source / drain region 510b) is improved, thereby forming a nanostructure channel 315 with a substantially uniform surface profile along the x-direction. Furthermore, the increased uniformity of material removal rate increases the likelihood of complete removal of impurities (e.g., germanium (Ge) impurities) from the top and bottom surfaces of the nanostructure channel 315, thereby improving the performance of the nanostructure channel 315 by reducing its resistance.

[0054] As shown in Figure 7A, each of the nanostructure channels 315 may have dimensions D1 and D2. Dimension D1 corresponds to the z-direction (vertical) cross-sectional thickness at the center of the nanostructure channel 315 (e.g., at the center of the x-direction length of the nanostructure channel 315), and dimension D2 corresponds to the z-direction (vertical) cross-sectional thickness at the ends (e.g., the outer portion) of the nanostructure channel 315 (e.g., at the ends of the x-direction length of the nanostructure channel 315, adjacent to the opposing source / drain regions 510a and 510b). Before the nanosheet release process, the z-direction thickness at the center of the nanostructure channel 315 and the z-direction thickness at the ends of the nanostructure channel 315 are approximately equal (e.g., dimension D1 ≈ dimension D2). After the nanosheet release process, the z-direction thickness at the center of the nanostructure channel 315 is less than the z-direction thickness at the ends of the nanostructure channel 315 (e.g., dimension D1 < dimension D2).

[0055] Referring to Figure 7B, and illustrating the outline 705 in Figure 7A, the etching operation of the nanosheet release process includes providing an etchant 710 around the exposed portions of the sacrificial nanostructure layer 120 and the nanostructure channel 315. The etchant 710 is used to etch the sacrificial nanostructure layer 120 to remove it and to trim or remove impurities from the nanostructure channel 315 (e.g., possibly corresponding to germanium (Ge) impurities in the mixed layer 130 formed between the sacrificial nanostructure layer 120 and the nanostructure channel layer 125). The semiconductor device 105 may be placed in the processing chamber of the etching tool, and the etchant 710 may be provided to the processing chamber as a mixture of process gases that react with each other and / or with the materials of the sacrificial nanostructure layer 120 and the nanostructure channel 315 to etch the sacrificial nanostructure layer 120 and the nanostructure channel 315.

[0056] During the etching operation, the temperature and pressure within the processing chamber are controlled to overcome high energy barriers (e.g., for material removal from the self-sacrificing nanostructure layer 120 and nanostructure channel 315), which could otherwise make it difficult or impossible to remove germanium (Ge) impurities from the central portion of the nanostructure channel 315. For example, in some embodiments, the temperature within the processing chamber may be maintained in the range of about 20 degrees Celsius to about 60 degrees Celsius, and the pressure within the processing chamber may be in the range of about 0.2 Torr to about 2 Torr. Although other ranges and values ​​are also within the scope of this disclosure, temperatures within the aforementioned ranges increase the adsorption of etchant gas on the central surface of the nanostructure channel 315. Pressures within the aforementioned ranges increase the viscosity of the etchant gas, making it more difficult for the gas to diffuse from the central surface to the ends of the nanostructure channel 315 in contact with the inner spacer 410. The increased viscosity of the etchant gas increases the interaction between etchant gas molecules, making it easier for the etchant gas to adsorb in the central portion of the nanostructure channel 315 than at the ends of the nanostructure channel 315 in contact with the inner spacer 410.

[0057] It should be noted that excessively high etching temperatures can damage the nanostructure channel 315, while excessively low etching temperatures will result in an excessively low etching rate for silicon germanium (SiGe) (which can be the material for sacrificial nanostructure layer 120), thereby reducing productivity. Excessively high etching pressure will lead to an excessively high etching rate for SiGe, making it difficult to control the stability of the etching operation, while excessively low etching pressure will lead to an excessively low etching rate for SiGe, thereby reducing productivity.

[0058] The etchant 710 may include a gas-based etchant, comprising a combination of a fluorine-based etchant (e.g., F2 gas) and a hydrofluoric acid etchant (e.g., HF gas). During the etching operation, other gases (such as purging gases, carrier gases, and / or other reactive gases) may also be supplied to the processing chamber. Such gases may include argon (Ar) gas, ammonia (NH3) gas, chlorine trifluoride (ClF3) gas, and / or nitrogen (N2) gas, and other embodiments. In some embodiments, during the etching operation, the flow rate of F2 gas entering the processing chamber may be in the range of about 20 standard cubic centimeters per minute (sccm) to about 250 sccm, and the flow rate of HF gas entering the processing chamber may be in the range of about 6 sccm to about 110 sccm. Furthermore, during the etching operation, the ratio of fluorine-based etchant (e.g., F2 gas) to hydrofluoric acid etchant (e.g., HF gas) in the processing chamber may be in the range of about 10:1 to about 1:10. However, other values ​​and / or ranges of gas flow rate and gas-to-gas ratio during etching operations are within the scope of this disclosure.

[0059] It should be noted that excessively high flow rates of fluorine-based etchants (e.g., F2 gas) can lead to excessively high etching rates of silicon germanium (SiGe) (which can be the material for sacrificial nanostructure layer 120), making it difficult to control the stability of the etching operation. Conversely, excessively low flow rates of fluorine-based etchants can lead to excessively low etching rates of SiGe, thereby reducing productivity. Excessively high flow rates of hydrofluoric acid etchants (e.g., HF gas) can cause selectivity problems, resulting in unnecessary dielectric layer etching, while excessively low flow rates of hydrofluoric acid etchants can lead to uneven etching of SiGe.

[0060] Etching agent 710 can laterally etch the sacrificial nanostructure layer 120 during an etching operation, starting from the outer edge of the sacrificial nanostructure layer 120 and etching towards the center of the sacrificial nanostructure layer 120 until the sacrificial nanostructure layer 120 is completely removed (or substantially completely removed). Etching agent 710 also etches exposed portions of the nanostructure channel 315 to remove impurities (e.g., germanium (Ge)) from the nanostructure channel 315, as described herein. Referring to Figure 1A, in some embodiments, etching agent 710 removes a mixing layer 130 (if present), which may include at least some impurities. In some embodiments, the etching operation lasts from about 20 seconds to about 150 seconds to ensure complete removal of portions of the sacrificial nanostructure layer 120, the mixing layer 130, and the nanostructure channel 315 including unwanted impurities without causing over-etching of the nanostructure channel 315. However, other ranges and values ​​are also within the scope of this disclosure.

[0061] Etching agent 710 can be used to etch portions of the sacrificial nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315 by removing silicon (Si) and / or germanium (Ge). The removal of silicon (Si) from portions of the sacrificial nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315 may be due to a reaction between the fluorine-based etchant (e.g., F2 gas) in etching agent 710 and the silicon-germanium (SiGe) in portions of the sacrificial nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315. As shown by element symbol 715a in Figure 7B, a fluorine-based etchant (e.g., F2 gas) in etchant 710 can adhere to silicon (Si) and germanium (Ge) in portions of the sacrificial nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315 to form GeF3 and SiF3, respectively. Fluorine migration (F-migration) may occur, in which fluorine (F) atoms migrate from GeF3 molecules to SiF3 molecules, thereby forming GeF2 and SiF4 gases. Removal of the SiF4 gas from the semiconductor device 105 removes silicon (Si) from portions of the sacrificial nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315. Fluorine (F) atom migration can occur at energies in the range of about 0.3 electron volts (eV) to about 0.35 eV. However, other values ​​and / or ranges of energy for fluorine (F) atom migration are within the scope of this disclosure. Fluorine (F) atom migration can be an exothermic process, where the enthalpy change (∆H) ranges from about -1.75 eV to about -2.0 eV. However, other values ​​and / or ranges of enthalpy change are within the scope of this disclosure.

[0062] The removal of germanium (Ge) from portions of the self-sacrificing nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315 may be due to the reaction between the combination of the fluorine-based etchant (e.g., F2 gas) and the hydrofluoric acid etchant (e.g., HF gas) in the etchant 710 and the silicon-germanium (SiGe) in portions of the self-sacrificing nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315. As shown by component symbol 715b in Figure 7B, fluorine (F) in a fluorine-based etchant (e.g., F2 gas) and / or a hydrofluoric acid etchant (e.g., HF gas) can adhere to silicon (Si) and germanium (Ge) in portions of the sacrificial nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315. Furthermore, hydrogen in the hydrofluoric acid etchant of etchant 710 can adhere to silicon (Si) and germanium (Ge) in portions of the sacrificial nanostructure layer 120, the mixed layer 130, and the nanostructure channel 315. Fluorine and hydrogen react with germanium to form GeH2F and SiHF2. Hydrogen migration (H migration) may occur, in which hydrogen (H) atoms migrate from SiHF2 molecules to GeH2F molecules, thereby forming GeH3F gas and SiF2. GeH3F gas is removed from the semiconductor device 105, thereby removing germanium (Ge) from the sacrificial nanostructure layer 120 and the mixed layer 130. Hydrogen (H) atom migration can occur at energies ranging from about 0.9 eV to about 1.0 eV. However, other energies and / or ranges for fluorine (F) atom migration are within the scope of this disclosure. Hydrogen (H) atom migration can be an exothermic process, wherein the enthalpy change (∆H) is included in the range of about -0.75 eV to about -0.9 eV. However, other enthalpy changes and / or ranges are also within the scope of this disclosure.

[0063] As shown in Figure 7B, during the etching operation, portions of the nanostructure channel 315 are etched to remove the sacrificial nanostructure layer 120. Removal of material from the top and bottom of the nanostructure channel 315 results in a curved or recessed cross-sectional profile along the length of the nanostructure channel 315 (e.g., along the x-direction). More specifically, each nanostructure channel in the nanostructure channel 315 has an arcuate surface 720 along the x-direction between a first source / drain region 510a on a first side of the nanostructure channel 315 and a second source / drain region 510b on a second side of the nanostructure channel 315. Without using the etching operation techniques described herein for nanosheet release processes, the resulting profile (cross-sectional profile) along the length of the nanostructure channel 315 (e.g., along the x-direction) might be wavy or W-shaped due to some impurities (e.g., germanium (Ge) impurities) remaining at the center of the nanostructure channel 315.

[0064] A plurality of first inner spacers 410a are adjacent to a first source / drain region 510a, and a plurality of second inner spacers 410b are adjacent to a second source / drain region 510b. Each arcuate surface 720 is located between a first inner spacer 410a and a second inner spacer 410b (the second inner spacer 410b is opposite to the first inner spacer 410a) or between two opposite first spacer layers 220a. For example, the arcuate surface 720 of the highest nanostructure channel 315 in the z-direction includes opposite ends that contact two opposite first spacer layers 220a respectively. The arcuate surface 720 of the nanostructure channel 315 below the highest nanostructure channel 315 in the z-direction includes a first edge that contacts the first inner spacer 410a and a second edge that contacts the second inner spacer 410b.

[0065] Each arcuate surface 720 includes a first edge contacting a first inner spacer and a second edge contacting a second inner spacer. As shown in Figure 7B, a given arcuate surface 720 includes a first outer segment 725a, a central segment 725b, and a second outer segment 725c (collectively referred to as "segment 725") located between the first and second inner spacers. Segments 725 are angled relative to each other and arranged in a U-shape. The central segment 725b includes a generally flat profile. Although two outer segments (first and second outer segments 725a and 725c) and a central segment 725b are shown, a number of other segments are also within the scope of this disclosure.

[0066] As shown in Figure 7C, each nanostructure channel 315 may have a size Hmax and a size Hmin. The dimensions of the highest nanostructure channel 315 in the z-direction are referred to as H1max and H1min. The dimensions of the central nanostructure channel 315 are referred to as H2max and H2min. The dimensions of the lowest nanostructure channel 315 in the z-direction are referred to as H3max and H3min. The dimensions H1max, H2max, and H3max are collectively referred to as Hmax. The dimensions H1min, H2min, and H3min are collectively referred to as Hmin. The size Hmax corresponds to the maximum z-direction (vertical) cross-sectional thickness of the central portion of the corresponding nanostructure channel 315 (e.g., the central portion along the x-direction length of the nanostructure channel 315), and the size Hmin corresponds to the minimum z-direction (vertical) cross-sectional thickness of the central portion of the corresponding nanostructure channel 315 (e.g., the central portion along the x-direction length of the nanostructure channel 315). The dimensions Hmin and Hmax can each range from about 3 nanometers to about 8 nanometers.

[0067] In some embodiments, after the nanosheet release process, the difference between Hmax and Hmin for each nanostructure channel 315 (e.g., H1max-H1min, H2max-H2min, and H3max-H3min) is less than or equal to about 0.5 nm, and in some cases less than or equal to about 0.2 nm. In some embodiments, after the nanosheet release process, the difference in the maximum z-direction (vertical) thickness (Hmax) of different nanostructure channels 315 (e.g., H2max-H1max, H3max-H1max, and H3max-H2max) is less than or equal to about 0.5 nm. In some embodiments, after the nanosheet release process, the difference in the minimum z-direction (vertical) thickness (Hmin) of different nanostructure channels 315 (e.g., H2min–H1min, H3min–H1min, and H3min–H2min) is less than or equal to about 0.5 nm. However, other values ​​and ranges of these differences are within the scope of this disclosure.

[0068] As described above, the removal of silicon (Si) from the sacrificial nanostructure layer 120 and the hybrid layer 130 involves the migration of fluorine (F) between molecules formed by silicon (Si) and germanium (Ge) in the sacrificial nanostructure layer 120 and the hybrid layer 130. However, the nanostructure channel 315 may not include germanium (Ge) and may only include silicon (Si). To remove silicon (Si) from the nanostructure channel 315 in the absence of germanium (Ge), an etching operation can be performed at a high temperature to provide sufficient energy to remove silicon (Si) from the nanostructure channel 315 using a fluorine-based etchant (e.g., F2 gas) in the etchant 710.

[0069] For example, the temperature in the processing chamber can be raised to greater than 50 degrees Celsius and up to about 60 degrees Celsius. The etching operation can be performed when the temperature in the processing chamber is within this range to achieve the following reaction between the fluorine-based etchant (e.g., F2 gas) in the etchant 710 and the silicon (Si) in the nanostructure channel 315: The fluorine-based etchant (e.g., F2 gas) in etchant 710 reacts with silicon (Si) in nanostructure channel 315 to form SiF4 gas. The SiF4 gas is removed from semiconductor device 105, resulting in the removal of silicon (Si) from nanostructure channel 315. The reaction can occur at energies in the range of about 1.1 electron volts (eV) to about 1.2 eV. However, other values ​​and / or ranges for the reaction are within the scope of this disclosure.

[0070] As described above, Figures 7A to 7C are provided as embodiments. Other embodiments may differ from those described with respect to Figures 7A to 7C.

[0071] Figures 8A and 8B are schematic diagrams of an exemplary embodiment 800 of the gate formation process described herein. The gate formation process may be performed as part of a replacement gate process, which replaces the dummy gate structure 205 of the nanostructured transistor of the semiconductor device 105 with a gate structure 805 (e.g., a high-k / metal gate structure). Figures 8A and 8B are illustrated from the viewpoint of section BB in Figure 2, respectively. In some embodiments, the operations described in conjunction with exemplary embodiment 800 are performed after one or more operations described in conjunction with Figures 1A through 7C.

[0072] As shown in Figure 8A, the gate structure 805 may include a gate electrode layer 810, one or more work function metal layers 815, and a gate dielectric layer 820 (or the gate dielectric layer 820 may be considered separate from the gate structure 805). The gate dielectric layer 820 of the gate structure 805 may be formed around the nanostructure channel 315. In some embodiments, the gate dielectric layer 820 is also formed on the mesa region 310. The gate dielectric layer 820 may be deposited using deposition tools, employing PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, the gate dielectric layer 820 is a high-k gate dielectric layer, comprising one or more high-k materials (e.g., dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO2, with a dielectric constant of about 3.9). Examples include lanthanum oxide (LaxOy, such as La2O3), hafnium oxide (HfOx, such as HfO2), zirconium oxide (ZrOx, such as ZrO2), and / or aluminum oxide (AlxOy, such as Al2O3). Alternatively and / or silicon dioxide (SiO2) and / or another dielectric material may be used instead of the high-k dielectric material. In some embodiments, the thickness of the gate dielectric layer 820 can range from about 0.5 nanometers to about 3 nanometers. However, other values ​​within this range are also within the scope of this disclosure.

[0073] The gate structure 805 includes a work function metal layer 815 formed on the gate dielectric layer 820 and a gate electrode layer 810 formed on the work function metal layer 815. The work function metal layer 815 can be deposited using deposition tools, employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques.

[0074] A work function metal layer 815 may be included to tune the work function of the gate structure 805. In some embodiments, the gate structure 805 is a p-type gate structure for a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor, and the work function metal layer 815 is a p-type work function metal layer. In these embodiments, the work function metal layer 815 may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals with a work function greater than about 4.7 eV, to tune the work function of the gate structure 805 such that the work function is adjusted to be close to the valence band (EV) of the material of the nanostructure channel 315. In some embodiments, the gate structure 805 is an n-type gate structure for an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor, and the work function metal layer 815 is an n-type work function metal layer. In these implementations, the work function metal layer 815 may include one or more n-type metals, such as titanium aluminum (TiAl) and / or titanium aluminum carbon (TiAlC), to tune the work function of the gate structure 805 so that the work function is close to the conduction band (EC) of the material of the nanostructure channel 315.

[0075] The work function metal layer 815 may be formed such that the work function metal layer 815 surrounds one or more sides of the nanostructure channel 315. In some embodiments, the material of the work function metal layer 815 is deposited between vertically adjacent nanostructure channels 315. In some embodiments, the work function metal layers 815 are merged between vertically adjacent nanostructure channels 315. Alternatively, the work function metal layers 815 are not merged but spaced apart between vertically adjacent nanostructure channels 315, such that the work function metal layer 815 surrounding each nanostructure channel 315 is spaced apart from the work function metal layers surrounding vertically adjacent nanostructure channels 315.

[0076] The gate electrode layer 810 of the gate structure 805 may be formed above the work function metal layer 815. The gate electrode layer 810 may be formed such that it surrounds one or more sides of the nanostructure channel 315. The material of the gate electrode layer 810 may be deposited between vertically adjacent nanostructure channels 315. The gate electrode layer 810 includes one or more conductive metal materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo). The gate electrode layer 810 may be deposited using deposition tools, employing CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The gate electrode layer 810 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the gate electrode layer 810 is deposited on the seed layer. In some embodiments, the gate electrode layer 810 may be planarized using a planarization tool after deposition.

[0077] The curved or concave cross-sectional profile of the nanostructure channel 315 implemented using the nanosheet release technique described in conjunction with Figures 7A to 7C provides a substantially uniform surface profile for the nanostructure channel 315, wherein impurities (e.g., germanium (Ge)) in the central portion of the nanostructure channel 315 have been removed. As described herein, parameters such as temperature and / or pressure are controlled during etching to counteract high energy barriers and increase etchant adsorption. Therefore, the uniformity of material removal rate during the fabrication of the nanostructure channel 315 is improved compared to other etching techniques. The implementation described herein can reduce the channel resistance of the nanostructure transistor, thereby improving the performance of the nanostructure transistor.

[0078] Figure 8B illustrates a close-up view 825 (located as indicated in Figure 8A). As shown in Figure 8B, the side surfaces of the portions of the gate structure 805 adjacent to a corresponding one of the nanostructure channels 315 include gate structure arcuate surfaces 830, which coincide with the arcuate surfaces 720 of the adjacent nanostructure channels 315. Similar to arcuate surface 720, gate structure arcuate surface 830 extends along the length of the gate structure 805 in the x-direction between the first source / drain region 510a and the second source / drain region 510b. Gate structure arcuate surface 830 may be located between the first inner spacer 410a and the second inner spacer 410b (opposite to the first inner spacer 410a), or between two opposing first spacer layers 220a. For example, the uppermost arcuate surface 830 of the gate structure 805 in the z-direction includes opposing ends that contact two opposing first spacer layers 220a, respectively. The portion of the arcuate surface 830 of the gate structure 805 located below the uppermost part of the gate structure 805 in the z-direction includes a first edge contacting a first inner spacer 410a and a second edge contacting a second inner spacer 410b. The gate dielectric layer 820 includes the arcuate surface 830. To conform to the concave profile of the arcuate surface 720, the arcuate surface 830 includes a convex profile.

[0079] As described above, Figures 8A and 8B are provided as embodiments. Other embodiments may differ from those described with reference to Figures 8A and 8B.

[0080] Figure 9 is a schematic diagram of an exemplary embodiment 900 of the semiconductor device 105 described herein, illustrated from the viewpoint of section BB in Figure 2. As shown in Figure 9, the semiconductor device 105 may include a plurality of nanostructure channels 315 (arranged along the z-direction) in the semiconductor device 105. The nanostructure channels 315 extend along the x-direction between a first source / drain region 510a and a second source / drain region 510b. The semiconductor device 105 includes a gate structure 805 surrounding the nanostructure channels 315 and a gate dielectric layer 820 located between the nanostructure channels 315 and the gate structure 805. The gate structure 805 may include a work function metal layer 815 formed on the gate dielectric layer 820 and a gate electrode layer 810 formed on the work function metal layer 815. A first spacer layer 220a is located on the side of the gate structure 805.

[0081] Referring to Figure 9, in some embodiments, the x-direction length (dimension D3) of the nanostructure channel 315 between the first source / drain region 510a and the second source / drain region 510b (e.g., the channel length of the nanostructure channel 315) includes a range of about 10 nanometers to about 30 nanometers. The x-direction length (dimension D4) of the gate structure 805 between the first inner spacer 410a and the second inner spacer 410b (e.g., the Lg of the gate structure) may include a range of about 10 nanometers to about 35 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0082] As shown in Figure 7C, the nanostructure channels 315 may each have dimensions Hmax and Hmin. In Figure 9, dimensions D6 and D5 correspond to dimensions Hmax and Hmin, respectively. Dimension D6 corresponds to the maximum z-direction (vertical) thickness at the central portion of the nanostructure channel 315 (e.g., the central portion along the x-direction length (dimension D4) of the nanostructure channel 315), and dimension D5 corresponds to the minimum z-direction (vertical) thickness at the central portion of the nanostructure channel 315 (e.g., the central portion along the x-direction length (dimension D4) of the nanostructure channel 315). Dimensions D5 and D6 may each range from about 3 nanometers to about 8 nanometers. As used herein, "central portion" refers to a subset of the x-direction length (dimension D4) corresponding to the x-direction length of the central segment 725b of the arcuate surface 720. As described herein, due to the pressure and temperature parameters used in the nanosheet release process, impurities (e.g., germanium (Ge)) are removed from the central portion, resulting in a generally flat (or slightly curved) profile for the central segment 725b of the arcuate surface 720. Therefore, the difference between dimension D6 and dimension D5 is relatively small. For example, in some embodiments, after the nanosheet release process, the difference between dimension D6 and dimension D5 (e.g., dimension D6 - dimension D5) for each nanostructure channel 315 is less than or equal to about 0.5 nanometers, and in some cases less than or equal to about 0.2 nanometers. In some embodiments, for a relatively short x-direction length (dimension D3) of the nanostructure channel 315, the difference between dimension D6 and dimension D5 may be smaller than for a relatively large x-direction length (dimension D3) of the nanostructure channel 315.

[0083] As described above, Figure 9 is provided as an example. Other embodiments may differ from the embodiment described with reference to Figure 9.

[0084] Figure 10 is a flowchart of an exemplary process 1000 related to the formation of a semiconductor structure. In some implementations, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 10.

[0085] As shown in Figure 10, process 1000 may include the following steps: forming a plurality of nanostructured semiconductor layers and a plurality of nanostructured sacrificial layers, such that the nanostructured semiconductor layers and nanostructured sacrificial layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device (block 1010). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructured semiconductor layers (e.g., nanostructured channel layer 125) and a plurality of nanostructured sacrificial layers (e.g., sacrificial nanostructured layer 120), such that the nanostructured semiconductor layers and nanostructured sacrificial layers are arranged alternately in a direction (e.g., z-direction) approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0086] As further shown in Figure 10, process 1000 may include the following steps: performing a first etch operation to etch a nanostructure semiconductor layer and a nanostructure sacrificial layer to define a plurality of nanostructure channels arranged in a direction approximately perpendicular to the semiconductor substrate (block 1020). For example, one or more semiconductor processing tools may be used to perform the first etch operation to etch the nanostructure semiconductor layer and the nanostructure sacrificial layer to define a plurality of nanostructure channels (e.g., nanostructure channel 315) arranged in a direction approximately perpendicular to the semiconductor substrate, as described herein. In some embodiments, the nanostructure channels and the nanostructure sacrificial layer are arranged alternately in a direction approximately perpendicular to the semiconductor substrate.

[0087] As further shown in Figure 10, process 1000 may include the following step: performing a second etch operation to etch the ends (block 1030) of the nanostructure sacrificial layer. For example, one or more semiconductor processing tools may be used to perform the second etch operation to etch the ends of the nanostructure sacrificial layer, as described herein.

[0088] As further shown in Figure 10, process 1000 may include the step of forming a plurality of inner spacers (block 1040) near the etched end of the nanostructure sacrificial layer. For example, one or more semiconductor processing tools may be used to form a plurality of inner spacers (e.g., first inner spacer 410a and second inner spacer 410b) near the etched end of the nanostructure sacrificial layer, as described herein.

[0089] As further shown in Figure 10, process 1000 may include the following steps: performing a third etch operation to remove the nanostructure sacrificial layer from the semiconductor device (block 1050). For example, one or more semiconductor processing tools may be used to perform the third etch operation to remove the nanostructure sacrificial layer from the semiconductor device, as described herein. In some embodiments, the third etch operation results in the surface of each nanostructure channel having a curved concave shape that extends between a first inner spacer (e.g., inner spacer 410a) and a second inner spacer (e.g., inner spacer 410b) of the inner spacer, the second inner spacer being opposite to the first inner spacer.

[0090] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in conjunction with those described elsewhere in this document.

[0091] In the first embodiment, the step of performing the third etching operation includes the following steps: performing the third etching operation at a temperature greater than or equal to 20 degrees Celsius and less than or equal to 60 degrees Celsius.

[0092] In the second embodiment, the step of performing the third etching operation, either alone or in combination with the first embodiment, includes the following steps: performing the third etching operation under a pressure greater than or approximately equal to 0.2 Torr and less than or approximately equal to 2 Torr.

[0093] In the third embodiment, the step of performing the third etching operation, either alone or in combination with one or more of the first and second embodiments, includes the following steps: performing the third etching operation using a fluorine-based etchant (e.g., as shown in component symbol 715a), wherein the fluorine-based etchant removes material from the nanostructure channels during the third etching operation.

[0094] In the fourth embodiment, the step of performing the third etching operation, either alone or in combination with one or more of the first to third embodiments, includes the following steps: performing the third etching operation using a hydrofluoric acid etchant (e.g., as shown in component symbol 715b), wherein the hydrofluoric acid etchant removes material from the sacrificial nanostructure layer during the third etching operation.

[0095] Although Figure 10 illustrates an exemplary block of process 1000, in some implementations, process 1000 may include more blocks, fewer blocks, different blocks, or blocks with different arrangements than those shown in Figure 10. Alternatively, two or more blocks of process 1000 may be executed in parallel.

[0096] In this manner, the nanostructure channels of a nanostructured transistor are etched during the nanosheet release process to remove the sacrificial nanostructure layers between the nanostructure channels. The etching of the nanostructure channels is controlled to improve the efficiency of the etching process, thereby removing impurities from the central portion of the nanostructure channels. More specifically, parameters such as etching temperature and / or pressure are controlled to counteract high energy barriers and increase etchant adsorption. Therefore, the uniformity of material removal rate on the nanostructure channels during the etching process is improved, resulting in nanostructure channels with a substantially uniform surface profile. The technique described herein can reduce the channel resistance of nanostructured transistors, thereby improving their performance.

[0097] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure surrounding the nanostructured channels. The semiconductor device includes a first source / drain region adjacent to a first side of the gate structure. The semiconductor device includes a second source / drain region adjacent to a second side of the gate structure, the second side being opposite to the first side, wherein each nanostructured channel of the nanostructured channel adjacent to the gate structure includes an arcuate surface along a direction between the first source / drain region and the second source / drain region.

[0098] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure surrounding the nanostructured channels, with a first source / drain region adjacent to a first side of the gate structure. The semiconductor device includes a second source / drain region adjacent to a second side of the gate structure, the second side opposite to the first side, wherein the side surface of each portion of the gate structure adjacent to each nanostructured channel includes an arcuate surface along a direction between the first source / drain region and the second source / drain region.

[0099] As described in more detail above, some embodiments described herein provide a method. The method includes the steps of: forming a plurality of nanostructured semiconductor layers and a plurality of nanostructured sacrificial layers, such that the nanostructured semiconductor layers and nanostructured sacrificial layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device. The method includes the steps of: performing a first etching operation to etch the nanostructured semiconductor layers and nanostructured sacrificial layers to define a plurality of nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate, wherein the nanostructured channels and nanostructured sacrificial layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate. The method includes the step of: performing a second etching operation to etch the ends of the nanostructured sacrificial layers. The method includes the step of: forming a plurality of inner spacers adjacent to the etched ends of the nanostructured sacrificial layers. The method includes the following steps: performing a third etch operation to remove a nanostructure sacrificial layer from a semiconductor device, wherein the third etch operation causes the surface of each nanostructure channel of the nanostructure channel to have a curved concave shape, the curved concave shape extending between a first inner spacer and a second inner spacer, the second inner spacer being opposite to the first inner spacer.

[0100] The terms "approximately" and "substantially" can mean that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0101] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

[0102] 100, 200, 300, 400, 500, 600, 700, 800, 900: Implementation 105: Semiconductor Devices 110: Semiconductor substrate 115: Layer stacking 120: Sacrificial Nanostructure Layer 125: Nanostructured Channel Layer 130: Hybrid Layer 135: Hard mask layer 140: Overlay 145: Oxide layer 150: Nitride layer 155: Fin-shaped structure 155a: First fin-shaped structure subset 155b: Second fin-shaped structure subset 160: Part 165: Fin-shaped part 170: Padding 175: STI region 205: Virtual gate structure 210: Gate electrode layer 215: Hard mask layer 220a: First spacer layer 220b: Second spacer layer 225: Gate dielectric layer 305: Source / Drain Groove 310: Countertop area 315: Nanostructured Channel 405: Cavity 410: Internal spacer 410a: First inner spacer 410b: Second inner spacer 505: Buffer Area 510: Source / Drain Region 510a: First source / drain region 510b: Second source / drain region 515: Covering layer 605: Dielectric layer 705: Outline Section 710: Etching agent 715a, 715b: Component symbols 725: Section 725a: First outer segment 725b: Center Section 725c: Second outer segment 805: Gate structure 810: Gate electrode layer 815: Work function metal layer 820: Gate Dielectric Layer 825: Close-up view 830: Gate structure arc-shaped surface 1000: Process Blocks 1010, 1020, 1030, 1040, 1050 AA, BB, CC: Cross-sections D1~D6: Dimensions X, Y, Z: Direction

[0103] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device comprising: a plurality of nanostructure channels arranged in a direction perpendicular to a semiconductor substrate of the semiconductor device; a gate structure surrounding the nanostructure channels; a first source / drain region adjacent to a first side of the gate structure; and a second source / drain region adjacent to a second side of the gate structure, the second side being opposite to the first side, wherein each of the nanostructure channels adjacent to the gate structure includes an arcuate surface along a direction between the first source / drain region and the second source / drain region, and each of the nanostructure channels includes a first cross-sectional thickness of a central portion and a second cross-sectional thickness of a plurality of external portions adjacent to the first source / drain region and the second source / drain region, wherein the first cross-sectional thickness is smaller than the second cross-sectional thickness.

2. The semiconductor device of claim 1, further comprising: a plurality of first inner spacers adjacent to the first source / drain region; and a plurality of second inner spacers adjacent to the second source / drain region, wherein the arcuate surface is located between one of the first inner spacers and one of the second inner spacers, the second inner spacers being opposite to the first inner spacers.

3. The semiconductor device of claim 2, wherein the arcuate surface includes a first edge in contact with the first inner spacer and a second edge in contact with the second inner spacer.

4. A semiconductor device comprising: a plurality of nanostructure channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure surrounding the nanostructure channels; a first source / drain region adjacent to a first side of the gate structure; and a second source / drain region adjacent to a second side of the gate structure, the second side being opposite to the first side, wherein the side surface of each portion of each nanostructure channel adjacent to the nanostructure channels of the gate structure includes an arcuate surface along a direction between the first source / drain region and the second source / drain region, and each nanostructure channel includes a first cross-sectional thickness of a central portion and a second cross-sectional thickness of a plurality of outer portions adjacent to the first source / drain region and the second source / drain region, wherein the first cross-sectional thickness is smaller than the second cross-sectional thickness.

5. The semiconductor device of claim 4, further comprising: a plurality of first inner spacers located between portions of the gate structure and the first source / drain region; and a plurality of second inner spacers located between portions of the gate structure and the second source / drain region, wherein the arcuate surface is located between one of the first inner spacers and one of the second inner spacers, the second inner spacers being opposite to the first inner spacers.

6. The semiconductor device as claimed in claim 4, wherein: Each part of the gate structure includes a gate dielectric layer and a metal layer located on the gate dielectric layer; and the gate dielectric layer includes the arc-shaped surface.

7. The semiconductor device as claimed in claim 4, wherein the arcuate surface includes a convex profile.

8. A method of forming a semiconductor device, comprising the steps of: forming a plurality of nanostructure semiconductor layers and a plurality of nanostructure sacrificial layers, such that the nanostructure semiconductor layers and the nanostructure sacrificial layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; performing a first etching operation to etch the nanostructure semiconductor layers and the nanostructure sacrificial layers to define a plurality of nanostructure channels arranged approximately perpendicular to the semiconductor substrate in the direction approximately perpendicular to the semiconductor substrate, wherein the nanostructure channels and the nanostructure sacrificial layers are arranged alternately in the direction approximately perpendicular to the semiconductor substrate; performing a second etching operation to etch a plurality of ends of the nanostructure sacrificial layers; forming a plurality of inner spacers adjacent to the etched ends of the nanostructure sacrificial layers; and performing a third etching operation to remove the nanostructure sacrificial layers from the semiconductor device. The third etching operation results in each of the nanostructure channels having a curved concave shape on its surface, which extends between a first inner spacer and a second inner spacer, with the second inner spacer opposite to the first inner spacer.

9. The method of claim 8, wherein the step of performing the third etching operation comprises the following steps: performing the third etching operation using a fluorine-based etchant, wherein the fluorine-based etchant removes material from the nanostructure channels during the third etching operation.

10. The method of claim 8, wherein the step of performing the third etching operation comprises the following steps: performing the third etching operation using a hydrofluoric acid etchant, wherein the hydrofluoric acid etchant removes material from the nanostructure sacrificial layer during the third etching operation.

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