Forming method of semiconductor device

Abstract

A method of forming a semiconductor device includes forming a plurality of first patterns extending in a first direction in a first hard mask layer on a substrate, wherein each of the first patterns includes a first central segment and two first end segments; forming a plurality of second patterns extending in a second direction different from the first direction in a second hard mask layer on a substrate, wherein each of the second patterns includes a second central segment and two second end segments; forming a hole pattern in a third hard mask layer by using the first and second patterns, wherein the third hard mask layer is located above the substrate and below the first and second hard mask layers; forming a photoresist layer to cover the second central segment of the second patterns; and removing the first end segments of the first patterns and the second end segments of the second patterns.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor device. Prior Technology

[0002] The yield of capacitor vias in semiconductor devices is determined by the quality of the via pattern used as a mask. However, in conventional methods, the mask is formed around the perimeter of the via pattern, and the vias are exposed. That is, the edges of such a mask are directly adjacent to the vias. This requires high precision in edge location and easily leads to poor via quality. Subsequent layer alignment and stack-up measurements are achieved using a matrix mask, defined by the aforementioned mask and capacitor vias. Therefore, poor edge quality results in poor alignment and stack-up measurement signals. The stack-up in subsequent processes will suffer from the consequences of poor alignment and stack-up.

[0003] Therefore, providing a method that can deliver high-quality hole patterns remains a goal of research and development in this field. Summary of the Invention

[0004] One of the technical features disclosed herein is a method for forming a semiconductor device.

[0005] In one embodiment of this disclosure, a method of forming a semiconductor device includes forming a plurality of first patterns extending in a first direction in a first hard mask layer on a substrate, wherein each of the first patterns includes a first central segment and two first end segments; forming a plurality of second patterns extending in a second direction different from the first direction in a first hard mask layer on a substrate, wherein each of the second patterns includes a second central segment and two second end segments; forming a hole pattern in a third hard mask layer by using the first and second patterns, wherein the third hard mask layer is located above the substrate and below the first and second hard mask layers; forming a photoresist layer to cover the second central segment of the second patterns; and removing the first end segments of the first patterns and the second end segments of the second patterns.

[0006] In one embodiment of this disclosure, forming the first pattern further includes forming a plurality of first dummy patterns on the first hard mask layer; forming a plurality of first spacer layers respectively surrounding the first dummy patterns; removing the first dummy patterns; and etching the first hard mask layer using the first spacer layers to form the first pattern.

[0007] In one embodiment of this disclosure, forming the first pattern further includes forming a plurality of second dummy patterns on a second hard mask layer; forming a plurality of second spacer layers respectively surrounding the second dummy patterns; removing the second dummy patterns; and using the second spacer layers to etch the second hard mask layer to form the second pattern.

[0008] In one embodiment of this disclosure, forming a photoresist layer to cover a second central segment of the second pattern further includes forming a photoresist layer such that a first end segment of the first pattern and a second end segment of the second pattern are exposed from the photoresist layer.

[0009] In one embodiment of this disclosure, forming a photoresist layer to cover a second central segment of a second pattern further includes forming a photoresist layer such that there is a first distance between a first edge of the photoresist layer along a first direction and one of the first edges of the first pattern closest to the first edge, and the first distance is in the range of 0 to 50 nanometers.

[0010] In one embodiment of this disclosure, forming a photoresist layer to cover a second central segment of a second pattern further includes forming a photoresist layer such that there is a second distance between a second edge of the photoresist layer along a second direction and one of the second edges of the second pattern, and the second distance is in the range of 0 to 50 nanometers.

[0011] In one embodiment of this disclosure, forming a hole pattern in a third hard mask layer using a first pattern and a second pattern further includes making the size of a plurality of holes in the hole pattern range from 20x20 nanometers square to 50x50 nanometers square.

[0012] In one embodiment of this disclosure, the method of forming a display device further includes filling a gap filler material around a hole pattern, wherein the gap filler material does not fill the plurality of holes in the hole pattern.

[0013] In one embodiment of this disclosure, the method of forming a display device further includes using a void-filling material that is a low-flow material.

[0014] In one embodiment of this disclosure, the method of forming the display device further includes etching a void-filling material to expose the upper surface of the hole pattern.

[0015] In one embodiment of this disclosure, the method for forming a semiconductor device further includes forming a plurality of capacitor vias by etching a substrate using a hole pattern.

[0016] One of the technical features disclosed herein is a method for forming a semiconductor device.

[0017] In one embodiment of this disclosure, a method for forming a semiconductor device includes forming a hole pattern in a first hard mask layer on a substrate, wherein the hole pattern includes a central segment and a plurality of end segments surrounding the central segment; forming a photoresist layer to cover the central segment of the hole pattern; removing the end segments of the hole pattern; and etching the substrate using the hole pattern to form a plurality of capacitor vias.

[0018] In one embodiment of this disclosure, forming a hole pattern in the first hard mask layer further includes making the size of a plurality of holes in the hole pattern range from 20x20 nanometers square to 50x50 nanometers square.

[0019] In one embodiment of this disclosure, the method of forming a semiconductor device further includes filling a void filler material around a hole pattern, wherein the void filler material does not fill the holes.

[0020] In one embodiment of this disclosure, forming the hole pattern in the first hard mask layer further includes an etched void-filling material to expose the upper surface of the hole pattern.

[0021] In one embodiment of this disclosure, forming a hole pattern in a first hard mask layer further includes forming a plurality of first patterns extending in a first direction in a second hard mask layer, wherein each of the first patterns includes a first central segment and two first end segments.

[0022] In one embodiment of this disclosure, forming a photoresist layer to cover the central segment of the hole pattern further includes forming a photoresist layer such that there is a first distance between a first edge of the photoresist layer along a first direction and one of the first edges of the first pattern closest to the first edge, and the first distance is in the range of 0 to 50 nanometers.

[0023] In one embodiment of this disclosure, forming a hole pattern in a first hard mask layer further includes forming a plurality of second patterns extending in a second direction different from the first direction in a third hard mask layer, wherein each of the second patterns includes a second central segment and two second end segments.

[0024] In one embodiment of this disclosure, the first central segment and the second central segment define the central segment of the hole pattern.

[0025] In one embodiment of this disclosure, forming a photoresist layer to cover the central segment of the hole pattern further includes forming a photoresist layer such that there is a second distance between the second edge of the photoresist layer along the second direction and one of the second edges of the second pattern, and the second distance is in the range of 0 to 50 nanometers.

[0026] In the above embodiments, the disclosed method allows for a more relaxed requirement for the precision of the photoresist layer's edge location by using a photoresist layer to cover the first central segment of the first pattern and the second central segment of the second pattern. Furthermore, since the gap-filling material cannot be inserted into the holes, it helps maintain the shape of the holes. This improves the yield of the capacitor holes. Simple Explanation of the Diagram

[0027] Figure 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 2B is a cross-sectional view of Figure 2A along line segment 2B-2B. Figure 3A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 3B is a cross-sectional view of Figure 3A along line segment 3B-3B. Figure 4A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 4B is a cross-sectional view of Figure 4A along line segment 4B-4B. Figure 5A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 5B is a cross-sectional view of Figure 5A along line segment 5B-5B. Figures 6A and 6B are schematic diagrams of a first pattern and a second pattern according to different embodiments of the present disclosure. Figure 7A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 7B is a cross-sectional view of Figure 7A along line segment 7B-7B. Figure 8A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 8B is a cross-sectional view of Figure 8A along line segment 8B-8B. Figure 9 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 10A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 10B is a cross-sectional view of Figure 10A along line segment 10B-10B. Figure 11 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 12 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Implementation

[0028] The following drawings disclose several embodiments of this disclosure. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner. And for clarity, the thickness of layers and regions in the drawings may be exaggerated, and the same element symbols represent the same elements in the description of the drawings.

[0029] Figure 1 is a cross-sectional view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 2B is a cross-sectional view of Figure 2A along line segment 2B-2B. Figure 3A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 3B is a cross-sectional view of Figure 3A along line segment 3B-3B.

[0030] The method for forming a semiconductor device begins by forming a plurality of first patterns 136 (Figure 3B) extending in a first direction D1 in a first hard mask layer 120 on a substrate 110. The first hard mask layer 120 is disposed on a third hard mask layer 140, and the third hard mask layer 140 is disposed on the substrate 110. The substrate 110 includes multiple layers, such as a lower silicon nitride layer, a boro-phospho-silicate glass (BPSG) layer, an oxide layer, and an upper silicon nitride layer. For example, the step of forming the first pattern 136 is illustrated in Figures 1, 2A, 2B, 3A, and 3B. In this embodiment, the step of forming the first pattern 136 is a self-aligned double patterning (SADP) method. In other embodiments, the step of forming the first pattern 136 is a litho-etch-litho-etch (LELE) method, a litho-freeze-litho-etch (LFLE) method, or other suitable methods.

[0031] As shown in Figure 1, a plurality of first dummy patterns 132 are formed on the first hard mask layer 120. As shown in Figures 2A and 2B, a plurality of first spacer layers 134 are formed to surround the first dummy patterns 132 respectively. Specifically, the material of the first spacer layers 134 is first deposited to cover the first dummy patterns 132 and the first hard mask layer 120, and then a portion of the material above the first hard mask layer 120 and on the upper surface of the first dummy patterns 132 is removed. Therefore, as shown in Figure 2A, each first spacer layer 134 has a rectangle surrounding the first dummy pattern 132, and the first dummy pattern 132 is exposed.

[0032] As shown in Figures 3A and 3B, the first dummy pattern 132 is removed, and a first hard mask layer 120 is etched using a first spacer layer 134 as a mask to form a first pattern 136. Each first pattern 136 includes a first central segment 1362 and two first end segments 1364 and 1366. The first central segment 1362 corresponds to the segment that will be used to form capacitor vias in subsequent processes. The first end segments 1364 and 1366 correspond to the segments that will be removed in subsequent processes.

[0033] Figure 4A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 4B is a cross-sectional view of Figure 4A along line segment 4B-4B. Figure 5A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 5B is a cross-sectional view of Figure 5A along line segment 5B-5B.

[0034] The method for forming a semiconductor device continues to the step of forming a plurality of second patterns 176 extending in a second direction D2 different from the first direction D1. As shown in Figure 4A, a first spacer layer 134 and the first patterns 136 are covered by a dielectric layer 150, and a second hard mask layer 160 is disposed above the dielectric layer 150. A second dummy pattern 172 is formed on the second hard mask layer 160. A second spacer layer 174 is formed to surround the second dummy pattern 172. The process for forming the second dummy pattern 172 and the second spacer layer 174 is substantially the same as the process for forming the first dummy pattern 132 and the first spacer layer 134 in Figures 1 and 2B.

[0035] As shown in Figures 5A and 5B, the second dummy pattern 172 is removed, and a second hard mask layer 160 is etched using a second spacer layer 174 as a mask to form a second pattern 176. Each second pattern 176 includes a second central segment 1762 and two second end segments 1764 and 1766. The second central segment 1762 corresponds to the segment that will be used to form capacitor vias in subsequent processes. The second end segments 1764 and 1766 correspond to the segments that will be removed in subsequent processes.

[0036] Figures 6A and 6B are schematic diagrams of a first pattern 136a and a second pattern 176a according to different embodiments of the present disclosure. As shown in Figure 6A, the first pattern 136a and the second pattern 176a extend in a third direction D3 and a fourth direction D4, different from the first direction D1 and the second direction D2. As shown in Figure 6B, the first pattern 136b and the second pattern 176b extend in a fifth direction D5 and a sixth direction D6, different from the first direction D1 and the second direction D2. The angular difference between the fifth direction D5 and the sixth direction D6 may be different from 90 degrees.

[0037] Figure 7A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 7B is a cross-sectional view of Figure 7A along line segment 7B-7B. The method for forming the semiconductor device continues to form a hole pattern 142 in a third hard mask layer 140 by using a first pattern 136 and a second pattern 176 as a mask. The third hard mask layer 140 is etched to transform the first pattern 136 and the second pattern 176 to form the hole pattern 142. Therefore, a first central segment 1362 of the first pattern 136 (Figure 3A) spans a second central segment 1762 of the second pattern 176 (Figure 5A) and forms a plurality of holes 144. In other words, a first central segment 1362 of the first pattern 136 (Figure 3A) spans a second central segment 1762 of the second pattern 176 to define the central segment of the hole pattern 142. The size of the holes 144 in the hole pattern 142 ranges from 20x20 nanometer square to 50x50 nanometer square.

[0038] Figure 8A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 8B is a cross-sectional view of Figure 8A along line segment 8B-8B. The method for forming the semiconductor device continues to the step of forming a photoresist layer 180 to cover the first central segment 1362 of the first pattern 136 and the second central segment 1762 of the second pattern 176. That is, the plurality of holes 144 of the hole pattern 142 are covered by the photoresist layer 180. The first end segments 1364, 1366 of the first pattern 136 and the second end segments 1764, 1766 of the second pattern 176 are exposed from the photoresist layer 180.

[0039] Referring to Figure 8B, a first distance L1 exists between the first edge 182 of the photoresist layer 180 along the first direction D1 and the closest one of the first patterns 136 to the first edge 182, and the first distance L1 is in the range of 0 to 50 nanometers. Similarly, a second distance L2 exists between the second edge 184 of the photoresist layer 180 along the second direction D2 and the closest one of the second patterns 176 to the second edge 184, and the second distance L2 is in the range of 0 to 50 nanometers.

[0040] In this way, the first distance L1 does not affect the shape of the hole 144. In other words, the precision requirement for the location of the edge of the photoresist layer 180 is less stringent. In conventional methods, the photoresist layer is formed to cover the edge region of the hole pattern 142. That is, the photoresist layer covers the first end segments 1364 and 1366 of the first pattern 136 and the second end segments 1764 and 1766 of the second pattern 176, and the edge of the photoresist layer is directly adjacent to the hole 144. As a result, the precision requirement for the location of the edge of the photoresist layer is higher. Otherwise, the shape of the hole 144 will be affected.

[0041] Figure 9 is a cross-sectional view of an intermediate state of a semiconductor device formation method according to an embodiment of the present disclosure. Referring to Figures 8A and 9, the semiconductor device formation method continues to the step of removing the first end segments 1364, 1366 of the first pattern 136 and the second end segments 1764, 1766 of the second pattern 176. After removing the second end segments 1764, 1766 of the second pattern 176, the photoresist layer 180 is removed to expose the first central segment 1362 of the first pattern 136 and the second central segment 1762 of the second pattern 176.

[0042] Figure 10A is a top view of an intermediate state of a method for forming a semiconductor device according to an embodiment of the present disclosure. Figure 10B is a cross-sectional view of Figure 10A along line segment 10B-10B. The method for forming the semiconductor device continues to fill the gaps with a filler material 190 around the hole pattern 142, wherein the gap filler material 190 does not fill the holes 144. Referring to Figure 10B, because the gap filler material 190 has low resin flowability, high molecular weight, high etch resistance, high flatness, and more reactive resin, the gap filler material 190 may not fill the holes 144 of the hole pattern 142.

[0043] Figure 11 is a cross-sectional view of an intermediate state of a semiconductor device formation method according to an embodiment of the present disclosure. The semiconductor device formation method continues until the gap-filling material 190 is polished or etched back until the upper surface of the hole pattern 142 is exposed to confirm that no remaining gap-filling material 190 remains in the holes 144. Since the gap-filling material 190 cannot fill the holes 144, it is beneficial to maintain the shape of the holes 144.

[0044] Figure 12 is a cross-sectional view of an intermediate state of a semiconductor device formation method according to an embodiment of the present disclosure. The semiconductor device formation method continues to the step of etching a substrate 110 using a hole pattern 142 to form capacitor holes 112.

[0045] In summary, the method disclosed herein allows for a more relaxed requirement regarding the precision of the photoresist layer's edge location by using a photoresist layer to cover the first central segment of the first pattern and the second central segment of the second pattern. Furthermore, since the gap-filling material cannot be inserted into the holes, it helps maintain the shape of the holes. This, in turn, improves the yield of capacitor holes.

[0046] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art may make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0047] 110:Substrate 112: Capacitor hole 120: First hard mask layer 132: First Dummy Pattern 134: First Spacing Layer 136, 136a, 136b: First pattern 1362: First Central Section 1364, 1366: First terminal section 140: Third hard mask layer 142: Hole Pattern 144: Hole 150: Dielectric layer 160: Second hard mask layer 172: Second dummy pattern 174: Second spacer layer 176, 176a, 176b: Second pattern 1762: Second Central Section 1764, 1766: Second terminal section 180: Photoresist layer 182: First Edge 184: Second Edge 190: Void filling material D1: First Direction D2: Second Direction D3: Third direction D4: Fourth Direction D5: Fifth Direction D6: Sixth Direction L1: First distance L2: Second distance 2B-2B, 3B-3B, 4B-4B, 5B-5B, 7B-7B, 8B-8B, 10B-10B: line segments

Claims

1. A method of forming a semiconductor device, comprising: forming a first hard mask layer in which a plurality of first patterns extending in a first direction are in a first hard mask layer on a substrate, wherein each of the first patterns includes a first central segment and two first end segments; forming a plurality of second patterns in a second hard mask layer in which the first patterns extend in a second direction different from the first direction are in a second hard mask layer on a substrate, wherein each of the second patterns includes a second central segment and two second end segments; forming a hole pattern in a third hard mask layer by using the first patterns and the second patterns, wherein the third hard mask layer is located above the substrate and below the first hard mask layer and the second hard mask layer; forming a photoresist layer to cover the second central segments of the second patterns; and removing the first end segments of the first patterns and the two second end segments of the second patterns.

2. The method of forming a semiconductor device as claimed in claim 1, wherein forming the first patterns further comprises: forming a plurality of first dummy patterns on the first hard mask layer; forming a plurality of first spacer layers respectively surrounding the first dummy patterns; removing the first dummy patterns; and etching the first hard mask layer using the first spacer layers to form the first patterns.

3. The method of forming a semiconductor device as claimed in claim 2, wherein forming the first patterns further comprises: forming a plurality of second dummy patterns on the second hard mask layer; forming a plurality of second spacer layers surrounding the second dummy patterns; removing the second dummy patterns; and etching the second hard mask layer using the second spacer layers to form the second patterns.

4. The method of forming a semiconductor device as claimed in claim 1, wherein forming the photoresist layer to cover the second central sections of the second patterns further comprises: forming the photoresist layer such that the first end sections of the first patterns and the two second end sections of the second patterns are exposed from the photoresist layer.

5. The method of forming a semiconductor device as claimed in claim 1, wherein forming the photoresist layer to cover the second central segments of the second patterns further comprises: forming the photoresist layer such that there is a first distance between a first edge of the photoresist layer along the first direction and one of the first patterns closest to the first edge, and the first distance is in the range of 0 to 50 nanometers.

6. The method of forming a semiconductor device as claimed in claim 1, wherein forming the photoresist layer to cover the second central segments of the second patterns further comprises: forming the photoresist layer such that there is a second distance between a second edge of the photoresist layer along the second direction and one of the second patterns closest to the second edge, and the second distance is in the range of 0 to 50 nanometers.

7. The method of forming a semiconductor device as claimed in claim 1, wherein forming the hole pattern in the third hard mask layer by using the first pattern and the second pattern further comprises: making a size of a plurality of holes in the hole pattern in the range of 20x20 nanometers square to 50x50 nanometers square.

8. The method of forming a semiconductor device as claimed in claim 1, further comprising: filling a void filling material around the hole pattern, wherein the void filling material does not fill any of the plurality of holes in the hole pattern.

9. A method for forming a semiconductor device as described in claim 8, wherein the void-filling material is a low-flow-rate material.

10. The method of forming a semiconductor device as claimed in claim 8, further comprising: etching the void-filling material to expose an upper surface of the hole pattern.

11. The method of forming a semiconductor device as claimed in claim 10 further comprises: etching the substrate using the hole pattern to form a plurality of capacitor vias.

12. A method of forming a semiconductor device, comprising: forming a hole pattern in a first hard mask layer on a substrate, wherein the hole pattern includes a central segment and a plurality of end segments surrounding the central segment, the method of forming the hole pattern in the first hard mask layer comprising: forming a plurality of first patterns extending in a first direction in a second hard mask layer on the substrate, wherein each of the first patterns includes a first central segment and two first end segments; forming a photoresist layer to cover the central segment of the hole pattern; removing the end segments of the hole pattern; and etching the substrate using the hole pattern to form a plurality of capacitor vias.

13. The method of forming a semiconductor device as claimed in claim 12, wherein forming the hole pattern in the first hard mask layer further comprises: making a size of a plurality of holes in the hole pattern be between 20 x 20 nanometers square and 50 x 50 nanometers square.

14. The method of forming a semiconductor device as claimed in claim 13, further comprising: filling a void filling material around the hole pattern, wherein the void filling material does not fill the holes.

15. The method of forming a semiconductor device as claimed in claim 14, wherein forming the hole pattern in the first hard mask layer further comprises: etching the void-filling material to expose an upper surface of the hole pattern.

16. The method of forming a semiconductor device as claimed in claim 12, wherein forming the photoresist layer to cover the central segment of the aperture pattern further comprises: forming the photoresist layer such that there is a first distance between a first edge of the photoresist layer along the first direction and one of the first patterns closest to the first edge, and the first distance is in the range of 0 to 50 nanometers.

17. The method of forming a semiconductor device as claimed in claim 16, wherein forming the hole pattern in the first hard mask layer further comprises: forming a plurality of second patterns extending in a second direction different from the first direction in a third hard mask layer on the substrate, wherein each of the second patterns includes a second central segment and two second end segments.

18. A method of forming a semiconductor device as claimed in claim 17, wherein the first central segment and the second central segment define the central segment of the hole pattern.

19. The method of forming a semiconductor device as claimed in claim 17, wherein forming the photoresist layer to cover the central segment of the aperture pattern further comprises: forming the photoresist layer such that there is a second distance between a second edge of the photoresist layer along the second direction and one of the second patterns closest to the second edge, and the second distance is in the range of 0 to 50 nanometers.

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