Chip package and method for forming the same

Abstract

A wafer package is provided, comprising: a device substrate, a metallization layer, a first redistribution layer, a passivation sheath structure, and a stop layer. The metallization layer and the first redistribution layer are respectively disposed on a front surface and a back surface of the device substrate. The passivation sheath structure covers an edge surface surrounding the device substrate and extends to the back surface, covering the first redistribution layer. The stop layer is disposed within the metallization layer and aligned with the passivation sheath structure covering the edge surface, thereby surrounding the device substrate.

Description

[Technical Field]

[0001] This invention relates to a wafer packaging technology, and more particularly to a wafer package that can increase the structural strength of a wafer and a method for manufacturing the same. [Previous Technology]

[0002] Various optoelectronic components are widely used in electronic products, such as desktop computers, laptops, tablets, mobile phones, digital cameras, and digital video recorders. Chip packaging is an important step in the process of forming electronic products. In addition to protecting the optoelectronic components from external environmental contamination, the chip package also provides an electrical connection path between the optoelectronic components and the outside world.

[0003] With the advancement of semiconductor technology and wafer packaging technology, the size of wafers may also change, posing challenges to wafer packaging technology. For example, when assembling thin wafers into a package, they are prone to warping or deformation due to insufficient rigidity of the wafer itself, increasing the difficulty of wafer packaging.

[0004] Therefore, it is necessary to seek a wafer package and its manufacturing method that can solve or improve the above-mentioned problems. [Summary of the Invention]

[0005] In this embodiment, a wafer package is provided, including a device substrate having an edge surface surrounding the device substrate. The wafer package also includes a metallization layer and a first redistribution layer, respectively disposed on a front surface and a back surface of the device substrate, and the first redistribution layer extends into the device substrate. The wafer package further includes a passivation sheath structure and a stop layer. The passivation sheath structure surrounds and covers the edge surface of the device substrate, and extends to the back surface and covers the first redistribution layer. The stop layer is disposed within the metallization layer and is aligned with the passivation sheath structure covering the edge surface and surrounds the device substrate.

[0006] In this embodiment, a method for manufacturing a wafer package is provided, comprising: providing a substrate having a wafer region and a dicing region surrounding the wafer region C. The method also includes forming a metallization layer on a front surface of the substrate, and the metallization layer having a first opening aligned with the dicing region and surrounding the wafer region C. The method further includes forming a stop layer within the first opening and forming a first redistribution layer on a back surface of the substrate and extending within the substrate. Additionally, the method includes forming a second opening within the substrate aligned with the dicing region to surround the wafer region and expose the stop layer. The method also includes forming a passivation sheath structure on the back surface. The passivation sheath structure fills the second opening and covers the first redistribution layer.

Implementation Method

[0008] The following will describe in detail the manufacturing and use of embodiments of the present invention. However, it should be noted that the present invention provides many applicable inventive concepts, which can be implemented in various specific forms. The specific embodiments discussed herein are merely specific ways of manufacturing and using the present invention and are not intended to limit the scope of the present invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present invention and do not represent any connection between the different embodiments and / or structures discussed. Moreover, when referring to a first material layer located on or above a second material layer, this includes situations where the first material layer and the second material layer are in direct contact or spaced apart by one or more other material layers.

[0009] The chip package of one embodiment of the present invention can be used to package microelectromechanical system (MEMS) chips. However, its application is not limited to this. For example, in the embodiments of the chip package of the present invention, it can be applied to various electronic components that include integrated circuits such as active or passive elements, digital or analog circuits, such as optoelectronic devices, microelectromechanical systems (MEMS), biometric devices, microfluidic systems, or physical sensors that measure changes in physical quantities such as heat, light, capacitance, and pressure. In particular, wafer-scale package (WSP) processes can be used to package semiconductor wafers such as image sensors, light-emitting diodes (LEDs), solar cells, radio frequency (RF) circuits, accelerometers, gyroscopes, fingerprint recognition devices, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads.

[0010] The aforementioned wafer-level packaging process mainly refers to the process of cutting the wafer into independent packages after the packaging steps are completed at the wafer stage. However, in a specific embodiment, for example, redistributing the separated semiconductor wafers onto a carrier wafer before performing the packaging process can also be referred to as a wafer-level packaging process. In addition, the aforementioned wafer-level packaging process is also applicable to arranging multiple wafers with integrated circuits in a stacked manner to form a multi-layer integrated circuit device (MID) chip package.

[0011] Figures 1A to 1J illustrate cross-sectional schematic diagrams of a method for manufacturing a wafer package according to some embodiments. In some embodiments, the wafer package is implemented as having a front-side illumination (FSI) sensing device. Referring to Figure 1A, a substrate 100W is provided. The substrate 100W has a front surface 100A (e.g., an active surface) and a back surface 100B (e.g., a non-active surface) opposite to the front surface 100A, and has a plurality of wafer regions (not shown) and a dicing channel region surrounding these wafer regions and separating adjacent wafer regions C. For the sake of simplicity, only a complete wafer region C and a dicing channel region SL separating the wafer region C are shown here (indicated by dashed lines). In some embodiments, the substrate 100W is a silicon wafer or other suitable semiconductor wafer to facilitate wafer-level packaging processes. In other embodiments, the substrate 100W may be a silicon substrate or other semiconductor substrate. In some embodiments, the substrate 100W of the wafer region C includes a circuit (not shown) and signals are input and output through subsequently formed pads.

[0012] Furthermore, a metallization layer 102 and one or more conductive pads 102B are located on the front surface 100A of the substrate 100W. In some embodiments, the metallization layer 102 formed on the front surface 100A may include an interlayer dielectric (ILD) layer, an inter-metal dielectric (IMD) layer, a passivation layer, or a combination thereof. For simplicity, only a planar layer is shown here. In some embodiments, the metallization layer 102 has an opening 106 aligned with the dicing region SL and surrounding the wafer region C. The opening 106 may penetrate the metallization layer 102 and extend partially from the front surface 100A into the substrate 100W, and may be formed by a laser grooving process. The opening 106 formed corresponding to the dicing region SL by laser grooving can mitigate the problem of reduced reliability due to cracking of the metallization layer 102 formed from low-dielectric materials.

[0013] In some embodiments, conductive pads 102B are formed within the metallization layer 102 before the opening 106 is formed, and optical components 104 are correspondingly formed on the metallization layer 102 of each wafer region C. In some embodiments, conductive pads 102B serve as input / output (I / O) pads and may be single-layer or multi-layer structures. For simplicity, only conductive pads 102B with a single-layer structure are illustrated here as examples. Conductive pads 102B may include metallic materials, such as copper, aluminum, combinations thereof, or other suitable pad materials. It is understood that the number of conductive pads 102B depends on design requirements and is not limited to the embodiment shown in Figure 1A.

[0014] In some embodiments, the optical component 104 is formed on the metallization layer 102 of each wafer region C and corresponds to a sensing region of the substrate 100W of each wafer region C. The optical component 104 may include a microlens array, a filter layer, a combination thereof, or other suitable optical components. The sensing region includes a sensing device 100S adjacent to the front surface 100A of the substrate 100W. For example, the sensing device may be an image sensing device or another suitable sensing device. In other embodiments, the sensing device includes a device for sensing biometrics (e.g., a fingerprint recognition device), a device for sensing environmental characteristics (e.g., a temperature sensing element, a humidity sensing element, a pressure sensing element, a capacitance sensing element), or another suitable sensing device.

[0015] Referring to Figure 1B, after the opening 106 is formed, a stop layer 108 is formed within the opening 106. The stop layer 108 can serve as a stop layer for subsequent pre-cutting processes (e.g., sawing processes). Additionally, the stop layer 108 can also serve as a stress buffer layer during the sawing process, thereby protecting the adjacent metallization layer 102. In some embodiments, the stop layer 108 includes epoxy resin, organic polymer materials (e.g., polyimide, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, acrylates), photoresist materials, or other suitable insulating materials.

[0016] Referring to Figure 1C, in some embodiments, after the stop layer 108 is formed, an adhesive layer 112 is formed on the metallization layer 102 and covers the optical component 104. The adhesive layer 112 serves as a temporary bonding layer, providing a flat surface for the structure of Figure 1B, to facilitate the attachment of the front surface 100A of the substrate 100W to a support substrate.

[0017] Referring to Figure 1D, in some embodiments, after the adhesive layer 112 is formed, a carrier substrate 116 is attached to the adhesive layer 112 via an adhesive tape layer 114 to temporarily bond the substrate 100W to the carrier substrate 116. For example, the adhesive layer 112 and / or the adhesive tape layer 114 may include temporary bonding materials such as light-to-heat conversion (LTHC), UV curing, or thermal curing. Additionally, the carrier substrate 116 may be made of silicon, glass, ceramic, or a suitable substrate material and may have a wafer shape to facilitate wafer-level packaging processes. For example, the carrier substrate 116 is a glass wafer and serves as a temporary support structure during the manufacturing of the substrate 100W. In some embodiments, the adhesive layer 112 may serve as a bonding layer between the carrier substrate 116 and other structures to temporarily bond the carrier substrate 116 to other structures.

[0018] Subsequently, a thinning process (e.g., etching, milling, grinding, or polishing) is performed on the back surface 100B of the substrate 100W to reduce the thickness of the substrate 100W.

[0019] Referring to Figure 1E, in some embodiments, after a thinning process, one or more openings 120 are formed within the substrate 100W, extending from the back surface 100B to the front surface 100A. For example, one or more openings 120 in the substrate 100W of each wafer region C can be formed through lithography and etching processes (e.g., dry etching, wet etching, plasma etching, reactive ion etching, or other suitable processes). The openings 120 penetrate the substrate 100W and extend into the metallization layer 102 to expose the conductive pads 102B.

[0020] Next, an insulating liner 122 (or electrical isolation layer) is compliantly formed on the back surface 100B of the substrate 100W. The insulating liner 122 is also compliantly deposited on the sidewall surface of the opening 120. In some embodiments, the insulating liner 122 may be silicon oxide or other suitable insulating materials. For example, the insulating liner 122 made of silicon oxide may be formed through a deposition process (e.g., thermal oxidation process, coating process, physical vapor deposition process, chemical vapor deposition process, or other suitable process).

[0021] Referring to Figure 1F, in some embodiments, a patterned redistribution layer (RDL) 130 is formed on an insulating liner 122 above the back surface 100B of the substrate 100W. In some embodiments, the patterned redistribution layer 130 may be formed sequentially through a deposition process (e.g., a coating process, a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless plating process, or other suitable processes), a lithography process, and an etching process. For example, a conductive layer (not shown) may be conformally formed on the insulating liner 122 through an electroplating process. The conductive layer is also conformally formed on the insulating liner 122 located on the sidewall surface of the opening 120 and directly electrically contacts or indirectly electrically connects to the exposed conductive pads 102B through the opening 120. Subsequently, the conductive layer is patterned sequentially through a lithography process and an etching process to form the redistribution layer 130. The conductive layer may include aluminum, titanium, tungsten, copper, or combinations thereof, or other suitable conductive materials.

[0022] In some embodiments, a redistribution layer 130 is formed on the back surface 100B of the substrate 100W and extends compliantly to the sidewall surface and bottom surface of the opening 120. The redistribution layer 130 is electrically isolated from the substrate 100W through an insulating liner 122 and is directly or indirectly electrically connected to the exposed conductive pads 102B via the opening 120. In this way, the redistribution layer 130 within the opening 120 forms a through-substrate via (TSV) electrode.

[0023] Referring to Figure 1G, in some embodiments, an opening 140 is formed within the substrate 100W and aligned with the dicing channel SL to surround the wafer region C and expose the stop layer 108 located within the metallization layer 102. In some embodiments, a sawing process may be performed along the dicing channel SL to form the opening 140. In some embodiments, the opening 140 extends through the substrate 100W and partially extends into the stop layer 108. For example, it extends to half the thickness of the stop layer 108. In other embodiments, the opening 140 extends through the substrate 100W but does not extend into the stop layer 108.

[0024] Referring to Figure 1H, in some embodiments, a passivation sheath structure is formed on the back surface 100B of the substrate 100W. The passivation sheath structure covers the redistribution layer 130 and extends into the openings 120 and 140. In some embodiments, the passivation sheath structure has a monolayer structure. For example, the passivation sheath structure is composed of a monolayer passivation sheath 150A. The monolayer passivation sheath 150A is then patterned so that a plurality of openings are formed within the patterned monolayer passivation sheath 150A to expose the redistribution layer 130 underneath. The portion of the redistribution layer 130 exposed through the openings serves as a pad area for electrically connecting to an external circuit (not shown). The monolayer passivation sheath 150A may be made of a monolayer organic polymer material (examples of organic polymer materials include polyimide resin, phenylcyclobutene (BCB), parylene, naphthalene polymer, fluorocarbon, and acrylate).

[0025] As shown in Figure 1H, the single-layer passivation sheath 150A plugs the openings 120 and 140. In some embodiments, the single-layer passivation sheath 150A completely fills the opening 140 but not the opening 120. For example, a void 152 is formed between the single-layer passivation sheath 150A located in the opening 120 and the redistribution layer 130 located above the bottom of the opening 120, and the interface between the void 152 and the single-layer passivation sheath 150A has an arched profile. The void 152 can act as a buffer between the single-layer passivation sheath 150A and the redistribution layer 130 to reduce unnecessary stress caused by the mismatch of the coefficients of thermal expansion between the single-layer passivation sheath 150A and the redistribution layer 130. Furthermore, when the external temperature or pressure changes drastically, it can also prevent the single-layer passivation sheath 150A from excessively stretching the redistribution layer 130, thereby preventing the redistribution layer 130 near the conductive pad 102B from peeling or breaking.

[0026] Referring to Figure 1I, in some embodiments, after forming the passivation sheath structure (i.e., a single passivation sheath 150A), a metal layer 160 is formed in each opening within the single passivation sheath 150A and extends over the single passivation sheath 150A. For example, each metal layer 160 extends through the openings through the single passivation sheath 150A and is electrically connected to the redistribution layer 130 located above the back surface 100B of the substrate 100W. The metal layer 160 serves as a conductive connector for electrically connecting to external circuitry. The metal layer 160 may have a multilayer structure. For simplicity, only a single layer is shown here. In some embodiments, the metal layer 160 is a metal stack composed of copper, nickel, and gold layers.

[0027] Referring to Figure 1J, in some embodiments, after forming the metal layer 160, the carrier substrate 116 is stripped and the stop layer 108 and passivation sheath structure (i.e., a single-layer passivation sheath 150A) are cut along the dicing path SL to form a monolithic wafer package 10A, as shown in Figure 2. In some embodiments, when the adhesive layer 112 and / or the tape layer 114 are made of a photothermal conversion (LTHC) material, a de-bonding process is performed by irradiating the adhesive layer 112 with laser light or ultraviolet light. Due to the heat generated by the laser light or ultraviolet light, the photothermal conversion (LTHC) material decomposes, and thus the carrier substrate 116 is removed from the structure including the substrate 100W.

[0028] Referring again to Figure 2, in some embodiments, the monolithic wafer package 10A includes a device substrate 100 cut from the substrate 100W and corresponding to the wafer region C, a metallization layer 102, a redistribution layer 130, a single-layer passivation sheath 150A (passivation sheath structure), and a stop layer 108. The metallization layer 102 and the redistribution layer 130 are respectively disposed on the front surface 100A and the back surface 100B of the device substrate 100. The single-layer passivation sheath 150A covers the edge surface 100E surrounding the device substrate 100 and extends to the back surface 100B, covering the redistribution layer 130. The stop layer 108 remaining in the metallization layer 102 is aligned with the single-layer passivation sheath 150A covering the edge surface 100E, so as to surround the device substrate 100 and directly contact the single-layer passivation sheath 150A.

[0029] In some embodiments, an opening 120 in the device substrate 100 extends from its back surface 100B to its front surface 100A, and a redistribution layer 130 extends into the corresponding opening 120 and is electrically connected to the corresponding conductive pad 102B located in the metallization layer 102. Furthermore, a single-layer passivation sheath 150A also extends into the opening 120 to block the opening 120, and a void 152 is formed between the single-layer passivation sheath 150A in the opening 120 and the redistribution layer 130 in the opening 120.

[0030] In some embodiments, in the monolithic wafer package 10A, an insulating liner 122 is disposed between the device substrate 100 and the redistribution layer 130, while a metal layer 160 passes through a single passivation sheath 150A to electrically connect to the redistribution layer 130.

[0031] In some embodiments, the monolithic wafer package 10A also includes an optical component 104 located outside the wafer package 10A, which is disposed on the metallization layer 102 and corresponds to the sensing device 100S within the device substrate 100.

[0032] Figures 3A to 3E are schematic cross-sectional views illustrating a method of manufacturing a wafer package according to some embodiments, wherein components identical to those in Figures 1A to 1J are referred to by the same reference numerals and their descriptions may be omitted. Referring to Figure 3A, in some embodiments, a structure as shown in Figure 1G is provided.

[0033] Referring then to Figures 3B to 3C, in some embodiments, a passivation sheath structure is formed on the back surface 100B of the substrate 100W. The passivation sheath structure covers the redistribution layer 130 and extends into the openings 120 and 140. In some embodiments, the passivation sheath structure has a multilayer structure. For example, the passivation sheath structure is composed of a first passivation sheath 151A and a second passivation sheath 151B. As shown in Figure 3B, in some embodiments, a first passivation sheath 151A is formed to cover the redistribution layer 130 above the back surface 100B of the substrate 100W. Similar to the single-layer passivation sheath 150A shown in Figure 1H, the first passivation sheath 151A plugs but does not completely fill the opening 120. For example, a hole 152 is formed between the first passivation sheath 151A located within the opening 120 and the redistribution layer 130 located above the bottom of the opening 120, and the interface between the hole 152 and the first passivation sheath 151A has an arched profile. Furthermore, unlike the single-layer passivation sheath 150A shown in Figure 1H, the first passivation sheath 151A does not fill the opening 140, leaving the opening 140 exposed above the first passivation sheath 151A.

[0034] Subsequently, the first passivation sheath 151A is patterned, forming multiple openings within the patterned first passivation sheath 151A to expose the redistribution layer 130 beneath it. The portion of the redistribution layer 130 exposed through the openings serves as a pad area for electrically connecting to an external circuit (not shown). The material and forming method of the first passivation sheath 151A may be similar to or the same as the material and forming method of the single-layer passivation sheath 150A.

[0035] As shown in Figure 3C, in some embodiments, a second passivation layer 151B is formed to cover the first passivation layer 151A and fill the exposed opening 140. Then, the first passivation layer 151A is patterned similarly. The second passivation layer 151B is also patterned such that a plurality of openings are formed within the patterned second passivation layer 151B, aligning with the openings in the first passivation layer 151A to expose the redistribution layer 130. The second passivation layer 151B may be made of an organic polymer material different from the first passivation layer 151A. For example, green paint or similar materials. Since green paint has better light-shielding properties than the organic polymer material constituting the first passivation layer 151A, it can serve as a light-shielding layer covering the edge surface of the substrate, blocking or absorbing light passing through the substrate of the sensing chip, thereby preventing or improving the problem of optical crosstalk.

[0036] Referring to Figure 3D, in some embodiments, after forming the passivation sheath structure (including the first passivation sheath 151A and the second passivation sheath 151B), a metal layer 160 is formed in each opening within the first passivation sheath 151A and the second passivation sheath 151B and extends over the second passivation sheath 151B. The metal layer 160 is electrically connected through the openings to the redistribution layer 130 located above the back surface 100B of the substrate 100W.

[0037] Referring to Figure 3E, in some embodiments, after the metal layer 160 is formed, the carrier substrate 116 is stripped and the stop layer 108 and the second passivation layer 151B are cut along the dicing path SL to form a monolithic wafer package 10B, as shown in Figure 4.

[0038] Referring again to Figure 4, in some embodiments, the monolithic wafer package 10B includes a device substrate 100 cut from the substrate 100W and corresponding to the wafer region C, a metallization layer 102, a redistribution layer 130, a passivation sheath structure (including a first passivation sheath 151A and a second passivation sheath 151B), and a stop layer 108. The metallization layer 102 and the redistribution layer 130 are respectively disposed on the front surface 100A and the back surface 100B of the device substrate 100. The second passivation sheath 151B covers the edge surface 100E surrounding the device substrate 100 and extends to the back surface 100B, covering the first passivation sheath 151A and the redistribution layer 130. The stop layer 108 remaining in the metallization layer 102 is aligned with the second passivation sheath 151B covering the edge surface 100E, so as to surround the device substrate 100 and directly contact the second passivation sheath 151B.

[0039] In some embodiments, the first passivation layer 151A extends into the opening 120 and plugs the opening 120, and a hole 152 is formed between the first passivation layer 151A in the opening 120 and the redistribution layer 130 in the opening 120.

[0040] Figures 5A to 5H illustrate cross-sectional schematic diagrams of a method for manufacturing a wafer package according to some embodiments, wherein components identical to those in Figures 1A to 1J are referred to by the same reference numerals and their descriptions may be omitted. Referring to Figure 5A, in some embodiments, a structure as shown in Figure 1D is provided. Subsequently, a thinning process (e.g., etching, milling, grinding, or polishing) is performed on the back surface 100B of the substrate 100W' to reduce the thickness of the substrate 100W'. After the thinning process, the thickness of the substrate 100W' is thinner than the thickness of the substrate 100W shown in Figure 1D.

[0041] Referring to Figure 5B, in some embodiments, after a thinning process, one or more openings are formed within the substrate 100W' extending from the back surface 100B to the front surface 100A. For example, one or more openings 120' are formed within the substrate 100W' of each wafer region C. The openings 120' penetrate the substrate 100W' and extend into the metallization layer 102 to expose the conductive pads 102B. Next, an insulating liner 122 (or electrical isolation layer) is compliantly formed on the back surface 100B of the substrate 100W'. The insulating liner 122 is also compliantly deposited on the sidewall surfaces of the openings 120'. Subsequently, a patterned redistribution layer (RDL) 130 is formed on the insulating liner 122 above the back surface 100B of the substrate 100W'. The redistribution layer 130 also extends compliantly to the sidewall surface and bottom surface of the opening 120', and is directly or indirectly electrically connected to the exposed conductive pad 102B via the opening 120'.

[0042] In some embodiments, after the redistribution layer 130 is formed, one or more conductive pillars 132A are formed on the corresponding redistribution layer 130. The conductive pillars 132A may be made of metal, such as copper or similar metals, and may be formed by an electroplating process.

[0043] Referring to Figure 5C, in some embodiments, a molding material layer 142 is formed to cover the back surface 100B of the substrate 100W' and the redistribution layer 130, and to surround each conductive pillar 132A. Furthermore, the molding material layer 142 also fills the opening 120'.

[0044] In some embodiments, the height of the molding material layer 142 is greater than the height of the conductive pillar 132A, so that the upper surface of the conductive pillar 132A is covered by the molding material layer 142. The molding material layer 142 can provide structural support for the thinner substrate 100W', thereby compensating for the lack of rigidity of the substrate 100W'.

[0045] Referring to Figure 5D, in some embodiments, the upper surface of the molding material layer 142 is thinned (e.g., etched, milled, ground, or polished) until the upper surface of the conductive pillar 132A is exposed. Subsequently, in some embodiments, one or more conductive layers 132B are formed on the molding material layer 142 and connected to the corresponding conductive pillar 132A to form another redistribution layer 135 (or redistribution structure) with the corresponding conductive pillar 132A. The material and formation method of the conductive layers 132B may be similar to or the same as those of the redistribution layer 130.

[0046] Referring to Figure 5E, in some embodiments, an opening 140B is sequentially formed within the molding material layer 142 and an opening 140A is sequentially formed within the substrate 100W'. Openings 140A and 140B are aligned with the dicing channel region SL to surround the wafer region C and expose the stop layer 108 located within the metallization layer. In some embodiments, a sawing process may be performed along the dicing channel region SL to sequentially form openings 140B and 140A. In some embodiments, opening 140A penetrates the substrate 100W' and partially extends within the stop layer 108. For example, it extends to half the thickness of the stop layer 108. In other embodiments, opening 140A penetrates the substrate 100W' but does not extend into the stop layer 108.

[0047] Referring to Figure 5F, in some embodiments, a passivation sheath structure is formed on the back surface 100B of the substrate 100W'. The passivation sheath structure covers the redistribution layer 130 and extends into the openings 140B and 140A. In some embodiments, the passivation sheath structure has a single-layer structure. For example, the passivation sheath structure is composed of a single-layer passivation sheath 150B. The single-layer passivation sheath 150B is then patterned so that a plurality of openings are formed within the patterned single-layer passivation sheath 150B to expose the redistribution layer 130 underneath. The portion of the redistribution layer 130 exposed through the openings serves as a pad area for electrically connecting to an external circuit (not shown). As shown in Figure 5F, the single-layer passivation sheath 150B completely fills the openings 140B and 140A. The material and formation method of the single-layer passivation coating 150B may be similar to or the same as the second passivation coating 151B shown in Figure 3C.

[0048] Referring to Figure 5G, in some embodiments, after forming the passivation sheath structure (i.e., a single passivation sheath 150B), a metal layer 160 is formed in each opening within the single passivation sheath 150B and extends over the single passivation sheath 150B. For example, each metal layer 160 extends through the openings through the single passivation sheath 150B and is electrically connected to the conductor layer 132B of the redistribution layer 135 located above the molding material layer 142. The metal layer 160 serves as a conductive connector for electrically connecting to external circuitry.

[0049] Referring to Figure 5H, in some embodiments, after forming the metal layer 160, the carrier substrate 116 is stripped and the stop layer 108 and passivation sheath structure (i.e., single passivation sheath 150B) are cut along the dicing zone SL to form a monolithic wafer package 10C, as shown in Figure 6.

[0050] Referring again to Figure 6, in some embodiments, the monolithic wafer package 10C includes a device substrate 100' cut from a substrate 100W' and corresponding to the wafer region C, a metallization layer 102, redistribution layers 130 and 135, a molding material layer 142, a single-layer passivation sheath 150B (passivation sheath structure), and a stop layer 108. The metallization layer 102 and the redistribution layer 130 are respectively disposed on the front surface 100A and the back surface 100B of the device substrate 100'. The single-layer passivation sheath 150B covers the edge surface 100E surrounding the device substrate 100' and the edge surface 142E of the molding material layer 142, and extends to the molding material layer 142 and covers the conductor layer 132B of the redistribution layer 135. The stop layer 108 remaining in the metallization layer 102 is aligned with the single passivation layer 150B covering the edge surfaces 100E and 142E, so as to surround the device substrate 100' and the molding material layer 142, and to be in direct contact with the single passivation layer 150B.

[0051] In some embodiments, an opening 120' within the device substrate 100' extends from its back surface 100B to its front surface 100A, and a redistribution layer 130 extends within the corresponding opening 120' and is electrically connected to the corresponding conductive pad 102B located within the metallization layer 102. Furthermore, the conductor layer 132B above the molding material layer 142 is electrically connected to the corresponding redistribution layer 130 through corresponding conductive pillars 132A.

[0052] In some embodiments, in the monolithic wafer package 10C, an insulating liner 122 is disposed between the device substrate and the redistribution layer 130, while a metal layer 160 passes through a single passivation sheath 150B to electrically connect the conductor layer 132B.

[0053] In some embodiments, the monolithic wafer package 10C also includes an optical component 104 located outside the wafer package 10C, which is disposed on the metallization layer 102 and corresponds to the sensing device 100S within the device substrate 100'.

[0054] Please refer to Figure 7, which shows a cross-sectional schematic diagram of a wafer package according to some embodiments, wherein the same components as in Figure 4 are referred to by the same reference numerals and their descriptions may be omitted. In some embodiments, the structure of the wafer package 10D is similar to that of the wafer package 10B in Figure 4, and therefore the method of forming the wafer package 10D is also similar to the method of forming the wafer package 10B (as shown in Figures 3A to 3E).

[0055] The second passivation layer 151B in the wafer package 10B covers the first passivation layer 151A and the redistribution layer 130, and the metal layer 160 in the wafer package 10B is formed in each opening in the first passivation layer 151A and the second passivation layer 151B, and extends above the second passivation layer 151B. Unlike the second passivation layer 151B and the metal layer 160 in the wafer package 10B, the second passivation layer 151B in the wafer package 10D is formed after the metal layer 160 is formed.

[0056] As shown in Figure 7, in some embodiments, a metal layer 160 is formed within each opening in the first passivation liner 151A and extends partially over the first passivation liner 151A. A second passivation liner 151B covers the edge surface 100E surrounding the device substrate 100 and extends to the back surface 100B to cover the first passivation liner 151A and the edge portions of each metal layer 160 (i.e., the portion of the metal layer 160 that partially extends beyond the first passivation liner 151A). In other words, the metal layer 160 extends partially between the first passivation liner 151A and the second passivation liner 151B. Each metal layer 160 not covered by or exposed to the second passivation liner 151B is connected to a conductive connection structure 180 (e.g., solder ball, bump, or conductive post) to electrically connect to the corresponding redistribution layer 130.

[0057] Please refer to Figure 8, which is a cross-sectional schematic diagram of a wafer package 10E according to some embodiments, wherein components identical to those in Figure 6 are referred to by the same reference numerals and their descriptions may be omitted. In some embodiments, the structure of the wafer package 10E is similar to that of the wafer package 10C in Figure 6, and therefore the method of forming the wafer package 10E is also similar to the method of forming the wafer package 10C (as shown in Figures 5A to 5H).

[0058] Unlike the wafer package 10C shown in Figure 6, the wafer package 10E includes a monolithized device substrate 100' stacked on a molding material layer 142. A device substrate 200 is formed within the molding material layer 142 and has an active surface 200B and a back surface 200A opposite to the active surface 200B. The back surface 200A of the device substrate 200 is bonded to the back surface 100B of the device substrate 100' through an adhesive layer 202, as shown in Figure 8. For example, the adhesive layer 202 may be a die attach film. The device substrate 200 also includes an insulating layer 201 and one or more pads 203 disposed on the active surface 200B of the device substrate 200. In some embodiments, the insulating layer 201 includes an interlayer dielectric (ILD) layer, an intermetallic dielectric (IMD) layer, a passivation sheath, or a combination thereof. Furthermore, pad 203 is formed within insulating layer 201, and the upper surface of pad 203 is exposed outside insulating layer 201 to serve as input / output (I / O) pad.

[0059] In some embodiments, the wafer package 10E further includes conductive pillars 132A and 132C formed within the molding material layer 142. The conductive pillar 132A extends between the redistribution layer 130 and the conductor layer 132B, while the conductive pillar 132C extends between the pad 203 of the device substrate 200 and the conductive line layer 132B.

[0060] According to the above embodiments, the edge surface of the device substrate within the wafer package is covered by a passivation sheath structure, thus preventing warping or deformation due to insufficient rigidity of the wafer itself, thereby reducing the difficulty of wafer packaging. Furthermore, according to the above embodiments, in a wafer package with a thinner device substrate design, the structural strength of the wafer can be improved by additionally providing a molding material layer on the back surface of the device substrate and covering the edge surface of the device substrate with a passivation sheath structure. Additionally, the passivation sheath structure may include an organic polymer material with better light-shielding properties, thus serving as a light-shielding layer covering the edge surface of the substrate to prevent or improve the problem of optical crosstalk.

[0061] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can modify and combine the above-described embodiments without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figures 1A to 1J illustrate cross-sectional schematic diagrams of a method for manufacturing a chip package according to some embodiments. Figure 2 illustrates cross-sectional schematic diagrams of a chip package according to some embodiments. Figures 3A to 3E illustrate cross-sectional schematic diagrams of a method for manufacturing a chip package according to some embodiments. Figure 4 illustrates cross-sectional schematic diagrams of a chip package according to some embodiments. Figures 5A to 5H illustrate cross-sectional schematic diagrams of a method for manufacturing a chip package according to some embodiments. Figure 6 illustrates cross-sectional schematic diagrams of a chip package according to some embodiments. Figure 7 illustrates cross-sectional schematic diagrams of a chip package according to some embodiments. Figure 8 illustrates cross-sectional schematic diagrams of a chip package according to some embodiments.

Claims

1. A chip package, comprising: A device substrate having an edge surface surrounding the device substrate; A metallization layer is disposed on a front surface of the device substrate; A first super-wiring layer is disposed on a back surface of the device substrate and extends into the device substrate; a passivation sheath structure surrounds and covers the edge surface of the device substrate and extends to the back surface and covers the first super-wiring layer. And a stop layer, disposed within the metallization layer and aligned with the passivation sheath structure covering the edge surface and surrounding the device substrate.

2. The chip package as described in claim 1 further includes: An electrical isolation layer is disposed between the device substrate and the first rewiring layer.

3. The chip package as described in claim 1, further comprising: A metal layer passes through the passivation sheath structure to electrically connect the first rewiring layer.

4. The wafer package of claim 1, wherein the device substrate has an opening extending from the back surface of the device substrate to the front surface, the first redistribution layer extending into the opening and electrically connected to a conductive pad located within the metallization layer.

5. The wafer package of claim 4, wherein the passivation sheath structure extends into the opening and plugs the opening, and wherein the passivation sheath structure is made of a single layer of organic polymer material.

6. The wafer package as claimed in claim 4, wherein the passivation sheath structure includes: A first passivation layer covers the first redistribution layer above the back surface of the device substrate and extends into the opening to plug it; and a second passivation layer covers the first passivation layer and is in direct contact with the edge surface of the device substrate.

7. The chip package as described in claim 6 further includes: A metal layer extends through the first passivation layer and partially extends between the first passivation layer and the second passivation layer, wherein the metal layer is electrically connected to the first redistribution layer.

8. The chip package as described in claim 1 further includes: A molding material layer having a first surface covering the first rewiring layer above the back side surface of the device substrate; And a second wiring layer disposed on a second surface of the molding material layer opposite to the first surface and extending within the molding material layer to electrically connect the first wiring layer.

9. The chip package as described in claim 8 further includes: A second device substrate is disposed within the molding material layer, wherein the second device substrate has a back surface that covers the first rewiring layer and is bonded to the back surface of the device substrate, and an active surface that is electrically connected to the second rewiring layer.

10. The wafer package as claimed in claim 9, wherein the second rewiring layer includes: A conductive wire portion is located on the second surface of the molding material layer; a first conductive pillar portion is located within the molding material layer and connected to the conductive wire portion and the first redistribution layer; and a second conductive pillar portion is located within the molding material layer and connected to the conductive wire portion and the active surface of the second device substrate.

11. The wafer package of claim 8, wherein the passivation sheath structure surrounds and covers an edge surface of the molding material layer, extends to the second surface and covers the second redistribution layer, and wherein the passivation sheath structure is made of a single layer of organic polymer material.

12. The chip package as described in claim 8 further includes: A metal layer passes through the passivation sheath structure to electrically connect the second wiring layer.

13. The wafer package of claim 8, wherein the second wiring layer includes: A conductive section is located on the second surface of the molding material layer; And a conductive pillar portion, located within the molding material layer, and connected to the wire portion and the first rewiring layer.

14. The wafer package of claim 8, wherein the device substrate has an opening extending from the back surface of the device substrate to the front surface; wherein the first rewiring layer extends into the opening and is electrically connected to a conductive pad located within the metallization layer; and wherein the molding material layer covers the first rewiring layer above the back surface of the device substrate and extends into the opening to plug the opening.

15. The chip package as described in claim 1 further includes: An optical component is disposed on the metallization layer and corresponds to a sensing device within the device substrate, wherein the optical component is located outside the wafer package.

16. The wafer package of claim 1, wherein the stop layer is in direct contact with the passivation sheath structure covering the edge surface.

17. A method for manufacturing a chip package, comprising: A substrate is provided, the substrate having a wafer region and a dicing region surrounding the wafer region; A metallization layer is formed on a front surface of the substrate, wherein the metallization layer has a first opening aligned with the dicing area and surrounding the wafer region; a stop layer is formed within the first opening; a first redistribution layer is formed on a back surface of the substrate and extends into the substrate; a second opening is formed in the substrate and aligned with the dicing area to surround the wafer region and expose the stop layer; and a passivation sheath structure is formed on the back surface and fills the second opening, wherein the passivation sheath structure covers the first redistribution layer.

18. The method for manufacturing a wafer package as described in claim 17 further includes: Before forming the first rewiring layer, an electrical isolation layer is formed on the back surface of the substrate and extends into the substrate, thereby separating the substrate from the first rewiring layer.

19. The method for manufacturing a wafer package as described in claim 17 further includes: A metal layer is formed on the passivation sheath structure and extends through the passivation sheath structure to electrically connect the first redistribution layer. And cut the stop layer and the passivation protective layer structure along the cutting channel area.

20. The method for manufacturing a chip package as described in claim 17 further includes: Before forming the first overlay layer, a third opening is formed in the substrate, allowing the first overlay layer to extend into the substrate through the third opening.

21. The method of manufacturing a wafer package as claimed in claim 20, wherein the passivation layer structure extends into the third opening to plug the third opening, and wherein the passivation layer structure is made of a single layer of organic polymer material.

22. The method of manufacturing a wafer package as claimed in claim 20, wherein forming the passivation sheath structure includes: A first passivation sheath is formed to cover the first redistribution layer above the back surface of the substrate and to plug the third opening, wherein the first passivation sheath exposes the second opening; and a second passivation sheath is formed to cover the first passivation sheath and fill the exposed second opening.

23. The method for manufacturing a wafer package as described in claim 17 further includes: Before forming the second opening, a conductive pillar is formed on the first rewiring layer; A molding material layer is formed to cover the back surface of the substrate and the first rewiring layer, and to surround the conductive pillar; and a conductor layer is formed on the molding material layer and connected to the conductive pillar to form a second rewiring layer with the conductive pillar.

24. The method for manufacturing a chip package as described in claim 23 further includes: Before forming the second opening, a third opening is formed within the molding material layer and aligned with the dicing area to surround the wafer area, wherein the formed passivation sheath structure covers the second redistribution layer and fills the third opening.

25. The method of manufacturing a wafer package as claimed in claim 24, wherein the passivation sheath structure is made of a single layer of organic polymer material.

26. The method for manufacturing a chip package as described in claim 24 further includes: A metal layer is formed through the passivation sheath structure to electrically connect the second wiring layer.

27. The method for manufacturing a chip package as described in claim 23 further includes: Before the first rewiring layer is formed, a third opening is formed in the substrate, through which the first rewiring layer extends into the substrate, wherein the molding material layer covers the first rewiring layer above the back surface of the substrate and plugs the third opening.

28. A method of manufacturing a wafer package as claimed in claim 17, wherein the stop layer directly contacts the passivation sheath structure located within the second opening.

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