Semiconductor device including cells with varying cell heights and method of manufacturing the same

Abstract

A device includes multiple cells, multiple active regions, multiple gate regions, multiple source and drain electrodes, and multiple power rails. The multiple cells include one or more taller cells, one or more shorter cells, and one or more half-height (OHH) cells. The shorter cells have a smaller cell height than the taller cells. The OHH cells have a larger cell height than the taller cells. An active region is formed in each cell. A gate region extends across the active region. Source and drain electrodes are formed in the active regions opposite the gate regions. The power rails include first and second power rails, defining the top and bottom boundaries of the cell, respectively. A method of manufacturing the device is also disclosed.

Claims

1. A semiconductor device, comprising: A plurality of cells are arranged in an array of columns and rows, wherein the plurality of cells include: one or more taller cells; one or more shorter cells having a smaller cell height than the taller cells; and one or more half-height (OHH) cells having a larger cell height than the taller cells; a plurality of active regions formed in each cell, wherein the active regions include a first conductivity type and a second conductivity type opposite to the first conductivity type; a plurality of gate regions, each gate region extending across the active regions; a plurality of source and drain electrodes formed in the active regions, located on opposite sides of the gate regions; and a plurality of power rails, including a first power rail and a second power rail, defining the top boundary and bottom boundary of a cell, respectively, wherein the cell height of the OHH cell is substantially equal to the cell height of the taller cells plus half the cell height of the shorter cells.

2. The semiconductor device as claimed in claim 1, wherein: The taller cells are located in the first column; the shorter cells are located in the second column; and the OHH cells span the first and second columns, wherein the OHH cells have a top edge aligned with the top edge of the taller cells and a bottom edge aligned with the center of the shorter cells.

3. The semiconductor device as claimed in claim 1, wherein: A tall cell is located in the first column; a short cell is located in the second column; and an OHH cell is located in the first column and the second column, wherein the OHH cell has a bottom edge aligned with the bottom edge of the short cell and a top edge aligned with the center of the tall cell.

4. The semiconductor device of claim 1 further includes one or more average height cells having an average cell height greater than the cell height of the shorter cell and less than the cell height of the taller cell.

5. The semiconductor device as claimed in claim 1, wherein: A first average height cell located in a first column; a second average height cell located in a second column; and an OHH cell spanning the first column and the second column, wherein the OHH cell has a top edge aligned with the top edge of the first average height cell and a bottom edge aligned with the center of the second average height cell.

6. A semiconductor device, comprising: A plurality of cells arranged in an array of columns and rows, wherein the plurality of cells includes: one or more average height cells; a plurality of unit cells including: a taller cell having a cell height greater than the average height cell; a shorter cell having a cell height smaller than the average height cell; and one or more half-height (OHH) cells having a cell height greater than the taller cell; a plurality of active regions formed in each cell, wherein the active regions include a first conductivity type and a second conductivity type opposite to the first conductivity type; a plurality of gate regions, each gate region extending across the active regions; a plurality of source and drain electrodes formed in the active regions, located on opposite sides of the gate regions; and a plurality of power rails, including a first power rail and a second power rail, defining the top boundary and bottom boundary of a cell, respectively, wherein the cell height of the OHH cell is substantially equal to the cell height of the taller cell plus half the cell height of the shorter cell.

7. The semiconductor device as claimed in claim 6, wherein: The taller cell is located in the first column; the shorter cell is located in the second column; and the OHH cell spans the first column and the second column, wherein the OHH cell has a top edge aligned with the top edge of the taller cell and a bottom edge aligned with the center of the shorter cell.

8. A method for manufacturing a semiconductor device, comprising: Fabricating a plurality of cells on a semiconductor substrate, arranged in an array of columns and rows, wherein fabricating the plurality of cells includes: fabricating a pair of first power rails defining a higher cell; fabricating a pair of second power rails defining a lower cell, wherein the lower cell has a smaller cell height than the higher cell; fabricating a pair of third power rails defining a half-height (OHH) cell, wherein the cell height of the OHH cell is substantially equal to the sum of the cell height of one of the higher cell and the lower cell and half the cell height of the other of the higher cell and the lower cell; patterning one or more active regions in each cell; forming a gate structure on the active regions; and doping the active regions to form source and drain regions on opposite sides of the gate structure.

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