Semiconductor wafer of monocrystalline silicon

Abstract

A single-crystal silicon semiconductor wafer having a front side and a back side comprises: an annular edge region at the outer edge of the wafer; and a region with a constant axial thickness disposed within the annular edge region; the region with a constant axial thickness includes a near-surface region on the front side, a near-surface region on the back side, and an internal region disposed between the near-surface regions; the near-surface region on the front side extends axially downward from the surface of the front side to a depth of not less than 50 micrometers; the interstitial oxygen concentration of the entire internal region is 5.2 × 10¹⁷ to 5.8 × 10¹⁷ atoms / cubic centimeter, with a radial variation of not more than 0.2 × 10¹⁷ atoms / cubic centimeter; and the nitrogen concentration of the near-surface region on the front side decreases axially from the surface to the interior of the wafer, and is 1.0 × 10¹⁴ to 1.7 × 10¹⁵ atoms / cubic centimeter at a depth of 5 micrometers from the surface.

Description

Technical Field

[0001] The subject of this invention is a single-crystal silicon semiconductor wafer. Prior Technology

[0002] For certain electronic components, single-crystal silicon semiconductor wafers, possessing exceptionally high mechanical stability, are essential starting materials. For example, the production of BCD-type (BIPOLAR-CMOS-DMOS) devices requires single-crystal silicon semiconductor wafers as the base material, characterized by high mechanical robustness, especially during processing steps that must be performed at relatively high temperatures for extended periods. Furthermore, such wafers need to exhibit a denuded zone (DZ) of desired depth and an interior region bordering the DZ, characterized by the potential to develop seeds with high peak density of bulk microdefects (BMDs). A denuded zone is understood as a region within the semiconductor wafer's lattice free of BMDs, and one in which BMDs cannot be generated by thermal processing.

[0003] The term "rapid thermal annealing" (RTA) describes a thermal process in which a semiconductor wafer is brought to a relatively high temperature relatively quickly, held at that temperature for a relatively short time, and then cooled relatively quickly. US 20030029859 A1 describes an apparatus suitable for performing RTA. During RTA, the semiconductor wafer in the apparatus is situated on a ring and is rotated and exposed to thermal radiation from above.

[0004] RTA processing under argon at holding temperatures above 1300°C produces relatively flat DZs with a depth of several micrometers because oxygen diffuses out near the surface under these conditions. US 20120001301 A1 describes such an RTA process, and the loss of oxygen leads to a weakening of the mechanical robustness of the semiconductor wafer. To enhance the mechanical robustness of the semiconductor wafer and promote the formation of BMDs within it, the semiconductor wafer can be, for example, doped with nitrogen.

[0005] To manufacture semiconductor wafers, when pulling single crystals using the Czochralski process, it is crucial to ensure that the ratio of the pulling speed *v* to the axial temperature gradient *G* at the phase boundary between the single crystal and the melt is adjusted. This allows the crystal lattice to exhibit certain properties related to point defects (such as interstitial silicon atoms and vacancies). A drawback of nitrogen doping during single crystal pulling is that the relatively high nitrogen concentration promotes the formation of OSF defects (oxygen-induced stacking faults).

[0006] It is also known that RTA processing in argon and ammonia atmospheres, followed by RTA processing in argon atmosphere, leaves a relatively deep DZ (T. Müller et al., "Near-Surface Defect Control by Vacancy Injecting / Out-Diffusing Rapid Thermal Annealing", Phys. Status Solidi A, 2019, 1900325). EP 4151782 B1 describes a method for manufacturing a single-crystal silicon semiconductor wafer having a front and back side composed of N regions containing an interstitial oxygen concentration of not less than 5.3 × 10¹⁷ atoms / cubic centimeter and not more than 5.9 × 10¹⁷ atoms / cubic centimeter; and a nitrogen concentration of not less than 2.0 × 10¹⁵ atoms / cubic centimeter that enters the semiconductor wafer from the front and back sides and decreases at a depth of 50 micrometers from the front side. The method of EP 4151782 B1 includes first, second, and third RTA processes. Summary of the Invention

[0007] Further improvements to the mechanical robustness of this single-crystal silicon semiconductor wafer, without being hindered by OSF defects, are particularly necessary for the production of BCD-type devices.

[0008] Therefore, one object of the present invention is to provide a single-crystal silicon semiconductor wafer that exhibits increased mechanical robustness compared to prior art without being hindered by OSF defects. It is also desirable that the semiconductor wafer exhibits the smallest possible edge exclusion to improve the efficiency of component manufacturing. This object is achieved by the single-crystal silicon semiconductor wafer according to the present invention.

[0009] The single-crystal silicon semiconductor wafer of the present invention, having a front side and a back side, is composed of the following: In the annular edge region at the outer edge of the wafer, the thickness of the wafer tapers in a radially outward direction; and A region with a constant axial thickness, consisting of N regions, is arranged within the annular edge region; The region with a constant axial thickness includes a near-surface region on the front side, a near-surface region on the back side, and an inner region disposed between these near-surface regions; and The near-surface region of the front extends axially downward from the surface of the front to a depth of not less than 50 micrometers; in The interstitial oxygen concentration throughout the entire internal region is no less than 5.2 × 10¹⁷ atoms / cm³ and no more than 5.8 × 10¹⁷ atoms / cm³, with a radial variation of no more than 0.2 × 10¹⁷ atoms / cm³; and The nitrogen concentration in the near-surface region on the front side decreases axially from the surface to the interior of the semiconductor wafer, and at a depth of 5 micrometers from the surface, it is not less than 1.0 × 10¹⁴ atoms / cubic centimeter and not more than 1.7 × 10¹⁵ atoms / cubic centimeter. Simple Explanation of the Diagram

[0010] Figure 1 shows the interstitial oxygen concentration determined by LT-FTIR in a single-crystal silicon wafer produced in the working embodiment, which is a function of radial position in a region at a distance of not less than 140 mm and not more than 151 mm from the axis of rotation in the radial direction.

[0011] Figure 2 shows a graph of mechanical stress in the semiconductor wafer of the present invention. The mechanical stress was determined by SIRD.

[0012] Figure 3 shows the interstitial oxygen concentration in a semiconductor wafer produced in the comparative example, measured by LT-FTIR as a function of radial position in a region at a distance of not less than 140 mm and not more than 151 mm from the axis of rotation in the radial direction.

[0013] Figure 4 shows a graph of mechanical stress in the semiconductor wafers produced in the comparative example. The mechanical stress was determined by SIRD. Implementation

[0014] The single-crystal silicon semiconductor wafer of the present invention may have a diameter of not less than 200 mm and not more than 450 mm, and preferably not less than 300 mm and not more than 310 mm, more preferably not less than 301 mm and not more than 305 mm. The semiconductor wafer of the present invention preferably has a thickness of not less than 500 micrometers and not more than 1500 micrometers, more preferably not less than 700 micrometers and not more than 1000 micrometers.

[0015] The semiconductor wafer of the present invention includes an annular edge region at the outer edge of the wafer, wherein the thickness of the wafer gradually decreases in a radially outward direction. Here, the thickness of the wafer refers to the axial range perpendicular to the radial direction, i.e., perpendicular to the main faces on the front and back sides of the wafer. A preferred feature of the edge region at the outer edge of the wafer is that the axial range of the semiconductor wafer continuously decreases in a radially outward direction in this region. Therefore, the annular edge region is a wafer region formed by a circumferential edge profile. The annular edge region preferably has a radial range of not less than 100 micrometers and not more than 600 micrometers, more preferably not less than 150 micrometers and not more than 500 micrometers.

[0016] The semiconductor wafer of the present invention includes a region having a constant axial thickness, which is composed of an N-region disposed within an annular edge region. The region having a constant axial thickness preferably directly borders the annular edge region. Therefore, the region having a constant axial thickness preferably has a cylindrical shape in the radial direction. Here, the axis of rotation of the cylinder coincides with the axis of rotation of the semiconductor wafer. If the semiconductor wafer of the present invention has a diameter of not less than 300 mm and not more than 310 mm, then the region having a constant axial thickness preferably has a radial range of not less than 290 mm and not more than 309 mm, more preferably a radial range of not less than 295 mm and not more than 299 mm. The semiconductor wafer may have a (100) orientation, a (110) orientation, or a (111) orientation, and preferably a (100) orientation.

[0017] The N-region is characterized by the absence of aggregates of interstitial silicon atoms or vacancy aggregates with a diameter greater than 20 nanometers, and preferably, the absence of such aggregates with a diameter greater than 15 nanometers. The concentration of aggregates of interstitial silicon atoms and vacancy aggregates with a diameter not greater than 15 nanometers in the N-region is preferably not greater than 3.0 × 10⁵ / cm³.

[0018] The region with constant axial thickness includes a near-surface region on the front side, a near-surface region on the back side, and an inner region disposed between the near-surface regions. In one embodiment, the region with constant axial thickness consists only of the near-surface region on the front side, the near-surface region on the back side, and the inner region disposed between the near-surface regions.

[0019] The near-surface region of the front side extends axially downward from the surface of the front side to a depth of not less than 50 micrometers, preferably not less than 100 micrometers. Preferably, the near-surface region of the front side extends axially downward from the surface of the front side to a depth of not more than 200 micrometers, preferably not more than 150 micrometers. In one embodiment, the near-surface region of the front side extends axially downward from the surface of the front side to a depth of not less than 50 micrometers and not more than 150 micrometers. In one embodiment, the near-surface region of the back side also extends axially downward from the surface of the back side to a depth of not less than 50 micrometers and not more than 150 micrometers.

[0020] During the fabrication of single crystals using the Tchaikovsky farad, a very large amount of oxygen is introduced at the interstitial sites of the crystal. This oxygen at the interstitial sites is called interstitial oxygen. The interstitial oxygen concentration throughout the entire internal region is not less than 5.2 × 10¹⁷ atoms / cm³ and not more than 5.8 × 10¹⁷ atoms / cm³, preferably not less than 5.3 × 10¹⁷ atoms / cm³ and not more than 5.7 × 10¹⁷ atoms / cm³. The variation in interstitial oxygen concentration throughout the entire internal region is not more than 0.2 × 10¹⁷ atoms / cm³, preferably not more than 0.1 × 10¹⁷ atoms / cm³. Since the interstitial oxygen concentration decreases particularly at the wafer edge, the variation in interstitial oxygen concentration can be determined by measuring the radial concentration distribution of interstitial oxygen at the outer edge of the internal region, i.e., the region bordering the semiconductor wafer. Preferably, the outer edge of the internal region has a ring-shaped region with a radial range of not less than 3 mm.

[0021] Interstitial oxygen concentration can be measured using LT-FTIR. It is preferred to determine interstitial oxygen concentration according to the standard SEMI MF1188-1107. To measure interstitial oxygen concentration at a defined depth within an internal region of a semiconductor wafer, the near-surface region can be removed by etching, or the semiconductor wafer can be fractured, and the measurement can be performed on the cross-sectional profile at the fracture edge.

[0022] The variation in interstitial oxygen concentration in the internal region of a semiconductor wafer is preferably determined by measuring the interstitial oxygen concentration in an annular region with a radial range of not less than 3 mm at a radial distance of not more than 0.5 mm at the outer edge of the internal region, and by forming the difference between the highest and lowest values ​​of the interstitial oxygen concentration measurement.

[0023] After heat treatment, the interstitial oxygen concentration in the entire internal region is preferably not less than 4.40 × 10¹⁷ atoms / cm³. The heat treatment includes (i) a first step in which the semiconductor wafer is exposed to an atmosphere of a mixture of oxygen and nitrogen at a temperature of 800°C, with a volume ratio of O₂:N₂ of 1:10, for a period of 4 hours; and (ii) a second step in which the semiconductor wafer is exposed to an atmosphere of a mixture of oxygen and nitrogen at a temperature of 1000°C, with a volume ratio of O₂:N₂ of 1:10, for a period of 16 hours.

[0024] After the aforementioned heat treatment, the interstitial oxygen concentration in the entire internal region preferably decreases by no more than 1.30 × 10¹⁷ atoms / cm³, and more preferably by no more than 1.00 × 10¹⁷ atoms / cm³. Here, the decrease in interstitial oxygen concentration at a defined location within the internal region corresponds to the difference between the oxygen concentration measured at that location before and after the aforementioned heat treatment.

[0025] The aforementioned two-stage heat treatment corresponds to the heat treatment for developing BMDs described in EP 4151782 B1. Therefore, the interstitial oxygen concentration after the two-stage heat treatment provides information about the oxygen concentration when the BMD has been formed. Excessive oxygen loss due to heat treatment weakens the mechanical robustness of the semiconductor wafer. Therefore, ideally, the interstitial oxygen concentration should not decrease too drastically due to the two-stage heat treatment, and should not decrease below a defined threshold.

[0026] The nitrogen concentration in the near-surface region of the front side decreases axially from the surface to the interior of the semiconductor wafer, and at a depth of 5 micrometers from the surface, is not less than 1.0 × 10¹⁴ atoms / cm³ and not more than 1.7 × 10¹⁵ atoms / cm³, preferably less than 1.5 × 10¹⁵ atoms / cm³. The front side is the side of the semiconductor wafer that is on top during RTA processing. In one embodiment, the nitrogen concentration in the near-surface region of the back side also decreases axially from the surface to the interior of the semiconductor wafer. The nitrogen concentration is preferably measured using LT-FTIR. At the same distance along the axial direction from the respective surfaces, the nitrogen concentration in the near-surface region of the front side is preferably higher than that in the near-surface region of the back side. The nitrogen concentration in the near-surface region of the back side of the semiconductor wafer is preferably not less than 30% and not more than 70% of the nitrogen concentration in the near-surface region of the front side of the semiconductor wafer, at the same distance along the axial direction from each surface. Within the interior, specifically between the near-surface regions of the front and back sides, the nitrogen concentration decreases to a minimum, corresponding to the nitrogen concentration in the single crystal from which the semiconductor wafer originates. In both the near-surface regions of the front and back sides, the nitrogen concentration decreases monotonically from the surface towards the interior of the semiconductor wafer, but not necessarily strictly monotonically. Therefore, once the minimum nitrogen concentration is reached, the nitrogen concentration in the near-surface regions of both the front and back sides remains constant in the radially inward direction.

[0027] The carbon concentration in regions with constant axial thickness is preferably no greater than 5.0 × 10¹⁵ atoms / cm³. During the pulling of single crystal ingots, the carbon concentration can be reduced by decreasing the amount of carbon entering the crucible from the gas flow. This can be achieved, for example, by using a quartz crucible with an increased wall height of at least 58 cm and a diameter of 32 inches, which also allows for a reduction in the development of SD-COP. The carbon concentration is preferably determined by FTIR.

[0028] Following the aforementioned two-stage heat treatment, the semiconductor wafer preferably has (i) a clean zone extending axially from the front surface downwards into the interior of the semiconductor wafer to a depth of not less than 10 micrometers, and (ii) a lower layer region having a BMD density preferably between 1.1 × 10¹⁰ / cm³ and 1.3 × 10¹⁰ / cm³. The clean zone preferably has an axial range or depth of not more than 20 micrometers from the front surface into the interior. The vacancy density of the clean zone is not greater than 1 × 10¹³ vacancy / cm³, preferably not greater than 7 × 10¹² vacancy / cm³, as determined by platinum diffusion and / or DLTS (deep-level transient spectroscopy).

[0029] Semiconductor wafers can be subjected to thermal stress in a deposition reactor used for depositing epitaxial layers to test their mechanical robustness. In such a deposition reactor, the semiconductor wafer is positioned between upper and lower lamp arrays that direct thermal radiation onto the back and front sides of the semiconductor wafer. The test can be designed such that, within a defined annular region with a radial width of 10 mm and a temperature of 1150°C, the semiconductor wafer is heated by 5°C more than the radially inward region of the semiconductor wafer surrounded by this annular region. The semiconductor wafer is then studied using SIRD (Scanning Infrared Depolarization). SIRD utilizes the physical principle that if linearly polarized light is incident through a region under mechanical stress, the polarization direction of the linearly polarized light is altered. Infrared radiation radiated onto the semiconductor wafer is depolarized in lattice regions where thermal stress has damaged the lattice. The greater the damage, the higher the depolarization, measured in depolarization units (DU). On the semiconductor wafer of the present invention, for no more than 2.0% of the studied area, and more preferably, actually for no more than 1.5% of the studied area, the depolarization exceeds the threshold of 30 DU. For semiconductor wafers from the prior art, such as the semiconductor wafer in the working embodiment of EP 4151782 B1, the fraction of the studied area with depolarization exceeding the threshold of 30 DU is greater than 5%.

[0030] The preferred concentration of crystal-originating particles (COPs) with a size no larger than 15 nanometers in semiconductor wafers is no greater than 3.0 × 10⁵ / cm³. COPs with a size no larger than 15 nanometers, such as BMDs, can be detected by IR-LST (infrared light scattering tomography).

[0031] The semiconductor wafer of the present invention preferably has an SD-COP defect density of no more than 1250 / cm². SD-COP is a defect that can be generated during a heat treatment period of at least 2 hours at a temperature exceeding 900°C. SD-COP defects include oxide COP and LPITS with a size of less than 15 nanometers. After etching, SD-COP is preferably measured by optical profilometry or microscopy using a Secco etching fluid (potassium dichromate (K₂Cr₂O₇) in hydrofluoric acid and water). SD-COP can also be detected by the preparation and analysis methods described in US 5,980,720, or by laser scattering tomography. In addition, SD-COP can also be detected as fluid pattern defects (FPD) by Secco etching and optical inspection.

[0032] Secco etching exposes etch pits of a certain size, also known as LPITs (large etch pits). LPITs can be detected, for example, by optical inspection. On the semiconductor wafer of this invention, no LPITs were detected after etching. This indicates the absence of aggregates of interstitial silicon atoms with a diameter greater than 20 nanometers. Preferably, on the semiconductor wafer of this invention, there are no aggregates of interstitial silicon atoms with a diameter greater than 15 nanometers.

[0033] The single-crystal silicon semiconductor wafer of the present invention can be manufactured by employing a method comprising the following steps in sequence: (i) A single crystal ingot with a cylindrical portion is drawn from a silicon melt contained in a crucible using the Tchaikovsky process; wherein The drawing speed for the cylindrical portion should be no less than 0.40 mm / min and no more than 0.60 mm / min. The melt was subjected to a horizontal magnetic field. The crucible is rotated during the pulling of the cylindrical portion of the single crystal; The crucible's rotation direction is switched within a time period of not less than 15 seconds and not more than 30 seconds. The crucible rotation speed ranges from no less than 0.3 rpm and no more than 6.0 rpm, and increases continuously during the drawing of the cylindrical portion; (ii) Remove the at least one semiconductor wafer from the cylindrical portion of the single crystal ingot; (iii) In a first atmosphere of argon and ammonia with a volume ratio of not less than 1:1.5 and not more than 1:0.9, at a target temperature within a first temperature range of not less than 700°C and not more than 1000°C, the semiconductor wafer is subjected to a first RTA process for a time period of not less than 10 seconds and not more than 20 seconds; (iv) In a second atmosphere of argon, at a target temperature within a second temperature range of not less than 1180°C and not more than 1200°C, for a time period of not less than 20 seconds and not more than 30 seconds, a first RTA process is performed on the semiconductor wafer; and (v) In a third atmosphere of argon and ammonia with a volume ratio of not less than 9:10 and not more than 2.75:2, at a target temperature within a third temperature range of not less than 1160°C and not more than 1170°C, the semiconductor wafer is subjected to a third RTA process for a time period of not less than 10 seconds and not more than 20 seconds.

[0034] The process is described in more detail below.

[0035] To fabricate the single-crystal silicon semiconductor wafer of this invention, a single crystal is first pulled using the Tchaikovsky method. During the pulling of the single crystal from the silicon melt contained in a crucible using the Tchaikovsky method, in an atmosphere of argon and hydrogen, the ratio of the pulling speed *v* to the axial temperature gradient *G* at the phase interface between the single crystal and the melt should be adjusted in such a manner that the cylindrical portion of the single crystal consists only of N-regions. During the pulling of the cylindrical portion of the single crystal, the coefficient *v / G* of the pulling speed *v* and the thermal gradient *G* at the interface preferably exhibits three ramps along the pulling axis. The pulling speed *v* is preferably greater than 0.45 mm / min and less than 0.50 mm / min. These conditions can reduce SD-COP defects.

[0036] The melt is subjected to a horizontal magnetic field. During the pulling of the cylindrical portion of the single crystal, the crucible rotates, with the rotation direction switching regularly at periods of not less than 15 seconds and not more than 30 seconds. The rotational speed range is not less than 0.3 rpm and not more than 6.0 rpm. Preferably, during the pulling of the cylindrical portion of the single crystal over a length region ranging from 20-25% to 90-100% of the total ingot length, the speed range continuously increases to 6.0 rpm. This allows for a periodic increase in interface thickness, thereby regulating the oxygen ingress into the melt. The oxygen ingress, in turn, determines the binding of interstitial oxygen into the grown single crystal. This single crystal is not intentionally doped with nitrogen. Therefore, the nitrogen concentration in the cylindrical portion of the single crystal is not greater than 1.0 × 10¹² atoms / cm³. Here, the diameter of the cylindrical portion of the single crystal is in the range of 312 to 315 mm.

[0037] In the subsequent grinding step, the diameter of the cylindrical portion of the single crystal ingot is reduced to 310 mm or less, and the cylindrical portion of the single crystal ingot is sawed, ground, edge-rounded, polished, and chemically cleaned. This yields a wafer with a diameter of not less than 300 mm and not more than 310 mm, preferably not less than 301 mm and not more than 305 mm.

[0038] By means of the above manufacturing method, a semiconductor wafer consisting only of N regions is obtained, wherein the N regions do not contain agglomerates of interstitial silicon atoms or vacancies with a diameter greater than 20 nanometers, preferably greater than 15 nanometers. The N regions preferably include at least one Ni domain and at least one Nv domain, wherein the Ni domain is dominated by interstitial silicon atoms as point defects, and the Nv domain is dominated by vacancies as point defects.

[0039] In order to obtain the semiconductor wafer of the present invention, the polished semiconductor wafer produced in the above process must undergo the following three RTA processes.

[0040] In the first RTA process, the semiconductor wafer is preferably heated to the target temperature in a first temperature range of not less than 700°C and not more than 1000°C, and held at the target temperature for not less than 10 seconds and not more than 20 seconds in a first atmosphere of argon (Ar) and ammonia (NH3) with a volume ratio of not less than 1:1.5 and not more than 1:0.9.

[0041] The second RTA process of the semiconductor wafer is carried out in a second atmosphere of argon, at a temperature within a second temperature range of not less than 1180°C and not more than 1220°C, for a time period of not less than 20 seconds and not more than 30 seconds.

[0042] The third RTA process of the semiconductor wafer is carried out in a third atmosphere of argon and ammonia with a volume ratio of not less than 9:10 and not more than 2.75:2, at a third temperature range of not less than 1160°C and not more than 1170°C, for a time period of not less than 10 seconds and not more than 20 seconds.

[0043] The first and third RTA processes represent steps in which the front side and, to a lesser extent, the back side of the semiconductor wafer are nitrided. Combined with the second RTA process, nitrogen diffuses into the near-surface region of the semiconductor wafer. In this way, up to 2 × 10¹⁵ atoms / cm³ of nitrogen enters the near-surface region of the semiconductor wafer, providing sufficient robustness to the lattice. No nitrogen-induced OSF defects form in the interior regions of the semiconductor wafer because the nitrogen concentration required for such formation is not achieved in these regions.

[0044] For the RTA process, the semiconductor wafer is preferably heated to a temperature of 1200°C at a rate of 60 K / s to 70 K / s, and then heated to a temperature exceeding 1200°C at a rate of 15 K / s to 20 K / s. After the final RTA process, the semiconductor wafer is preferably cooled from the target temperature of the final RTA process at a rate of 30 K / s.

[0045] JP 2015-73049 A demonstrates that thermally induced dislocations can be quantitatively described using SIRD and BFA (bad fraction area) analysis. According to JP 2006-269896 A, the duration and temperature of heat treatment affect the occurrence of thermally induced dislocations. Therefore, the following methods can be used to test the resistance of single-crystal silicon semiconductor wafers to thermally induced dislocations.

[0046] Single-crystal silicon semiconductor wafers exhibit superior resistance to thermally induced dislocations, as tested using the method described below. The method described below for testing resistance to thermally induced dislocations is used to assess whether a wafer is free of thermally induced dislocations (slip). This method comprises the following steps (a) to (c).

[0047] (a) The semiconductor wafers of the present invention can be heat-treated in a vertical furnace, such as equipment from ASM International NV, wherein each semiconductor wafer is situated on three fingers of a boat (e.g., a long-finger boat from manufacturer Ferrotec Materials Technologies Corporation). Thus, during heat treatment, there is contact between the semiconductor wafers and the fingers of the boat.

[0048] In the heat treatment, the semiconductor wafer is heated to a temperature of 1000°C at a rate of 5 K / min, and then heated at a rate of 2 K / min or lower, preferably 0.5 K / min, within a temperature range of 1000°C to 1200°C. It is then held at 1200°C for 10 to 30 minutes, and then cooled to 1000°C at a rate of 2 K / min or lower, and then cooled again below 1000°C at a rate of 10 K / min or lower.

[0049] (b) BFA analysis was performed using a SIRD system from PVA Metrology & Plasma Solutions GmbH, analyzing a circular sub-region with a radius of 40 mm around a stationary point where there is contact between the fingers of the semiconductor wafer and the boat during heat treatment. The shortest distance from the three sub-regions to the edge of the semiconductor wafer was not less than 1 mm and not greater than 33% of the semiconductor wafer diameter, preferably around 10 mm.

[0050] (c) The high-pass filtered depolarization map provided by the SIRD system is evaluated in the sub-regions, for which a threshold depolarization range of ±10 DU (depolarization unit) is defined. In the BFA analysis, depolarization is determined for the cells of the grid actually placed on the depolarization map. This grid preferably consists of square cells with an edge length preferably of 2 mm. The result of the BFA analysis is the percentage bcf (difference cell fraction), which corresponds to the ratio of the number of difference cells outside the threshold range in the three sub-regions to the number of cells in the three sub-regions. Cells not completely located in a sub-region are counted only if the area of ​​affected cells overlapping with the sub-region is at least 50%. If the percentage bcf is less than 1%, the wafer is considered to have no thermally induced dislocations.

[0051] [Detailed Description of Working Examples]

[0052] First, according to the Tchaikovsky method, a silicon single crystal with a (100) orientation was pulled in an atmosphere of argon and hydrogen (hydrogen partial pressure: 25-35 Pa). This was accomplished using a quartz crucible with a wall height greater than 58 cm and a diameter of 32 inches. In this case, the cylindrical portion of the single crystal had a diameter of 313 mm. During the pulling of the cylindrical portion of the single crystal at a period of 25 seconds, the rotation direction of the crucible was switched, and the rotation speed was continuously increased to 6 rpm, exceeding 20% ​​to 25% of the total crystal length. The average rotation speed of the crucible was 0.6 rpm. The coefficient v / G, formed by the pulling speed v and the thermal gradient G at the interface, exhibited three slopes along the pulling axis during the pulling of the cylindrical portion. The cylindrical portion of the single crystal was pulled at a pulling speed of not less than 0.48 mm / min and not more than 0.50 mm / min.

[0053] In the subsequent grinding step, the diameter of the cylindrical portion of the single crystal ingot is reduced. The cylindrical portion of the single crystal ingot is processed to form a polished wafer with a diameter of 301 mm and a thickness of 780 μm, followed by chemical cleaning. Due to the selection of conditions regarding the v / G ratio during the pulling process, the lattice of the semiconductor wafer with a diameter of 301 mm consists only of N-regions, with portions containing Nv and Ni regions. The semiconductor wafer is then subjected to a series of RTA processes.

[0054] In the first RTA process, the semiconductor wafer is held at a temperature within a first temperature range of not less than 700°C and not more than 1000°C for a period of not less than 10 seconds and not more than 20 seconds, during which time it is exposed to a first atmosphere of argon and ammonia in a volume ratio of not less than 1:1.5 and not more than 1:0.9.

[0055] In the second RTA process, the semiconductor wafer is held at a temperature within a second temperature range of not less than 1180°C and not more than 1220°C for a period of not less than 20 seconds and not more than 30 seconds, during which time it is exposed to a second atmosphere of argon.

[0056] In the third RTA process, the semiconductor wafer is held at a temperature within a third temperature range of not less than 1160°C and not more than 1170°C for a period of not less than 10 seconds and not more than 20 seconds, during which time it is exposed to a third atmosphere of argon and ammonia with a volume ratio of not less than 9:10 and not more than 2.75:2.

[0057] The semiconductor wafer is heated to a maximum temperature of 1200°C at a rate of 60 K / s to 70 K / s, and then heated to a temperature exceeding 1200°C at a rate of 15 K / s to 20 K / s. After the final RTA process, the semiconductor wafer is cooled from the target temperature of the final RTA process at a rate of 30 K / s.

[0058] Figure 1 illustrates that the semiconductor wafer thus manufactured exhibits the desired interstitial oxygen concentration on the one hand, and low variation in the desired interstitial oxygen concentration in the annular edge region 147 mm to 150 mm from the rotation axis of the semiconductor wafer on the other hand. This measurement was performed by LT-FTIR. Figure 2 shows the results of mechanical stress testing in a vertical oven from ASM International NV, measured by SIRD. Each semiconductor wafer was placed on three fingers of a boat (long finger boat) from the manufacturer Ferrotec Materials Technologies Corporation. The semiconductor wafer was heated to 1150°C in the edge region with a radial width of 10 mm, which was 5°C more than the central region surrounded by the edge region, resulting in only a small amount of stress in the edge region. In the above method for testing resistance to thermally induced dislocations, a percentage bfc of less than 1% was determined, and therefore the wafer was considered to have no thermally induced dislocations (depolarization threshold range ±10 DU).

[0059] [Description of the comparative example]

[0060] In the comparative example, numerous semiconductor wafers were produced using the method described in EP 4151782 B1. Compared to Working Example 1, interstitial oxygen concentration measurements via LT-FTIR showed a greater edge drop in oxygen concentration, as can be seen in Figure 3. Therefore, the interstitial oxygen concentration in the annular edge region at a distance of 147 mm to 150 mm from the semiconductor wafer rotation axis decreased significantly by more than 0.2 × 10¹⁷ atoms / cm³. The wafers were further subjected to the thermally induced dislocation resistance tests described in Working Example 1, including mechanical stress testing and subsequent SIRD measurements and evaluation. During this process, a percentage bfc greater than 5% was determined, indicating that the wafer has a considerable number of thermally induced dislocations (depolarization threshold range ±10 DU). Figure 4, shown by SIRD measurements, illustrates that after the mechanical stress test, a higher concentration of stress and consequently defects were present in the edge region compared to the working example.

Claims

1. A single-crystal silicon semiconductor wafer having a front side and a back side, comprising: an annular edge region at the outer edge of the wafer, wherein the thickness of the wafer tapers in a radially outward direction; and a region having a constant axial thickness, comprising an N-region disposed within the annular edge region; wherein the region having a constant axial thickness includes a near-surface region on the front side, a near-surface region on the back side, and an inner region disposed between the near-surface regions; and the near-surface region on the front side extends axially downward from the surface of the front side to a depth of not less than 50 micrometers; The interstitial oxygen concentration in the entire internal region is not less than 5.2 × 10¹⁷ atoms / cubic centimeter and not more than 5.8 × 10¹⁷ atoms / cubic centimeter, with a radial variation of not more than 0.2 × 10¹⁷ atoms / cubic centimeter; and the nitrogen concentration in the near-surface region on the front side decreases axially from the surface to the interior of the semiconductor wafer, and at a depth of 5 micrometers from the surface, it is not less than 1.0 × 10¹⁴ atoms / cubic centimeter and not more than 1.7 × 10¹⁵ atoms / cubic centimeter.

2. The semiconductor wafer as claimed in claim 1, wherein, The interstitial oxygen concentration in the entire internal region varies in the radial direction by no more than 0.1 × 10¹⁷ atoms per cubic centimeter.

3. The semiconductor wafer as described in claim 1 or 2, wherein, The interstitial oxygen concentration in the entire internal region after heat treatment is not less than 4.40 × 10¹⁷ atoms / cubic centimeter. The heat treatment includes the following steps: a first step in which the semiconductor wafer is exposed to an atmosphere composed of a mixture of oxygen and nitrogen at a temperature of 800°C, with a volume ratio of O₂:N₂ of 1:10, for 4 hours; and a second step in which the semiconductor wafer is exposed to an atmosphere composed of a mixture of oxygen and nitrogen at a temperature of 1000°C, with a volume ratio of O₂:N₂ of 1:10, for 16 hours.

4. The semiconductor wafer as claimed in claim 3, wherein, The interstitial oxygen concentration in the entire internal region after the heat treatment is no more than 1.30 × 10¹⁷ atoms / cubic centimeter lower than before the heat treatment.

5. The semiconductor wafer as claimed in claim 4, wherein, After the heat treatment, the interstitial oxygen concentration in the entire internal region is no more than 1.00 × 10¹⁷ atoms per cubic centimeter lower than before the heat treatment.

6. The semiconductor wafer as described in claim 1 or 2, wherein, The near-surface region on the front side has a higher nitrogen concentration than the near-surface region on the back side.

7. The semiconductor wafer as claimed in claim 1 or 2, wherein, The near-surface region on the front side has a denuded zone that extends axially downward from the surface of the front side to a depth of not less than 10 micrometers into the interior of the semiconductor wafer; and below the denuded zone is a region with a BMD (bulk micro defects) density of 1.1 × 10¹⁰ / cm³ to 1.3 × 10¹⁰ / cm³.

8. The semiconductor wafer as claimed in claim 1 or 2, wherein, The carbon concentration in this region with a constant axial thickness is no greater than 5.0 × 10¹⁵ atoms per cubic centimeter at any location.

9. The semiconductor wafer as claimed in claim 1 or 2, wherein the N region is free of aggregates of interstitial silicon atoms or vacancies with a diameter greater than 20 nanometers.

10. The semiconductor wafer as claimed in claim 1 or 2, wherein the N region is free of agglomerates of interstitial silicon atoms or vacancies with a diameter greater than 15 nanometers.

11. The semiconductor wafer as claimed in claim 1 or 2, wherein, The concentration of crystal-originating particles (COPs) with a size of no more than 15 nanometers in the semiconductor wafer is no more than 3.0 × 10⁵ / cm³.

12. The semiconductor wafer as claimed in claim 1 or 2, wherein, The semiconductor wafer has a diameter of not less than 300 mm and not more than 310 mm, and a thickness of not less than 500 micrometers and not more than 1500 micrometers.

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