Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes conductive lines and via structures. The via structure is on the conductive lines and includes a first via portion, a second via portion, and a connecting portion. The connecting portion connects the first via portion and the second via portion. The depth of the connecting portion is less than the depth of the first via portion and the depth of the second via portion.

Claims

1. A semiconductor structure comprising: a conductive line; and a via structure, the conductive line including a first via portion, a second via portion, and a connecting portion, the connecting portion being connected between the first via portion and the second via portion, wherein a depth of the connecting portion is less than a depth of the first via portion and a depth of the second via portion, the first via portion, the connecting portion, and the second via portion are arranged along a first direction, and a width of the conductive line in a second direction is equal to or substantially equal to a width of the first via portion in the second direction or a width of the second via portion in the second direction, the second direction being perpendicular to the first direction.

2. The semiconductor structure as claimed in claim 1, wherein the length of the conductive line in the first direction is equal to or substantially equal to 3.8 to 4.8 times the length of the first via portion in the first direction, or 3.8 to 4.8 times the length of the second via portion in the first direction.

3. The semiconductor structure as claimed in claim 2, wherein the length of the conductive line in the first direction is equal to 3.8 to 4.8 times the length of the first via portion in the first direction by 5 nanometers, or the length of the second via portion in the first direction by 3.8 to 4.8 times the length of the second via portion in the first direction by 5 nanometers.

4. The semiconductor structure as described in claim 2, wherein the length of the first via portion is equal to or substantially equal to the length of the second via portion.

5. The semiconductor structure as claimed in claim 4, wherein the width of the first via portion is equal to or substantially equal to the width of the second via portion.

6. The semiconductor structure as claimed in claim 1, wherein a length of the connection portion is equal to or substantially equal to 1.8 to 2.8 times the length of a first via portion or 1.8 to 2.8 times the length of a second via portion.

7. The semiconductor structure as claimed in claim 1, wherein the surface of the connection portion opposite to the conductive line is substantially flat.

8. The semiconductor structure as claimed in claim 1, wherein the depth of the first via is equal to or substantially equal to the depth of the second via.

9. A method for forming a semiconductor structure, comprising: providing a first layout pattern comprising a plurality of first patterns; providing a second layout pattern comprising a plurality of second patterns; overlapping the first layout pattern and the second layout pattern to determine whether at least two first patterns overlap one of the plurality of second patterns; checking the second layout pattern to determine whether a length of the second pattern is equal to or substantially equal to 3.8 to 4.8 times the length of one of the at least two first patterns; and modifying the first layout pattern to add at least one connecting pattern between the at least two first patterns.

10. The method as described in claim 9 further comprises: determining whether a width of the second pattern is equal to or substantially equal to a width of the at least two first patterns.

11. The method as described in claim 9 further comprises: performing an optical proximity correction (OPC) method after modifying the first layout pattern.

12. The method of claim 11 further comprises: providing a substrate and a first photoresist layer on the substrate; transferring the modified first layout pattern to the first photoresist layer; performing an etching process and a deposition process through the first photoresist layer to form a plurality of vias and at least one connection in the substrate, wherein the plurality of vias correspond to the plurality of first patterns and the at least one connection corresponds to the at least one connection pattern.

13. The method of claim 12 further comprises: providing a dielectric layer on the substrate and a second photoresist layer on the dielectric layer; transferring the second layout pattern to the second photoresist layer; and performing another etching process and another deposition process through the second photoresist layer to form a plurality of conductive lines in the dielectric layer, wherein the plurality of conductive lines correspond to the plurality of second patterns.

14. The method as described in claim 12, wherein a depth of the at least one connection portion is less than a depth of the plurality of through-hole portions.

15. The method as described in claim 9, wherein the at least one connecting pattern is connected between the at least two first patterns.

16. The method as described in claim 9, wherein the at least one connecting pattern and the at least two first patterns are arranged along a first direction, and the length of the second pattern is in the first direction.

17. The method of claim 9 further comprises: providing a substrate and a first photoresist layer on the substrate; transferring the modified first layout pattern to the first photoresist layer; performing an etching process and a deposition process through the first photoresist layer to form a plurality of vias and at least one connection in the substrate, wherein the plurality of vias correspond to the plurality of first patterns, the at least one connection corresponds to the at least one connection pattern, and the at least one connection is connected between two vias in the plurality of vias.

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