Semiconductor device and manufacturing method thereof

Abstract

A method for manufacturing a semiconductor device includes: forming a plurality of photoresist strips on a substrate, wherein an opening is formed in each of the photoresist strips; forming a plurality of contacts in the opening of the photoresist strips, wherein an outer contour of each of the contacts is a strip shape; and using the photoresist strips to form a plurality of bit lines.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Prior Technology

[0002] In the final stage of memory cell manufacturing, wafer acceptance testing (WAT) is often performed to test the electrical properties of the wafer. However, despite changes in wafer manufacturing processes and the introduction of self-aligned double patterning (SADP), testing has become more difficult to perform due to the presence of numerous active areas (AAs) caused by mask shifting. This mask shifting is difficult to control or avoid, necessitating new testing methods. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a semiconductor device.

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a plurality of photoresist strips on a substrate, wherein an opening is formed in each of the photoresist strips; forming a plurality of contacts in the opening of the photoresist strips, wherein an outer contour of each of the contacts is a strip shape; and using the photoresist strips to form a plurality of bit lines.

[0005] In some embodiments disclosed herein, the method of manufacturing the semiconductor device further includes forming a plurality of active regions on the substrate.

[0006] In some embodiments of this disclosure, each of the contacts connects to both of the active regions.

[0007] In some embodiments disclosed herein, each of the active regions connects to both of the contacts.

[0008] In some embodiments disclosed herein, the method of manufacturing the semiconductor device further includes forming a peripheral contact on the substrate.

[0009] In some embodiments disclosed herein, the peripheral contact is electrically connected to the contacts.

[0010] In some embodiments disclosed herein, the method of manufacturing the semiconductor device further includes measuring an active region via the contacts.

[0011] Another aspect of this disclosure provides a method for manufacturing a semiconductor device.

[0012] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a plurality of active regions on a substrate; using a plurality of photoresist strips to form a plurality of contacts, wherein an opening is formed in each of the photoresist strips, and an outer periphery of each of the contacts is strip-shaped; and using the photoresist strips to form a plurality of bit lines.

[0013] In some embodiments of this disclosure, each of the contacts connects to both of the active regions.

[0014] In some embodiments disclosed herein, each of the active regions connects to both of the contacts.

[0015] In some embodiments disclosed herein, the method of manufacturing the semiconductor device further includes forming a peripheral contact on the substrate.

[0016] In some embodiments disclosed herein, the peripheral contact is electrically connected to the contacts.

[0017] In some embodiments disclosed herein, the method of manufacturing the semiconductor device further includes measuring an active region via the contacts.

[0018] Another aspect of this disclosure provides a semiconductor device.

[0019] According to one embodiment of this disclosure, a semiconductor device includes a substrate, a plurality of active regions, a plurality of contacts, a plurality of bit lines, and a plurality of peripheral contacts. The active regions are positioned on the substrate. The contacts are positioned on and electrically connected to the active regions, wherein an outer periphery of each of the contacts is a strip shape. The bit lines are positioned on the active regions. The peripheral contacts are positioned on the active regions.

[0020] In some embodiments of this disclosure, each of the contacts connects to both of the active regions.

[0021] In some embodiments disclosed herein, each of the active regions connects to both of the contacts.

[0022] In some embodiments disclosed herein, the peripheral contacts are electrically connected to the contacts and the active areas.

[0023] In the embodiments described above in this disclosure, since these strip-shaped contacts are formed in the semiconductor device manufacturing process, the test probe can be electrically connected to both of these peripheral contacts when performing wafer acceptance testing. Subsequently, a single conductive path formed by the peripheral contacts, the strip-shaped contacts, and the active area is formed and can be used to perform wafer acceptance testing. This single conductive path makes the testing easier and ensures the yield. Simple Explanation of the Diagram

[0024] The nature of this disclosure can be best understood by reading it in conjunction with the accompanying illustrations and by the embodiments described below. Note that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation. Figures 1 to 4 are top views of intermediate steps in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 5 is a top view of the semiconductor device at step 4. Figure 6 is a top view of an intermediate step in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Implementation

[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. Furthermore, references to numbers and / or letters may be repeated throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0026] Additionally, spatial relative terms, such as "below," "below," "lower part," "above," "upper part," and similar terms, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0027] The terms “about,” “approximately,” or “substantially” as used herein, taking into account the specific quantity of measurement discussed and the errors associated with the measurement (i.e., limitations of the system being measured), include the value and the average of the value within an acceptable tolerance range for a specific value as determined by a person skilled in the art. For example, “about” may indicate within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, or ±5% of the value. Furthermore, for the terms “about,” “approximately,” or “substantially” as used herein, the relatively acceptable tolerance range or standard deviation may be selected based on optical properties, etched properties, or other properties, rather than a single standard applied to all properties.

[0028] Figures 1 through 4 are top views of intermediate steps in a method of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Referring to Figure 1, firstly, a plurality of active regions 120 are formed on a substrate 110. The number of active regions 120 is not limited to the number shown in Figure 1. In some embodiments, the active regions 120 are elliptical in shape. In some embodiments, the active regions 120 are circular, square, or any suitable shape. In some embodiments, the active regions 120 may be configured as an array or other suitable configuration that maximizes the density of the active regions 120.

[0029] Referring to Figure 2, a plurality of photoresist strips 200 are subsequently formed on substrate 110, with an opening 210 formed in each of the photoresist strips 200. In some embodiments, the photoresist strips 200 are bit line (BL) contour etchants, as they are used to form bit lines in subsequent processes. In some embodiments, the photoresist strips 200 are uniformly coated on the substrate and then subjected to exposure and development processes. In some embodiments, the openings 210 of the photoresist strips 200 are configured such that all openings 210 are arranged in a row. The extension direction of the wiring may be parallel to the major axis of the elliptical active region 120, or may have an angle between them.

[0030] Referring to Figure 3, a plurality of contacts 130 are subsequently formed in the opening 210 of the photoresist strip 200, wherein the outer contour of each of the contacts 130 is strip-shaped. The contacts 130 are positioned on and electrically connected to the active region 120. In some embodiments, the contacts 130 are contact pads of the active region 120. In some embodiments, each of the contacts 130 connects to both of the active regions 120. In some embodiments, each of the active regions 120 connects to both of the contacts 130. Because each of the contacts 130 connects to both of the active regions 120 and each of the active regions 120 connects to both of the contacts 130, contact-AA-contact…AA-contact is formed after the contacts 130 are formed on the active region 120. In some embodiments, the material of the contacts 130 may include conductive materials such as copper (Cu), silver (Ag), silver (Au), gold (Au), alloys thereof, combinations thereof, or the like. In some embodiments, the contact 130 may be formed via a deposition process. It is worth noting that other contact pads, not just strips, are also formed in this step, which will be described in Figure 5.

[0031] Referring to Figure 4, peripheral contacts 140 are then formed on substrate 110. Peripheral contacts 140 are positioned on the outermost edge of substrate 110 above contacts 130 and are electrically connected to the outermost contact 130 of substrate 110, thus electrically connecting peripheral contacts 140 to the conductive path mentioned above. Figure 4 shows only two peripheral contacts 140, but in real-world applications, more peripheral contacts 140 can be formed. The purpose of peripheral contacts 140 is to connect test probes for active area (AA) resistance testing, enabling wafer acceptance testing to be performed.

[0032] Figure 5 is a top view of the semiconductor device at the step in Figure 4. Referring to Figure 5, after the step of forming peripheral contacts 140, the resistance of the active region is measured via contacts 130. Notably, the measurement uses only strip-shaped contacts 130, which are located in the conductive path mentioned above. Other contact pads 160 that are not strip-shaped are used for electrical connections to subsequent processes of circuitry, such as bit lines, word lines, or other peripheral circuitry. In some embodiments, the active region resistance is measured via a four-terminal sensing method, but this disclosure is not limited thereto. In some embodiments, two of the probes of the four-terminal sensing method are electrically connected to the peripheral contacts 140 in Figure 5.

[0033] Figure 6 is a top view of an intermediate step in a method for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Referring to Figure 6, subsequently, a plurality of bit lines 150 are formed using a photoresist strip 200. After this step, the semiconductor device 100 is manufactured. The bit lines 150 are positioned on and electrically connected to the active region 120. Notably, although there are openings 210 in the photoresist strip 200, the formed bit lines 150 are continuous. In some embodiments, the bit lines 150 are formed on both sides of the photoresist strip 200, such that each photoresist strip 200 can form two bit lines 150. In some embodiments, word lines (not shown) are formed after this step, and the word lines are perpendicular to the extension direction of the bit lines 150.

[0034] In short, since the strip contact 130 is formed in the manufacturing process of the semiconductor device 100, the test probe can be electrically connected to both of the peripheral contacts 140 when wafer acceptance testing is performed. Subsequently, a single conductive path formed by the peripheral contacts 140, the strip contact 130, and the active region 120 is formed and can be used to perform wafer acceptance testing, which makes the testing easier and ensures the yield.

[0035] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0036] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the additional claims should not be limited to the description of the embodiments contained herein.

[0037] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the following claims.

[0038] 100: Semiconductor devices 110:Substrate 120: Active Area 130: Contact 140: Peripheral Touchpoints 150: Bit line 160: Contact pad 200: Photoresist strip 210: Opening

[0039] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: forming a plurality of photoresist strips on a substrate, wherein an opening is formed in each of the photoresist strips; forming a plurality of contacts in the opening of the photoresist strips, wherein an outer contour of each of the contacts is a strip shape; and using the photoresist strips to form a plurality of bit lines.

2. The method for manufacturing a semiconductor device as claimed in claim 1 further comprises the step of: forming a plurality of active regions on the substrate.

3. A method of manufacturing a semiconductor device as claimed in claim 2, wherein each of the contacts connects to both of the active regions.

4. A method of manufacturing a semiconductor device as claimed in claim 2, wherein each of the active regions is connected to both of the contacts.

5. The method of manufacturing a semiconductor device as claimed in claim 1 further includes the step of: forming a peripheral contact on the substrate.

6. A method of manufacturing a semiconductor device as described in claim 5, wherein the peripheral contacts are electrically connected to the contacts.

7. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising the step of: measuring an active region resistance via the contacts.

8. A method for manufacturing a semiconductor device, comprising the steps of: forming a plurality of active regions on a substrate; forming a plurality of contacts using a plurality of photoresist strips, wherein an opening is formed in each of the photoresist strips, and an outer contour of each of the contacts is a strip shape; and forming a plurality of bit lines using the photoresist strips.

9. A method of manufacturing a semiconductor device as claimed in claim 8, wherein each of the contacts connects to both of the active regions.

10. A method of manufacturing a semiconductor device as claimed in claim 8, wherein each of the active regions is connected to both of the contacts.

11. The method of manufacturing a semiconductor device as described in claim 8 further comprises the step of: forming a peripheral contact on the substrate.

12. A method of manufacturing a semiconductor device as claimed in claim 11, wherein the peripheral contact is electrically connected to the contacts in the openings of the equibit lines.

13. The method of manufacturing a semiconductor device as claimed in claim 8 further comprises the step of: measuring an active region resistance via the contacts.

14. A semiconductor device comprising: a substrate; a plurality of active regions positioned on the substrate; a plurality of contacts positioned on and electrically connected to the active regions, wherein an outer contour of each of the contacts is a strip shape, and each of the contacts connects two of the active regions; a plurality of bit lines positioned on the active regions; and a plurality of peripheral contacts positioned on the active regions.

15. The semiconductor device as claimed in claim 14, wherein each of the active regions is connected to both of the contacts.

16. The semiconductor device as claimed in claim 14, wherein the peripheral contacts are electrically connected to the contacts and the active regions.

17. The semiconductor device as claimed in claim 14, wherein two of the peripheral contacts are electrically connected to each other via the active regions and the contacts.

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