Integrated circuit and testing method thereof

Abstract

An integrated circuit includes a plurality of semiconductor dies, a power network, and a power control circuit. The semiconductor dies may be disposed on a single semiconductor substrate. Each of the semiconductor dies may include a plurality of operating modules. A plurality of power switches may be respectively coupled to the operating modules. The power network may be disposed relative to the semiconductor dies. The power control circuit is configured to: receive a first signal indicating that one or more operating modules of at least one of the semiconductor dies are damaged; and based on the first signal, send a second signal to the corresponding power switches respectively coupled to the one or more operating modules to disconnect the power supply voltage from the one or more operating modules.

Description

[Technical Field]

[0001] None. [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Primarily, this improvement in integration density stems from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of an embodiment of this disclosure. Repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] In addition, spatial relative terms, such as "below," "below," "lower part," "above," "upper part," "top," "bottom," and the like, may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] In some integrated circuit architectures, all dies and modules can be connected to a single power supply. This design simplicity promotes power distribution but introduces significant vulnerability: a failure in either a die or a module can lead to abnormal power consumption. When a component / die / module fails, it typically absorbs excessive power, an anomalous decrease in overall computing power due to inefficient resource allocation and increased thermal load. Therefore, this results in higher power consumption and lower performance delivery, eroding the efficiency and effectiveness of integrated circuits in critical applications.

[0008] This disclosure presents an embodiment of a novel method for power management in low-power artificial intelligence systems by integrating an embedded power headend into each module, thereby ensuring distributed and autonomous power control. This design is critical for enhancing the overall energy efficiency of the system. By allowing each module to modulate its own power supply, the system minimizes unnecessary power consumption and reduces the risk of power-related failures that can occur when a single power supply powers all components / modules / die on a single substrate / wafer. The embedded power headend in each module maximizes computational power by ensuring that each module operates within its power range, thereby maximizing performance and extending the lifespan of system components. This architecture step-through provides a low-power solution and significantly improves computational efficiency.

[0009] This disclosure provides various embodiments of an integrated circuit including a plurality of semiconductor dies, a power network, and power control circuitry. The plurality of semiconductor dies may be disposed on a single semiconductor substrate. Each of the plurality of semiconductor dies may include a plurality of operating modules. A plurality of power switches may be respectively coupled to the plurality of operating modules. The power network may be disposed relative to the plurality of semiconductor dies and may be used to provide a power supply voltage to each of the plurality of semiconductor dies. The power control circuitry may be disposed on the semiconductor substrate. The power control circuitry may be used to: receive a first signal indicating that one or more operating modules of at least one of the plurality of semiconductor dies are damaged; and based on the first signal, send a second signal to a corresponding power switch respectively coupled to one or more operating modules to disconnect the power supply voltage from being provided to one or more operating modules. The proposed integrated circuitry provides a low-power solution and significantly enhances computational efficiency in artificial intelligence computing.

[0010] Figure 1 illustrates an example schematic diagram of an integrated circuit 100 according to some embodiments. The integrated circuit 100 may include a plurality of semiconductor dies 100a, 100b, 100n, a power network 110, and a power control circuit 120. In some embodiments, the plurality of semiconductor dies 100a, 100b, 100n may be disposed on a single semiconductor substrate (e.g., a wafer). The semiconductor substrate may serve as the basis for a circuit layer on which operational microelectronic devices are constructed. The circuit layer typically defines one or more surfaces on each die, on which circuits and various microelectronic devices are fabricated using a photolithography system. The semiconductor substrate is preferably made of silicon, but it may also be composed of or include other suitable materials such as silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide, alloys of silicon and germanium, indium phosphide, and the like. In its basic form, the substrate may be a native wafer. Additionally, the substrate may have one or more material layers similar to photoresist, dielectric, and conductive materials. The photoresist, i.e., the photosensitive material used in lithography, can be positive or negative. Semiconductor substrates, typically circular in shape, are available in various diameters including 100 mm, 150 mm, 200 mm, 300 mm, and 450 mm, thereby facilitating the fabrication of integrated circuits.

[0011] In some embodiments, each of a plurality of semiconductor dies (e.g., die 1 100a, die 2 100b, ..., die N 100n) may include a plurality of operation modules 104 (e.g., module 1, module 2, module 3, ..., module N). In some embodiments, the operation module 104 of each semiconductor die may be identical to each other. In some embodiments, each of the operation modules 104 may serve as a computing unit for artificial intelligence. In some embodiments, each of the plurality of operation modules 104 may include one of the following: a natural language processing (NLP) module, a computer vision module, a speech recognition module, a recommendation system module, a predictive analytics module, an autonomous navigation module, an anomaly detection module, an emotion detection module, a generative model module, a knowledge graph module, an optical character recognition module, a data cleaning module, a dynamic pricing module, a pose estimation module, or a time series analysis module. In some embodiments, the integrated circuit may include several dedicated modules tailored for various artificial intelligence tasks. Natural language processing (NLP) modules process human language to perform tasks such as translation and sentiment analysis. Computer vision modules interpret visual data, enabling image recognition and object detection. Speech recognition modules convert spoken language into text for voice command functionality, while recommendation system modules personalize suggestions for users on platforms such as online shopping. Predictive analytics modules use historical data to predict future events that can be used in fields such as finance and health. Autonomous navigation modules enable robots and vehicles to navigate using technologies similar to GPS and radar without human input. Anomaly detection modules identify key abnormal data patterns in an area, such as spoofing detection. Emotion detection modules recognize human emotions from facial expressions or tone of voice, enhancing customer service applications. Generative modeling modules generate new data instances, such as synthesized images or music. Knowledge graph modules organize information with logical relationships to aid semantic search and decision support. The Optical Character Recognition (OCR) module converts documents into an editable format. The data cleaning module corrects errors in the dataset to ensure data quality. The dynamic pricing module adjusts prices based on market conditions commonly used in e-commerce. The pose estimation module determines the position of objects in images used for augmented reality, and the time series analysis module analyzes sequential data points for predicting financial conditions and weather forecasts. Each module is equipped with a specific algorithm to efficiently handle its designated task within the AI ​​system.

[0012] In some embodiments, a plurality of die-to-die connections may be formed between a plurality of semiconductor dies (e.g., die 1 100a, die 2 100b, ..., die N 100n) to establish communication. The plurality of semiconductor dies 100a, 100b, 100n may be directly connected to one or more die-to-die connections, or indirectly connected at least via intermediate die-to-die connections established between one or more semiconductor dies. Therefore, this configuration enables faster communication and data processing between dies compared to communication between dies not maintained on the same substrate (e.g., the same wafer). Each of the plurality of semiconductor dies 100a, 100b, 100n remains on a single substrate and is not diced from the substrate into individual dies for separate packaging into individual computer chips. Specifically, during formation, a single excess bare die along the periphery of the substrate (e.g., a bare die without circuitry or an inactive bare die) is preferably removed from the substrate, and the remaining portion of the substrate having a plurality of semiconductor bare dies 100a, 100b, 100n (e.g., inactive bare dies) can be formed together with the substrate into a predetermined shape (e.g., a rectangular shape). The resulting substrate, after being reduced to remove excess bare dies and potentially after one or more additional reinforcements or IC manufacturing processes, can then be packaged onto a board (e.g., a printed circuit board (PCB) or an organic substrate).

[0013] In some embodiments, a plurality of power switches 102 may be coupled to the operating modules 104 respectively. In some embodiments, the power switch 102 may be used to selectively decouple a voltage carried via the power network 110 from the corresponding operating module based on a first signal indicating that the corresponding operating module is damaged. In some embodiments, the voltage may include the power supply voltage (VDD) or the ground voltage (VSS). In some embodiments, the power switch 102 may include at least one of the following: a head terminal or a foot terminal. In electronic circuit design, particularly in integrated circuits, "head terminal" and "foot terminal" may refer to a specific configuration of a transistor used to control the power distribution. The head terminal, commonly referred to as a "pull-up" transistor, may typically be an n-type MOSFET and may be used to connect a circuit node to the positive power supply voltage (VDD). Positioned at the top of the circuit layout, the head terminal transistor may be used to boost the voltage to the power supply level upon startup, thereby allowing current to flow through the circuit. Conversely, the pin of a p-type MOSFET, known as a "pull-down" transistor, can be placed at the bottom of the layout and connected to the circuit node to ground or a lower voltage level (VSS). This pin transistor pulls the voltage down to the ground level under certain conditions, thus ensuring the current's path out of the circuit is complete. In some embodiments, at least one of the plurality of power switches 102 can be used to selectively decouple the voltage carried via the power network 110 from the corresponding operating module 104 based on a first signal indicating that the corresponding operating module has failed.

[0014] In circuit design, the power switch (e.g., head unit) features act as a critical control element, selectively allowing or restricting current based on operational requirements. This component can be configured using various transistor types, including all NMOS, all PMOS, or combinations of PMOS and NMOS, depending on the specific requirements of the application. The versatility of the head unit composition allows it to adapt to different power handling and switching characteristics, thus making it suitable for a wide range of electronic environments. In some embodiments, the head unit also includes an embedded level shifter, an important addition enabling the conversion from low-voltage signals to high-voltage outputs. This feature is particularly beneficial in high-voltage applications, where maintaining signal integrity at high operating voltages is critical. By integrating a level shifter within the head unit, the circuit ensures that voltage levels are properly managed, thereby supporting stable and efficient high-voltage operation.

[0015] In some embodiments, each of the plurality of power switches may include: a first inverter for receiving a first data bit of a second signal and logically inverting the first data bit to provide a second data bit; a second inverter for receiving the second data bit and logically inverting the second data bit to provide a third data bit; and a p-type transistor having a source terminal coupled to a power network, a gate terminal for receiving the third data bit, and a drain terminal coupled to a corresponding operating module.

[0016] In some embodiments, each of the plurality of power switches may include: a first inverter for receiving a first data bit of a second signal and logically inverting the first data bit to provide a second data bit; a second inverter for receiving the second data bit and logically inverting the second data bit to provide a third data bit; a first p-type transistor having a source terminal coupled to a power network, a gate terminal for receiving the third data bit, and a drain terminal; and a second p-type transistor having a source terminal coupled to the drain terminal of the first p-type transistor, a gate terminal for receiving half of the power supply voltage, and a drain terminal coupled to a corresponding operating module.

[0017] In some embodiments, each of the plurality of power switches may include: a first inverter for receiving a first data bit of a second signal and logically inverting the first data bit to provide a second data bit; a second inverter for receiving the second data bit and logically inverting the second data bit to provide a third data bit; a third inverter for receiving the third data bit and logically inverting the third data bit to provide a fourth data bit; a fourth inverter for receiving the fourth data bit and logically inverting the fourth data bit to provide a fifth data bit; a first p-type transistor having a source terminal coupled to a power network, a gate terminal for receiving the fifth data bit, and a drain terminal coupled to a corresponding operating module; and a second p-type transistor having a source terminal coupled to a power network, a gate terminal for receiving the third data bit, and a drain terminal coupled to a corresponding operating module. In some embodiments, the size of the second p-type transistor may be smaller than the size of the first p-type transistor.

[0018] In some embodiments, a plurality of semiconductor bare wafers 100a, 100b, 100n may be disposed on a single semiconductor substrate, such as a wafer or board. The substrate may serve as the basis for a circuit layer on which a functional microelectronic device is constructed. The circuit layer typically defines one or more surfaces on each bare wafer on which circuits and various microelectronic devices are fabricated using a photolithography system. The semiconductor substrate is preferably made of silicon, but the semiconductor substrate may also be composed of or include other suitable materials, such as silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide, alloys of silicon and germanium, indium phosphide, and the like. In its basic form, the substrate may be a native wafer. In addition, the substrate may have one or more material layers similar to photoresist, dielectric, and conductive materials. The photoresist, i.e., the photosensitive material used in photolithography, may be positive or negative. Semiconductor substrates, typically circular in shape, are available in various diameters including 100 mm, 150 mm, 200 mm, 300 mm and 450 mm, thereby facilitating the fabrication of integrated circuits.

[0019] In some embodiments, a power network 110 may be disposed relative to a plurality of semiconductor bare dies 100a, 100b, 100n. The power network 110 may be used to provide a power supply voltage to each of the plurality of semiconductor bare dies 100a, 100b, 100n. In some embodiments, the power network 110 may include a plurality of interconnect structures disposed in one or more metallization layers formed over a semiconductor substrate. These metallization layers may include metals such as copper or aluminum. The primary function of the power network is to provide a stable power supply voltage to the various semiconductor bare dies on the substrate, thereby ensuring that each module receives the necessary power supply when the module meets operational requirements.

[0020] In some embodiments, the power control circuit 120 may be disposed on a semiconductor substrate. The power control circuit 120 may be configured to receive a first signal indicating that one or more operating modules of at least one of a plurality of semiconductor dies have been damaged. Based on the first signal, the power control circuit 120 may be configured to send a second signal to a corresponding power switch respectively coupled to one or more operating modules to disconnect the power supply voltage from the one or more operating modules. In some embodiments, the power control circuit 120 may act as a headend decoder. The power control circuit 120 may send a signal to disable the power supply voltage or disconnect the power supply voltage from the corresponding power switch of a specific module on a given die. For example, if module 1 on die 2 is damaged, the power control circuit may send a signal to the headend of module 1 on die 2 to disable the headend and prevent the power supply voltage from being delivered. In some embodiments, the first signal may include a first number (N1) of first data bits. The second signal may include a second number (N2) of second data bits. In some embodiments, N2 may be equal to In some embodiments, N2 may be equal to the total number of power switches formed on the semiconductor substrate. In some embodiments, the headend decoder in the circuit design is carefully fabricated to address the need for multi-module selection in complex systems. The headend decoder may be designed to accommodate scenarios where more than one module may fail simultaneously, thereby making a decoder capable of participating in multiple modules simultaneously to ensure system stability and functionality necessary.

[0021] In some embodiments, the power control circuit 120 may include a plurality of first inverters, a plurality of NAND gates, and a plurality of second inverters. Each of the plurality of first inverters can be used to logically invert a corresponding first data bit to provide N1 third data bits. Each of the plurality of NAND gates can be used to input a corresponding third data bit to provide N2 fourth data bits. Each of the plurality of second inverters can be used to logically invert a corresponding fourth data bit to provide a corresponding second data bit.

[0022] The method for testing whether a module is damaged includes several key steps. Initially, all bare dies and modules within the system are initiated for a comprehensive scan test. This initial step ensures that each component is operational and ready for further diagnostics. During this phase, the current drawn by each module is closely monitored. Deviations in the current level can indicate potential faults. Specifically, if the current of a module does not meet predefined standard requirements, the module is marked as potentially faulty. Once a module is identified as damaged, the next step involves the power control circuitry. The power control circuitry plays a crucial role in troubleshooting. The power control circuitry adjusts the decoder settings specifically for the faulty module. By setting the correct decoder address, the power control circuitry effectively controls systems or specific components similar to the headend associated with the damaged module. Actions taken include disabling the headend of the damaged module, which prevents further voltage supply to the faulty unit. This isolation helps prevent additional power consumption and maintains the overall stability and functionality of the circuitry.

[0023] Figure 2 illustrates an example schematic diagram of the power control circuit 120 of the integrated circuit of Figure 1 according to some embodiments. Figure 2 provides a detailed illustration of a system configuration including two bare dies, each of which includes two modules. The power control circuit 120 may utilize two control pins that are integrated for the operation of the integrated circuit. These control pins facilitate the generation of four unique signals: PD_d1m1, PD_d1m2, PD_d2m1, and PD_d2m2. Each signal corresponds to a specific module on each bare die, thereby effectively controlling the power disable function. In some embodiments, the power control circuit 120 may act as a headend decoder. The power control circuit 120 may send signals to disable the power supply voltage or disconnect the power supply voltage from the corresponding power switch of a specific module on a given bare die.

[0024] In some embodiments, the power control circuit 120 may include a plurality of first inverters 202, 204, a plurality of NAND gates 212, 214, 216, 218, and a plurality of second inverters 222, 224, 226, 228. Each of the plurality of first inverters 202, 204 can be used to logically invert a corresponding first data bit (e.g., A0, A1) to provide N1 third data bits (e.g., A0B, A1B). For example, the first inverter 202 can receive the A0 signal and output the inverted A0B signal. Each of the plurality of NAND gates 212, 214, 216, 218 can be used to input corresponding third data bits and first data bits to provide N2 fourth data bits. For example, the NAND gate 212 can receive the A0B signal and output the A1B signal. NAND gate 212 can then output a signal referred to as fourth data. Each of the plurality of second inverters 222, 224, 226, 228 can be used to logically invert a corresponding bit of the fourth data to provide a corresponding bit of the second data (e.g., PD_d1m1, PD_d1m2, PD_d2m1, PD_d2m2). For example, second inverter 222 can receive the fourth data and output a PD_d1m1 signal indicating that module 1 on bare die 1 is damaged.

[0025] The power control circuit 120 can be used to receive a first signal (e.g., A0, A1). The first signal can indicate that at least one or more of the operating modules among a plurality of semiconductor bare wafers are damaged. Based on the first signal, the power control circuit 120 can be used to send a second signal (e.g., PD_d1m1, PD_d1m2, PD_d2m1, PD_d2m2) to corresponding power switches respectively coupled to one or more operating modules, so as to disconnect the power supply voltage and prevent it from being supplied to one or more operating modules. In some embodiments, the first signal may include a first number (N1) of first data bits (e.g., A0, A1). The second signal may include a second number (N2) of second data bits (e.g., PD_d1m1, PD_d1m2, PD_d2m1, PD_d2m2). In some embodiments, N2 may be equal to the total number of power switches formed on the semiconductor substrate. In some embodiments, N2 may be equal to the total number of power switches formed on the semiconductor substrate. When A1 = 0 and A0 = 0, the power control circuit 120 can output a signal to disable the header of module 1 on bare wafer 1 (e.g., PD_d1m1). When A1 = 0 and A0 = 1, the power control circuit 120 can output a signal to disable the header of module 2 on bare wafer 1 (e.g., PD_d1m2). When A1 = 1 and A0 = 0, the power control circuit 120 can output a signal to disable the header of module 1 on bare wafer 2 (e.g., PD_d2m1). When A1 = 1 and A0 = 1, the power control circuit 120 can output a signal to disable the header of module 2 on bare wafer 2 (e.g., PD_d2m2).

[0026] Figure 3 illustrates an example schematic diagram of an integrated circuit according to some examples and example waveforms of various signals during operation of the integrated circuit. Figure 3 illustrates an example of a module on a bare die being damaged. In some embodiments, if module 1 on bare die 2 encounters a fault, the power control circuit 120 can respond quickly by directly sending a signal designated PD_d2m1 directly to the headend 102 of module 1 on bare die 2. This signal effectively disables the headend, thereby cutting off the power supply voltage from the power network 110 to the damaged module.

[0027] As depicted in Figure 3(b), the system is initially configured such that the headers of all modules are enabled by default at the start of the operating cycle. This setting ensures that all modules start from standard operating conditions, thereby allowing for consistent performance evaluation and management across the board. However, when module 1 on bare die 2 is tested and subsequently identified as defective, the control logic within the power control circuit 120 adjusts its response based on this specific condition. The A1 signal is triggered high, indicating that the module has a problem. Under the condition that A1 = 1 and A0 = 0, the power control circuit 120 then actively outputs the PD_d2m1 signal to immediately disable the header of module 1 on bare die 2. This automatic fault-tolerant response not only isolates the faulty module to prevent potential damage but also maintains the stability and efficiency of the remaining system. By implementing this mechanism, the integrated circuit ensures that operational disturbances are minimized and that module failures do not jeopardize the integrity of the entire system on a single semiconductor substrate.

[0028] Figure 4 illustrates an example schematic diagram of a power switch 102 of an integrated circuit 100 of Figure 1 according to some embodiments. Each of the semiconductor dies in the integrated circuit 100 may include a plurality of operating modules 104. Each of the operating modules 104 may be coupled to the power switch 102 (e.g., a head or a foot). In some embodiments, the power switch 102 may include a first inverter 402, a second inverter 404, and a p-type transistor 406. The first inverter 402 may be used to receive a first data bit (e.g., PD) of a second signal and logically invert the first data bit to provide a second data bit. The second inverter 404 may be used to receive the second data bit and logically invert the second data bit to provide a third data bit. The p-type transistor 406 may have a source terminal coupled to a power network 110, a gate terminal for receiving the third data bit, and a drain terminal coupled to a corresponding operating module 104. In integrated circuit design, the power switch / power header 102 plays a crucial role in managing the power states of individual modules. Specifically, the power switch 102 operates using a simple yet effective binary communication mechanism. When the PD signal is set low (L), power is supplied to the module, effectively turning it on. Conversely, when the PD signal is set high (H), power to the module is cut off, causing the module to be turned off. This binary control allows for precise and effective management of power distribution across various modules within a single semiconductor substrate, ensuring power is used for functional modules and thereby enhancing the overall energy efficiency of the system. The power switch 102 controls which modules are enabled and which are blocked. This mechanism is particularly valuable in complex electronic systems where optimal power management is critical for maintaining system stability and minimizing energy consumption.

[0029] Figure 5 illustrates an example schematic diagram of a power switch 102 of an integrated circuit of Figure 1 according to some embodiments. Each of the semiconductor dies in the integrated circuit 100 may include a plurality of operating modules 104. Each of the operating modules 104 may be coupled to the power switch 102 (e.g., a head or a foot). In some embodiments, the power switch 102 may include a first inverter 502, a second inverter 504, a first p-type transistor 506, and a second p-type transistor 508. The first inverter 502 may be used to receive a first data bit (e.g., PD) of a second signal and logically invert the first data bit to provide a second data bit. The second inverter 504 may be used to receive the second data bit and logically invert the second data bit to provide a third data bit. The first p-type transistor 506 may have a source terminal coupled to a power network 110 to receive a power supply voltage (e.g., VDD), a gate terminal for receiving the third data bit, and a drain terminal. The second p-type transistor 508 may have a source terminal coupled to the drain terminal of the first p-type transistor 506, a gate terminal for receiving half of the power supply voltage (e.g., VDD / 2), and a drain terminal coupled to the corresponding operating module 104. The integrated circuit utilizes a power supply header 102 specifically designed to handle high-power applications where the power supply voltage (VDD) exceeds typical device reliability thresholds (e.g., VDD > 0.96V). In this configuration, the power supply header operates using a direct control mechanism: setting the power disable (PD) signal low (L) enables power to be supplied to the module, allowing the module to operate under higher power conditions without compromising device reliability. Conversely, setting the PD signal high (H) shuts off power, ensuring no power is supplied to the module. This configuration ensures that there are no reliability issues in device conditions, regardless of the high power setting. The design effectively manages the risk of overvoltage damage by enabling precise control of the power supply application, thereby protecting circuit components from potential stress or failure while maintaining optimal performance.

[0030] In some embodiments, the power switch 102 may be a multi-stack configuration (e.g., an N-type stack). The power switch 102 may include a plurality of p-type transistors (e.g., N p-type transistors). In this configuration, each stack may be adapted to different voltage levels, thereby allowing for customized electrical properties for each stack. For example, a configuration where N=2 is demonstrated by using a halved voltage (VDD / 2), thereby optimizing the circuitry for specific performance requirements or power constraints. In some embodiments, N may be greater than or equal to 1, thereby ensuring that the basic threshold for circuit functionality is maintained across all configurations. This multi-stack approach not only allows for greater customization within electronic designs but also improves efficiency and the adaptability of the circuitry to various operational needs.

[0031] Figure 6 illustrates an example schematic diagram of a power switch 102 of the integrated circuit of Figure 1 according to some embodiments. Figure 7 illustrates an example schematic diagram of a level shifter 602 of the power switch 102 of Figure 6 according to some embodiments. Each of the semiconductor dies in the integrated circuit 100 may include a plurality of operating modules 104. Each of the operating modules 104 may be coupled to the power switch 102 (e.g., a head or a foot).

[0032] In some embodiments, the power switch 102 may include a level shifter 602, a first inverter 604, a second inverter 606, a first p-type transistor 608, and a second p-type transistor 610. The level shifter 602 may receive a power supply voltage VDD and a power supply voltage VDDQ (e.g., about > 0.96 V). The level shifter 602 may be used to shift the voltage from a first voltage domain to a second voltage domain for module 104. The first inverter 604 may be used to receive a first data bit (e.g., hvpg) of a second signal and logically invert the first data bit to provide a second data bit. The second inverter 606 may be used to receive the second data bit and logically invert the second data bit to provide a third data bit. The first p-type transistor 608 may have a source terminal coupled to the power network 110 to receive the power supply voltage (e.g., VDDQ), a gate terminal for receiving the third data bit, and a drain terminal. The second p-type transistor 610 may have a source terminal coupled to the drain terminal of the first p-type transistor 608, a gate terminal for receiving half of the power supply voltage (e.g., VDDQ / 2), and a drain terminal coupled to the corresponding operating module 104. As illustrated in Figure 7, the circuit acts as a level shifter 602, thereby, for example, converting the signal from tt to hvng and from bb to hvpg. The integrated circuit design features a high-order power supply header customized for high-power applications, where the power supply voltage (VDDQ) exceeds typical device reliability thresholds (e.g., VDDQ > 0.96 V). In this setup, the PD signal operates within the VDD control domain, thereby effectively managing the power state of the module. Specifically, when PD is low (L), the module is on, and when PD is high (H), the module is off, thereby ensuring that high voltage does not jeopardize device reliability. Furthermore, the design incorporates an embedded level shifter 602 within the VDDQ high-voltage (HV) domain, referred to as Power_global, where the level shifter 602 plays a role in signal conversion. The level shifter 602 translates the input signal based on the PD state; when PD=0 (and tt=0, bb=VDD), the output hvpg is 0; conversely, when PD=VDD (and tt=VDD, bb=0), the output hvpg rises to VDDQ. This integration of the level shifter with the power supply header ensures seamless functionality across different voltage levels, maintaining stability and performance without any reliability issues, regardless of high-power conditions. The header 102 also includes the embedded level shifter 602, a crucial addition enabling the conversion from low-voltage signals to high-voltage outputs. This feature is particularly beneficial in high-voltage applications, where maintaining signal integrity at high operating voltages is critical. By integrating a level shifter within the head end, the circuit ensures that the voltage level is properly managed, thereby supporting stable and efficient high-voltage operation.

[0033] Figure 8 illustrates an example schematic diagram of a power switch 102 of the integrated circuit of Figure 1 according to some embodiments. Figure 9 illustrates example waveforms of various signals simultaneously operating the power switch of Figure 8 according to some embodiments. Each of the semiconductor dies in the integrated circuit 100 may include a plurality of operating modules 104. Each of the operating modules 104 may be coupled to the power switch 102 (e.g., a head or a foot).

[0034] In some embodiments, the power switch 102 may include a first inverter 802, a second inverter 804, a third inverter 806, a fourth inverter 808, a first p-type transistor 810, and a second p-type transistor 812. The first inverter 802 can be used to receive a first data bit (e.g., PD) of a second signal and logically invert the first data bit to provide a second data bit. The second inverter 804 can be used to receive the second data bit and logically invert the second data bit to provide a third data bit. The third inverter 806 can be used to receive the third data bit and logically invert the third data bit to provide a fourth data bit. The fourth inverter 808 can be used to receive the fourth data bit and logically invert the fourth data bit to provide a fifth data bit. The first p-type transistor 810 may have a source terminal coupled to the power network 110, a gate terminal for receiving the fifth data bit (e.g., PD2), and a drain terminal coupled to the corresponding operating module 104. The second p-type transistor 812 may have a source terminal coupled to the power network 110, a gate terminal for receiving a third data bit (e.g., PD1), and a drain terminal coupled to the corresponding operating module 104. In some embodiments, the size of the second p-type transistor 812 may be smaller than the size of the first p-type transistor 810. In some embodiments, a plurality of master heads (e.g., Mn) and a plurality of precharge heads (e.g., Mm) may be included to reduce stress on the system.

[0035] In integrated circuit design, a power supply header 102 with pre-charge characteristics can be used to enhance system efficiency and responsiveness. The power supply header 102 may include two main components: a primary header (M1) and a smaller secondary pre-charge header (M2). The size difference between M1 and M2 is strategic: the smaller M2 is designed to pre-charge the circuit, effectively reducing peak currents occurring during power transitions, resulting in improved performance and reduced stress on the system. Additionally, this design utilizes two unique power disable signals, PD1 and PD2, where PD1 operates faster than PD2, as indicated by timing parameters TPD1 and TPD2 (TPD1 > TPD2). This faster response time of PD1, functionally coupled to the pre-charge capability of M2, allows for more efficient and controlled power rise, minimizing the risk of voltage spikes and ensuring faster power delivery to the module. By aligning the speed of operation with the power requirements of the integrated circuit, this setup not only stabilizes the system during high-demand scenarios but also optimizes overall power management.

[0036] As depicted in Figure 9, at the beginning of the operating cycle at 902, the PD signal goes low. Since PD1 operates faster than PD2, at stage 904, head M1 is turned off while M2 is turned on. This configuration initiates a pre-charge phase, in which M2 supplies a limited current to power_local 104 alone. This stage 904 is critical for stabilizing the power supply wiring and preparing the circuit by gradually accumulating voltage, thus minimizing the risk of voltage spikes and electrical stress. After pre-charging, at stage 906, when both head M1 and M2 are turned on, the system transitions to the full-on phase. During this stage 906, both head terminals work together to deliver the full supply voltage to power_local 104. This two-stage power control strategy ensures effective power management, thereby reducing the likelihood of excessive current conditions and enhancing the reliability and durability of the circuit.

[0037] Figure 10 illustrates an example flowchart for testing an integrated circuit according to some embodiments of the present disclosure. Please note that method 1000 is merely an example and is not intended to limit the scope of any embodiment of the present disclosure. Therefore, it should be understood that any additional operations may be provided before, during, and after method 1000 of Figure 10, and some other operations may only be briefly described herein. Method 1000 can be used to operate integrated circuit 100, and therefore the operation of method 1000 will be discussed in conjunction with the components discussed in Figures 1 through 9.

[0038] For brevity, method 1000 begins with operation 1002 as follows: a semiconductor substrate on which a plurality of semiconductor dies 100a, 100b, 100n are disposed. Each of the plurality of semiconductor dies 100a, 100b, 100n may include a plurality of operation modules 104. A plurality of power switches 102 may be coupled to the plurality of operation modules 104 respectively. In some embodiments, the plurality of semiconductor dies 100a, 100b, 100n may be disposed on a single semiconductor substrate (e.g., a wafer). In some embodiments, each of the operation modules 104 may serve as a computing unit for artificial intelligence. In some embodiments, each of the plurality of operation modules 104 may include one of the following: a natural language processing (NLP) module, a computer vision module, a speech recognition module, a recommendation system module, a predictive analytics module, an autonomous navigation module, an anomaly detection module, an emotion detection module, a generative model module, a knowledge graph module, an optical character recognition module, a data cleaning module, a dynamic pricing module, a pose estimation module, or a time series analysis module.

[0039] Corresponding to operation 1010 in Figure 10, a power supply voltage (e.g., VDD) can be delivered to each of the operation modules 104 of each of a plurality of semiconductor dies 100a, 100b, 100n. In some embodiments, a power network 110 may be provided relative to the plurality of semiconductor dies 100a, 100b, 100n. The power network 110 can be used to provide a power supply voltage to each of the plurality of semiconductor dies 100a, 100b, 100n. In some embodiments, the power network 110 may include a plurality of interconnect structures disposed in one or more metallization layers formed above a semiconductor substrate.

[0040] Corresponding to operation 1015 in Figure 10, one or more operating modules that have failed to meet at least one requirement can be identified. The method for testing whether a module has failed to meet at least one requirement includes several key steps. Initially, all bare dies and modules within the system are initiated for a comprehensive scan test. This initial step ensures that each component is operational and ready for further diagnostics. During this phase, the current drawn by each module is closely monitored. Deviations in the current level can indicate potential faults. Specifically, if the current of a module does not meet a predefined standard requirement, the module is marked as potentially faulty.

[0041] Corresponding to operation 1020 in Figure 10, a first signal indicating one or more damaged operation modules can be received. Power control circuit 120 can be used to receive the first signal indicating that one or more operation modules of at least one of a plurality of semiconductor bare wafers have been damaged.

[0042] Corresponding to operation 1025 in Figure 10, a second signal may be sent. Based on the first signal, the power control circuit 120 may be used to send the second signal to corresponding power switches respectively coupled to one or more operating modules, so as to disconnect the power supply voltage from the one or more operating modules. In some embodiments, the power control circuit 120 may act as a head-end decoder. The power control circuit 120 may send a signal to disable the power supply voltage or disconnect the power supply voltage from the corresponding power switch of a specific module on a given bare die. In some embodiments, the first signal may include a first number (N1) of first data bits. The second signal may include a second number (N2) of second data bits. In some embodiments, N2 may be equal to... In some embodiments, N2 may be equal to the total number of power switches formed on the semiconductor substrate.

[0043] As used herein, the terms “about” and “approximately” generally indicate a given number of values ​​that may vary based on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the term “about” may indicate a given number of values ​​that may vary within, for example, 10% to 30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0044] The foregoing summarizes the features of several embodiments to enable those skilled in the art to better understand the appearance of an embodiment disclosed herein. Those skilled in the art should understand that an embodiment disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment disclosed herein, and that such equivalent constructions can be modified, replaced, and substituted in various ways herein without departing from the spirit and scope of an embodiment disclosed herein. [Simplified Explanation of the Diagram]

[0004] The present disclosure of an embodiment is best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, according to industry standard practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates an example schematic diagram of an integrated circuit according to some embodiments. Figure 2 illustrates an example schematic diagram of a power control circuit of the integrated circuit of Figure 1 according to some embodiments. Figure 3 illustrates an example schematic diagram of an integrated circuit according to some embodiments and example waveforms of various signals during operation of the integrated circuit. Figure 4 illustrates an example schematic diagram of a power switch of the integrated circuit of Figure 1 according to some embodiments. Figure 5 illustrates an example schematic diagram of a power switch of the integrated circuit of Figure 1 according to some embodiments. Figure 6 illustrates an example schematic diagram of a power switch of the integrated circuit of Figure 1 according to some embodiments. Figure 7 illustrates an example schematic diagram of a level shifter of the power switch of Figure 6 according to some embodiments. Figure 8 illustrates an example schematic diagram of a power switch of the integrated circuit of Figure 1 according to some embodiments. Figure 9 illustrates example waveforms of various signals simultaneously operating the power switch of Figure 8 according to some embodiments. Figure 10 illustrates an example flowchart for testing integrated circuits according to some embodiments.

Claims

1. An integrated circuit comprising: a plurality of semiconductor dies disposed on a single semiconductor substrate, wherein each of the semiconductor dies includes a plurality of operating modules and a plurality of power switches respectively coupled to the operating modules; a power network disposed relative to the semiconductor dies and configured to provide a power voltage to each of the semiconductor dies; and a power control circuit disposed on the semiconductor substrate; wherein the power control circuit is configured to: receive a first signal indicating that one or more operating modules of at least one of the semiconductor dies are damaged; and based on the first signal, send a second signal to the corresponding power switches respectively coupled to one or more of the operating modules to disconnect the power voltage from being provided to one or more of the operating modules.

2. The integrated circuit as claimed in claim 1, wherein each of the operating modules comprises one of the following: a natural language processing module, a computer vision module, a speech recognition module, a recommendation system module, a predictive analytics module, an autonomous navigation module, an anomaly detection module, an emotion detection module, a generative model module, a knowledge graph module, an optical character recognition module, a data cleaning module, a dynamic pricing module, a pose estimation module, or a temporal series analysis module.

3. The integrated circuit as claimed in claim 1, wherein the first signal includes a first number (N1) of first data bits, and the second signal includes a second number (N2) of second data bits.

4. The integrated circuit as described in claim 3, wherein N2 is equal to 1.

5. The integrated circuit as claimed in claim 3, wherein the power control circuit comprises: a plurality of first inverters, each of the first inverters being configured to logically invert a corresponding one of the first data bits to provide a first number of third data bits; a plurality of NAND gates, each of the NAND gates being configured to input a corresponding first number of third data bits to provide a second number of fourth data bits; and a plurality of second inverters, each of the second inverters being configured to logically invert a corresponding one of the second number of fourth data bits to provide a corresponding one of the second data bits.

6. The integrated circuit as claimed in claim 1, wherein each of the power switches comprises: A first inverter is used to receive a first data bit of the second signal and logically invert the first data bit to provide a second data bit; A second inverter for receiving the second data bit and logically inverting the second data bit to provide a third data bit; and a p-type transistor having a source terminal coupled to the power network, a gate terminal for receiving the third data bit, and a drain terminal coupled to the corresponding operating module.

7. The integrated circuit as claimed in claim 1, wherein each of the power switches comprises: A first inverter is used to receive a first data bit of the second signal and logically invert the first data bit to provide a second data bit; A second inverter for receiving the second data bit and logically inverting the second data bit to provide a third data bit; a first p-type transistor having a source terminal coupled to the power network, a gate terminal for receiving the third data bit, and a drain terminal; And a second p-type transistor, the second p-type transistor having a source terminal coupled to the drain terminal of the first p-type transistor, a gate terminal for receiving half of the power supply voltage, and a drain terminal coupled to the corresponding operating module.

8. The integrated circuit as claimed in claim 1, wherein each of the power switches comprises: A first inverter is used to receive a first data bit of the second signal and logically invert the first data bit to provide a second data bit; A second inverter for receiving the second data bit and logically inverting the second data bit to provide a third data bit; a third inverter for receiving the third data bit and logically inverting the third data bit to provide a fourth data bit; a fourth inverter for receiving the fourth data bit and logically inverting the fourth data bit to provide a fifth data bit; a first p-type transistor having a source terminal coupled to the power network, a gate terminal for receiving the fifth data bit, and a drain terminal coupled to the corresponding operating module; And a second p-type transistor, the second p-type transistor having a source terminal coupled to the power network, a gate terminal for receiving the third data bit and a drain terminal coupled to the corresponding operating module.

9. An integrated circuit comprising: a plurality of semiconductor dies disposed on a single semiconductor substrate, each of the semiconductor dies including a plurality of operating modules, and a plurality of power switches respectively coupled to the operating modules; wherein at least one of the power switches is configured to selectively decouple a voltage carried via a power network from the corresponding operating module based on a first signal indicating that the corresponding operating module is damaged.

10. A method for testing an integrated circuit, comprising the steps of: providing a semiconductor substrate with a plurality of semiconductor dies disposed on the semiconductor substrate, wherein each of the semiconductor dies includes a plurality of operating modules and a plurality of power switches respectively coupled to the operating modules; delivering a power supply voltage to each of the operating modules of each of the semiconductor dies; identifying one or more of the operating modules that have failed to meet at least one requirement; receiving a first signal indicating one or more of the damaged operating modules; and sending a second signal to the corresponding power switches respectively coupled to one or more of the operating modules to disconnect the power supply voltage from being supplied to one or more of the operating modules.

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