Demodulation circuit and digital isolator

Abstract

This invention provides a demodulation circuit and a digital isolator, wherein the demodulation circuit includes a waveform conditioner, a first counter, a second counter, and an SR latch. The waveform conditioner generates a regulated modulation signal based on a differential isolation modulation signal generated by modulating an input data signal with a carrier clock signal. The first counter counts the periods of the regulated modulation signal to generate a set signal. The second counter counts the periods of a reference clock signal to generate a reset signal. The SR latch includes: a set terminal for receiving the set signal; a reset terminal for receiving a reset signal; and an output terminal for outputting the demodulated output signal. The SR latch is triggered by the set signal to pull the demodulated output signal high and triggered by the reset signal to pull the demodulated output signal low.

Description

[Technical Field]

[0001] This invention relates to a demodulation circuit, and more specifically, to a demodulation circuit used in a digital isolator. [Previous Technology]

[0002] A digital isolator is a device that provides electrical isolation between two digital systems while enabling data transfer. This isolation is crucial for the safety and noise suppression of many electronic systems, especially in industrial and automotive applications. A digital isolator allows one circuit to transmit digital signals to another circuit through an isolation barrier without physical contact or direct electrical connection. Isolation barriers are typically implemented using techniques such as capacitive coupling, magnetic coupling, or optical isolation.

[0003] One of the key challenges facing digital isolators is meeting common-mode transient immunity (CMTI) requirements. Common-mode transients refer to sudden voltage spikes or fluctuations between the circuit grounds on both sides of the isolation barrier. If not handled properly, these transients can cause errors in digital isolators. [Summary of the Invention]

[0004] One aspect of the present invention provides a demodulation circuit. The demodulation circuit includes a waveform conditioner, a first counter, a second counter, and a set / reset (SR) latch. The waveform conditioner is configured to generate a normalized modulation signal based on a pair of differential isolation modulation signals. The differential isolation modulation signal is generated by modulating an input data signal with a carrier clock signal. The first counter includes a clock input for receiving the normalized modulation signal, a reset input, and an output for outputting a set signal. The second counter includes a clock input for receiving a reference clock signal, a reset input for receiving the normalized modulation signal, and a first output for outputting a reset signal. The SR latch includes a set input connected to the output of the first counter, a reset input connected to the output of the second counter, and an output for outputting a demodulated output signal. The first counter generates a set signal by counting the number of cycles of the regularized modulation signal and triggers the SR latch to pull up the demodulated output signal. The second counter generates a reset signal by counting the number of cycles of the reference clock signal and triggers the SR latch to pull down the demodulated output signal.

[0005] Another aspect of the present invention provides a digital isolator. The digital isolator includes the aforementioned demodulation circuit and isolation circuit. The isolation circuit receives a differentially modulated input signal pair generated by modulating an input data signal with a carrier clock signal, and outputs the differentially isolated modulated signal pair.

[0006] The purpose of this invention is to provide a demodulation circuit and a digital isolator to meet the common-mode transient immunity (CMTI) requirements.

[0007] To achieve the above objective, the present invention provides a demodulation circuit, comprising: a waveform conditioner configured to generate an regulated modulation signal based on a pair of differential isolation modulation signals, wherein the differential isolation modulation signals are generated by modulating an input data signal with a carrier clock signal; a first counter comprising: a clock input terminal configured to receive the regulated modulation signal; a reset terminal; and an output terminal configured to output a set signal; and a second counter comprising: a clock input terminal configured to receive a reference clock signal; a reset terminal configured to receive the regulated modulation signal; and a first output terminal configured to receive a set signal; and a second counter comprising: a clock input terminal configured to receive a reference clock signal; a reset terminal configured to receive the regulated modulation signal; and a first output terminal configured to receive a set signal; and a second counter comprising: a clock input terminal configured to receive a reference clock signal; a reset terminal configured to receive the regulated modulation signal; and a first output terminal configured to receive a set signal; and a second counter configured to receive a set signal; and a second counter configured to receive a set signal; and a third counter configured to receive a set signal; and a fourth counter configured to receive a set signal; and a fifth counter configured to receive a set signal; and a sixth counter configured to receive a set signal; and a seventh ... sixth counter configured to receive a set signal; and a seventh counter configured to receive a set signal; and a sixth counter configured to receive a set signal; and a seventh counter configured to receive a set signal The system comprises: a set terminal coupled to the output of the first counter; a reset terminal coupled to the first output of the second counter; and an output terminal configured to output a demodulated output signal; wherein the first counter is configured to count the period of the modulated signal to generate the set signal and trigger the first SR latch to pull the demodulated output signal high, and the second counter is configured to count the period of the reference clock signal to generate the reset signal and trigger the first SR latch to pull the demodulated output signal low.

[0008] For example, the second counter further includes a second output terminal coupled to the reset terminal of the first counter, and the second counter is further configured to output a turn-on reset signal through the second output terminal when the duration for which the regulated modulation signal remains at a logic low level exceeds the duration of a first predetermined number of cycles of the reference clock signal.

[0009] For example, the first counter is configured to generate the set signal when a second predetermined number of cycles of the regulated modulation signal has been counted and the turn-on reset signal has not been received.

[0010] For example, the second counter is configured to generate the reset signal when the regulated modulation signal is held at a logic low level and the count reaches a third predetermined number of cycles of the reference clock signal.

[0011] For example, the first predetermined number of cycles, the second predetermined number of cycles, and the third predetermined number of cycles can be programmed.

[0012] For example, the first counter further includes a counter register, and the output of the first counter is coupled to the most significant bit of the counter register to output the set signal.

[0013] For example, the second counter further includes a counter register, and a first output of the second counter is coupled to the most significant bit of the counter register to output the reset signal.

[0014] As an example, the demodulation circuit further includes an OR gate, comprising: a plurality of input terminals coupled to a plurality of most significant bits of the counter register; and an output terminal coupled to the reset terminal of the first counter, configured to output an on reset signal.

[0015] For example, the frequency of the reference clock signal is equal to the frequency of the carrier clock signal.

[0016] For example, when the differential isolation modulation signal periodically jumps, the waveform adjuster adjusts the duty cycle of the adjusted modulation signal to be approximately equal to 50%.

[0017] For example, the waveform conditioner includes: a hysteresis comparator, including: a non-inverting input configured to receive a first isolation modulation signal in the differential isolation modulation signal; an inverting input configured to receive a second isolation modulation signal in the differential isolation modulation signal; and an output; a D flip-flop, including: a data input configured to receive a power supply voltage; a clock input coupled to the output of the hysteresis comparator; a reset input; and an output configured to output the regulated modulation signal; and a delay circuit, including: an input coupled to the output of the D flip-flop; and an output coupled to the reset input of the D flip-flop.

[0018] For example, the delay circuit includes multiple cascaded inverters.

[0019] For example, the delay circuit includes: a resistor including: a first terminal coupled to an input terminal of the delay circuit; a second terminal coupled to an output terminal of the delay circuit; and a capacitor including: a first terminal coupled to a second terminal of the resistor; and a second terminal coupled to a ground node.

[0020] For example, the waveform conditioner includes: a first hysteresis comparator, including: a non-inverting input configured to receive a first isolated modulation signal in the differential isolated modulation signal; an inverting input configured to receive a second isolated modulation signal in the differential isolated modulation signal; and an output; a second hysteresis comparator, including: a non-inverting input configured to receive the second isolated modulation signal; an inverting input configured to receive the first isolated modulation signal; and an output; and a second SR latch, including: a set input coupled to the output of the second hysteresis comparator; a reset input coupled to the output of the first hysteresis comparator; and an output configured to output the adjusted modulation signal.

[0021] The present invention also provides a digital isolator, comprising: a demodulation circuit as described above; and an isolation circuit configured to receive a pair of differentially modulated input signals generated by modulating an input data signal with a carrier clock signal, and output the differentially isolated modulated signal pair.

[0022] For example, the second counter further includes a second output terminal coupled to the reset terminal of the first counter, and the second counter is further configured to output an on reset signal through the second output terminal when the duration of the adjusted modulation signal being held at a logic low level exceeds the duration of a first predetermined number of cycles of the reference clock signal.

[0023] For example, the isolation circuit includes: a first capacitor, including: a first terminal configured to receive a first modulation input signal in the differential modulation input signal; a second terminal; a second capacitor, including: a first terminal configured to receive a second modulation input signal in the differential modulation input signal; a second terminal; a third capacitor, including: a first terminal coupled to a second terminal of the first capacitor; a second terminal configured to output a first isolation modulation signal in the differential isolation modulation signal; a fourth capacitor, including: a first terminal coupled to a second terminal of the second capacitor; a second terminal configured to output a second isolation modulation signal in the differential isolation modulation signal; a first resistor, including: a first terminal coupled to a second terminal of the third capacitor; a second terminal; and a second resistor, including: a first terminal coupled to a second terminal of the fourth capacitor; a second terminal coupled to a second terminal of the first resistor.

[0024] For example, the isolation circuit further includes: a third resistor, comprising: a first terminal configured to receive the first modulation input signal; a second terminal coupled to a first terminal of the first capacitor; and a fourth resistor, comprising: a first terminal configured to receive the second modulation input signal; and a second terminal coupled to a first terminal of the second capacitor.

[0025] For example, the digital isolator further includes a modulation circuit configured to generate the differential modulation input signal by modulating the input data signal with the carrier clock signal.

[0026] For example, the modulation circuit includes: a gate, including: a first input configured to receive the carrier clock signal; a second input configured to receive the input data signal; and an output configured to output a first modulation input signal in the differential modulation input signal; and an inverter, including: an input coupled to the output of the gate; and an output configured to output a second modulation input signal in the differential modulation input signal.

[0027] In summary, compared with the prior art, the digital isolator and demodulation circuit provided by the present invention use two counters to control the on and off times of the demodulated output signal. By utilizing the time measurement capability of the counters, the demodulation circuit can ignore noise caused by different types of common-mode transients, thereby reducing glitches in the demodulated output signal and enabling the digital isolator to achieve high CMTI. In addition, since the on-state glitches threshold, the off-state glitches threshold, and the maximum allowable off-state time can be programmed through the counters, this also provides great flexibility for circuit design.

[0028] The present invention can be more fully understood by referring to the detailed description and the scope of the claims, wherein the same numbers throughout the text refer to similar elements.

Implementation Method

[0030] The following description is taken in conjunction with the accompanying drawings, which form part of this specification and illustrate embodiments of the invention, but the invention is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to form other embodiments.

[0031] The terms "one embodiment," "embodiment," "exemplary embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments must include that particular feature, structure, or characteristic. In addition, repeated use of the phrase "in this embodiment" does not necessarily refer to the same embodiment.

[0032] To make the present invention fully clear, the following description will provide detailed steps and structures. Obviously, the implementation of the present invention is not limited to the specific details known to those skilled in the art. Furthermore, to avoid unnecessarily limiting the present invention, known structures and steps will not be repeated. Preferred embodiments of the present invention will be described in detail below, but in addition to the detailed description, the present invention can also be widely implemented in other embodiments. The scope of the present invention is not limited by the detailed description, but is defined by the claims.

[0033] FIG1 illustrates a digital isolator 100 according to a first embodiment of the present invention. The digital isolator 100 includes a modulation circuit 110, an isolation circuit 120, and a demodulation circuit 130. The digital isolator 100 provides isolation between the input side (such as the side where the modulation circuit 110 is located) and the output side (such as the side where the demodulation circuit 130 is located) through a capacitive isolation barrier in the isolation circuit 120. In some embodiments, the capacitor-based isolation circuit 120 can be regarded as a high-pass filter or a band-pass filter that can block low-frequency noise. In this case, in order to enable data transmission across the capacitive isolation barrier, the modulation circuit 110 modulates the input data signal SIGDIN with a carrier clock signal SIGCRCK having a carrier frequency, converting the low-frequency SIGDIN into a modulated input signal SIGMA1 and its complementary signal SIGMA2. Since SIGMA1 and SIGMA2 are both high-frequency signals, they can pass through the filter of the isolation circuit 120.

[0034] Figure 2 shows the signal timing diagram of the digital isolator 100. As shown in Figure 2, during period P1, the input data signal SIGDIN is at a logic high level, and the modulation circuit 110 modulates the input data signal SIGDIN into high-frequency modulation input signals SIGMA1 and SIGMA2, which are at the same frequency as the carrier clock signal SIGCRCK. Furthermore, during period P2, the input data signal SIGDIN is at a logic low level, and the modulation circuit 110 maintains the modulation input signal SIGMA1 at a logic low level and the modulation input signal SIGMA2 at a logic high level.

[0035] Isolation circuit 120 receives modulation input signals SIGMA1 and SIGMA2, and outputs isolated modulation signals SIGMB1 and SIGMB2 after filtering. Subsequently, demodulation circuit 130 demodulates isolated modulation signals SIGMB1 and SIGMB2 to obtain a demodulated output signal SIGDOUT, similar to the input data signal SIGDIN, as shown in FIG2. Thus, data transmission across both sides of the isolation barrier is realized. In this embodiment, demodulation circuit 130 uses two counters (first counter 134 and second counter 136) to control the setting and resetting of SR latch 138, thereby generating demodulated output signal SIGDOUT. By utilizing the time measurement capability of first counter 134 and second counter 136, demodulation circuit 130 can ignore noise caused by common-mode transients, thereby reducing glitches in demodulated output signal SIGDOUT and enabling digital isolator 100 to achieve high CMTI.

[0036] The following will describe more details and structures of the modulation circuit 110, the isolation circuit 120 and the demodulation circuit 130.

[0037] As shown in Figure 1, the modulation circuit 110 includes a gate 112 and an inverter 114. The gate 112 includes: a first input terminal for receiving a carrier clock signal SIGCRCK, a second input terminal for receiving an input data signal SIGDIN, and an output terminal for outputting a modulation input signal SIGMA1. The inverter 114 includes: an input terminal coupled to the output terminal of the gate 112, and an output terminal for outputting a modulation input signal SIGMA2. In this case, the modulation input signal SIGMA2 output by the inverter 114 and the modulation input signal SIGMA1 output by the gate 112 are complementary, and the modulation input signals SIGMA1 and SIGMA2 can be regarded as a differential modulation input signal pair.

[0038] In this embodiment, modulation is implemented by gate 112. However, in other embodiments, modulation can also be implemented by other logic gates besides gate 112. For example, an inverting gate can be used instead of gate 112 for data modulation. Furthermore, in some embodiments, to compensate for the delay introduced by inverter 114 and to synchronize the modulation input signal SIGMA1 and modulation input signal SIGMA2, more inverters and / or non-inverting transmission gates can be added to the input and output paths of the modulation circuit 110.

[0039] The isolation circuit 120 receives differential modulation input signal pairs SIGMA1 and SIGMA2, and outputs differential isolation modulation signal pairs SIGMB1 and SIGMB2. As shown in Figure 1, the isolation circuit 120 includes resistors R1 and R2, and capacitors C1, C2, C3 and C4.

[0040] Capacitor C1 includes: a first terminal for receiving the modulation input signal SIGMA1 and a second terminal. Capacitor C2 includes: a first terminal for receiving the modulation input signal SIGMA2 and a second terminal. Capacitor C3 includes: a first terminal coupled to the second terminal of capacitor C1 and a second terminal for outputting the isolation modulation signal SIGMB1. Capacitor C4 includes: a first terminal coupled to the second terminal of capacitor C2 and a second terminal for outputting the isolation modulation signal SIGMB2. Resistor R1 includes: a first terminal coupled to the second terminal of capacitor C3 and a second terminal. Resistor R2 includes: a first terminal coupled to the second terminal of capacitor C4 and a second terminal coupled to the second terminal of resistor R1.

[0041] In the isolation circuit 120, the capacitor-resistor network formed by capacitors C1, C3, C2, C4 and resistors R1, R2 can block low-frequency noise and distinguish the modulation input signals SIGMA1 and SIGMA2 as signal transients (i.e., isolate the modulation signals SIGMB1 and SIGMB2). In some embodiments, the capacitance values ​​of capacitors C1, C2, C3, and C4 can be the same, for example, but not limited to about 70 fF, and the resistance values ​​of resistors R1 and R2 can be the same, for example, but not limited to less than or equal to 150 ohms (Ω).

[0042] Furthermore, in some embodiments, the modulation circuit 110 and capacitors C1 and C2 are arranged on one chip, while the demodulation circuit 130 and capacitors C3 and C4 are arranged on another chip, thereby ensuring isolation between the input stage and the output stage of the digital isolator 100. In this case, the second ends of capacitors C1 and C2 are coupled to the first ends of capacitors C3 and C4, respectively, via bonding wires.

[0043] As shown in Figure 1, the isolation circuit 120 further includes resistors R3 and R4. Resistor R3 is coupled between capacitor C1 and modulation circuit 110, and resistor R4 is coupled between capacitor C2 and modulation circuit 110. Resistor R3 includes: a first terminal coupled to the output of gate 112 to receive the modulation input signal SIGMA1, and a second terminal coupled to the first terminal of capacitor C1. Resistor R4 includes: a first terminal coupled to the output of inverter 114 to receive the modulation input signal SIGMA2, and a second terminal coupled to the first terminal of capacitor C2.

[0044] Resistors R3 and R4 are used to increase the time constant of the isolation circuit 120, so that the glitches at the input of the hysteresis comparator 1321 in the demodulation circuit 130 decrease more slowly, thereby enabling the hysteresis comparator 1321 to respond in a timely manner. In some embodiments, the resistance values ​​of resistors R3 and R4 can be the same, for example, but not limited to 500 ohms (Ω).

[0045] Furthermore, as shown in FIG1, the isolation circuit 120 also includes capacitors C5 and C6. Capacitor C5 is the input capacitor of the hysteresis comparator 1321, and capacitor C6 is used to hold and indicate the common-mode voltage of the differential isolation modulation signals SIGMB1 and SIGMB2. In some embodiments, capacitor C5 is crucial for the hysteresis comparator 1321 to receive input signals within the amplitude range. In some embodiments, the capacitance value of capacitor C5 should be smaller than the capacitance values ​​of capacitors C1, C2, C3, or C4.

[0046] The demodulation circuit 130 includes a waveform conditioner 132, a first counter 134, a second counter 136, and a set / reset (SR) latch 138. The waveform conditioner 132 generates a modulated signal SIGRM based on the differential isolation modulation signals SIGMB1 and SIGMB2. When the input data signal SIGDIN is at a logic high level and is modulated by the carrier clock signal SIGCRCK, the first counter 134 generates a set signal SIGSET and triggers the SR latch 138 to pull up the demodulated output signal SIGDOUT. When the input data signal SIGDIN is at a logic low level, the second counter 136 generates a reset signal SIGRST and triggers the SR latch 138 to pull down the demodulated output signal SIGDOUT.

[0047] The waveform conditioner 132 includes a hysteresis comparator 1321, a D flip-flop 1322, and a delay circuit 1323. The hysteresis comparator 1321 includes: a non-inverting input for receiving the isolated modulation signal SIGMB1; an inverting input for receiving the isolated modulation signal SIGMB2; and an output. The D flip-flop 1322 includes: a data input for receiving the power supply voltage VCC; a clock input coupled to the output of the hysteresis comparator 1321; a reset input; and an output for outputting the regulated modulation signal SIGRM. The delay circuit 1323 includes: an input coupled to the output of the D flip-flop 1322; and an output coupled to the reset input of the D flip-flop 1322.

[0048] When the voltage at the non-inverting input of the hysteresis comparator 1321 is higher than the voltage at the inverting input by a threshold value, its output is at a high level; when the voltage at the inverting input is higher than the voltage at the non-inverting input by a threshold value, its output is at a low level. Therefore, the hysteresis comparator 1321 converts signal transients (i.e., isolated modulation signals SIGMB1 and SIGMB2) into pulses to trigger the D flip-flop 1322.

[0049] Each time the D flip-flop 1322 is triggered to output a high-order logic bit, the delay circuit 1323 resets the D flip-flop 1322 after a fixed delay. Since the isolated modulation signals SIGMB1 and SIGMB2 periodically transition during signal modulation, the waveform conditioner 132 can generate a regulated modulation signal SIGRM with a uniform duty cycle through the fixed delay provided by the delay circuit 1323. In some embodiments, the waveform conditioner 132 can adjust the duty cycle of the regulated modulation signal SIGRM to approximately 50%, but the invention is not limited thereto.

[0050] The regulated modulation signal SIGRM is then received as a clock signal by the first counter 134 and as a reset signal by the second counter 136. Specifically, the first counter 134 includes: a clock input for receiving the regulated modulation signal SIGRM; a reset input; and an output for outputting a set signal SIGSET. The second counter 136 includes: a clock input for receiving a reference clock signal SIGRFCK; a reset input for receiving the regulated modulation signal SIGRM; a first output for outputting a reset signal SIGRST; and a second output coupled to the reset input of the first counter 134 for outputting a conduction reset signal SIGONRST. The SR latch 138 includes: a set input coupled to the output of the first counter 134; a reset input coupled to the output of the second counter 136; and an output for outputting a demodulated output signal SIGDOUT.

[0051] When the regulated modulation signal SIGRM continues to change, it may mean that the input data signal SIGDIN is at a logic high level and is modulated by the carrier clock signal SIGCRCK. At this time, the first counter 134 continuously counts the periods of the regulated modulation signal SIGRM to determine whether its voltage change is caused by signal modulation or transient noise. The first counter 134 generates a set signal SIGSET based on the counting result, and triggers the SR latch 138 to pull up the demodulated output signal SIGDOUT when the count reaches a predetermined number of periods.

[0052] For example, in period P1 of Figure 2, since the input data signal SIGDIN is modulated by the carrier clock signal SIGCRCK, the regulated modulation signal SIGRM continuously jumps. At this time, the first counter 134 generates a logic high-level set signal SIGSET after counting 8 periods of the regulated modulation signal SIGRM, and the SR latch 138 will pull the demodulated output signal SIGDOUT high to the logic high level at time T1. In other words, by counting the number of periods of the regulated modulation signal SIGRM, the first counter 134 can wait for a period of time after detecting its jump before sending the set signal SIGSET, thereby ensuring that the voltage jump is caused by stable data modulation and reducing glitches caused by unstable transients. Therefore, in this invention, the number of periods of the regulated modulation signal SIGRM that the first counter 134 needs to count before generating the set signal SIGSET can also be called the conduction glitch threshold number.

[0053] In some embodiments, the frequency of the carrier clock signal SIGCRCK is, but is not limited to, 500MHz. By counting eight cycles of the modulated signal SIGRM, the first counter 134 will result in an input-output delay of 16ns, which is very short and acceptable in most cases. However, in some embodiments, the conduction de-glitch threshold number can be programmed for the first counter 134 and adjusted as needed.

[0054] Furthermore, when the regulated modulation signal SIGRM remains at a logic low level (e.g., period P2 in Figure 2), it may mean that the input data signal SIGDIN is also at a logic low level. In this case, the second counter 136 counts the periods of the reference clock signal SIGRFCK to measure the duration for which the regulated modulation signal SIGRM remains at a logic low level, thereby determining whether its low-level state is caused by the input data signal SIGDIN or transient noise. Therefore, the second counter 136 generates a reset signal SIGRST based on the counting result and triggers the SR latch 138 to pull low the demodulated output signal SIGDOUT when the count reaches a predetermined number of periods.

[0055] For example, in period P2 of Figure 2, the regulated modulation signal SIGRM remains at a low logic level, and the second counter 136 generates a high logic level reset signal SIGRST after counting eight cycles of the reference clock signal SIGRFCK. Therefore, the SR latch 138 is reset by the reset signal SIGRST and pulls the demodulated output signal SIGDOUT low at time T2. Thus, the demodulated output signal SIGDOUT can reproduce the waveform of the input data signal SIGDIN after the brief input-output delay introduced by the second counter 136 counting. In some embodiments, the de-glitch threshold number (i.e., the number of cycles of the reference clock signal SIGRFCK that need to be counted before the second counter 136 generates the reset signal SIGRST) is programmable and can be adjusted as needed.

[0056] In some embodiments, the frequency of the reference clock signal SIGRFCK may be the same as the frequency of the carrier clock signal SIGCRCK, and the reference clock signal SIGRFCK may be generated by an oscillator different from the oscillator that generates the carrier clock signal SIGCRCK, since the modulation circuit 110 and the demodulation circuit 130 are arranged in different wafers. In some embodiments, the reference clock signal SIGRFCK may be generated by an external oscillator, but the invention is not limited thereto. Furthermore, in FIG. 2 (and subsequently FIG. 3 and 4), the reference clock signal SIGRFCK is in phase with the carrier clock signal SIGCRCK, but the invention is not limited thereto. In some embodiments, there may be a phase difference between the reference clock signal SIGRFCK and the carrier clock signal SIGCRCK, resulting in slight edge transition inaccuracies, but this will not affect the degluing and demodulation functions of the demodulation circuit 130.

[0057] In this embodiment, the first counter 134 may include a 4-bit counter register for recording the current count value. In this case, as the first counter 134 continuously counts the period of the modulated signal SIGRM after adjustment, the counter register may overflow, and the count value may return to zero. When the count value returns to zero, the first counter 134 will stop outputting the logic high-level set signal SIGSET, as shown in Figure 2. Since the SR latch 138 can be implemented by an inverse OR gate, its output demodulated output signal SIGDOUT will remain at the logic high level as long as the reset signal SIGRST is not received. Similarly, the second counter 136 may also include a 4-bit counter register for recording the current count value, and the count value may return to zero when the counter register overflows. Therefore, the second counter 136 will not continuously output the logic high-level reset signal SIGRST as in period P2 of Figure 2. However, as mentioned above, the SR latch 138 will remain at the logic low level until the next set signal SIGSET is received.

[0058] Since the first counter 134 can generate a set signal SIGSET to trigger the SR latch 138 to pull up the demodulated output signal SIGDOUT after counting a predetermined number of cycles of the modulated signal SIGRM, and the second counter 136 can generate a reset signal SIGRST to trigger the SR latch 138 to pull down the demodulated output signal SIGDOUT after counting a predetermined number of cycles of the reference clock signal SIGRFCK, the glitches in the demodulated output signal SIGDOUT caused by common-mode transients can be reduced.

[0059] Figure 3 shows the signal timing diagram of the digital isolator 100, demonstrating the glitching capability in an example scenario. As shown in Figure 3, in the initial period P1, the input data signal SIGDIN is at a logic high level, and the regulated modulation signal SIGRM continuously changes. Subsequently, after counting 8 periods up to the regulated modulation signal SIGRM, the first counter 134 generates a logic high level set signal SIGSET, and triggers the SR latch 138 to pull up the demodulated output signal SIGDOUT at time T1.

[0060] At time T2 in Figure 3, a common-mode transient occurs, causing the regulated modulation signal SIGRM to lose 5 pulses. In this case, when the regulated modulation signal SIGRM becomes logic low, the second counter 136 will start counting the period of the reference clock signal SIGRFCK. However, when the second counter 136 counts to the 5th period of the reference clock signal SIGRFCK, the second counter 136 will be reset because the regulated modulation signal SIGRM becomes logic high again at time T3. Since the second counter 136 has not reached the glitch cutoff count (e.g., 8), a logic high reset signal SIGRST will not be generated, and the demodulated output signal SIGDOUT will remain at logic high throughout the entire time period shown in Figure 3, unaffected by the common-mode transient. In other words, the counting scheme of the second counter 136 can avoid glitches caused by common-mode transients, thereby improving the CMTI of the digital isolator 100. The counting scheme of the first counter 134 can also achieve glitch cutoff capability.

[0061] Furthermore, common-mode transients can not only cause pulse loss but also trigger unexpected pulses. Therefore, the second counter 136 can also generate a turn-on reset signal SIGONRST to reset the first counter 134 when an unexpected pulse is generated by a common-mode transient. Specifically, since the frequency of the unexpected pulse may be low and the duration of the logic low level may be long, the second counter 136 can measure the off-time of the regulated modulation signal SIGRM (i.e., the time it holds at the logic low level) and output the turn-on reset signal SIGONRST through the second output terminal when the off-time exceeds the maximum allowable off-time (e.g., the duration corresponding to a predetermined number of cycles of the reference clock signal SIGRFCK).

[0062] Figure 4 shows the signal timing diagram of the digital isolator 100, demonstrating degluing capability in another example scenario. As shown in Figure 4, the input data signal SIGDIN remains at a logic low level, the modulation input signal SIGMA1 remains at a logic low level, and the modulation input signal SIGMA2 remains at a logic high level. However, a common-mode transient occurs at time T1, resulting in 10 unexpected pulses in the regulated modulation signal SIGRM. At this time, the number of unexpected pulses exceeds the predetermined degluing threshold number of the first counter 134 (e.g., 8 cycles of the regulated modulation signal SIGRM). However, since the off-time of each of these 10 pulses exceeds the predetermined maximum allowable off-time of the second counter 136 (e.g., 2 cycles of the reference clock signal SIGRFCK), the second counter 136 will reset the first counter 134 during each pulse.

[0063] Therefore, the count value of the first counter 134 will remain at 1 during these 10 pulses, and will not reach the conduction de-glitch threshold number (e.g., 8). Therefore, the first counter 134 will not generate the set signal SIGSET during the entire time period shown in Figure 4. At this time, even if a common-mode transient occurs, the demodulated output signal SIGDOUT will remain consistent with the input data signal SIGDIN, maintaining a low logic level. In some embodiments, the number of cycles of the reference clock signal SIGRFCK used by the second counter 136 to determine the maximum allowable off-time is programmable and can be adjusted as needed.

[0064] In other words, for the first counter 134 to generate the set signal SIGSET and trigger the SR latch 138 to pull up the demodulated output signal SIGDOUT, it must count at least 8 cycles of the regulated modulation signal SIGRM, and the off-time in each cycle must not exceed 2 cycles of the reference clock signal SIGRFCK. For example, although the turn-on reset signal SIGONRST is not shown in Figures 2 and 3, in cycle P1 of Figures 2 and 3, since the off-time of each cycle of the regulated modulation signal SIGRM is approximately 1 ns (shorter than 2 cycles of the reference clock signal SIGRFCK), the second counter 136 will not generate the turn-on reset signal SIGONRST to reset the first counter 134. Therefore, the first counter 134 will count from the first cycle of the regulated modulation signal SIGRM to the eighth cycle, and then generate the set signal SIGSET to trigger the SR latch 138 to pull up the demodulated output signal SIGDOUT.

[0065] In some embodiments, the set signal SIGSET generated by the first counter 134 can be controlled by referring to the most significant bit of its counter register. Similarly, the reset signal SIGRST and the on-reset signal SIGONRST generated by the second counter 136 can also be controlled by referring to certain bits of its counter register.

[0066] Figure 5 shows a digital isolator 200 according to a second embodiment of the present invention. The difference between digital isolator 200 and digital isolator 100 is that the output terminals of the first counter 234 and the second counter 236 in the demodulation circuit 230 can be coupled to the selection position in its counter register.

[0067] As shown in Figure 5, the first counter 234 includes a 4-bit counter register 2342 for recording the current count value. The current count value can be represented by bits A[3] to A[0], and the output of the first counter 234 is coupled to the most significant bit A[3] of the counter register 2342 for outputting a set signal SIGSET when the count value reaches 8. However, the present invention is not limited thereto. In other embodiments, the size of the counter register 2342 can be determined according to the conduction de-glitch threshold number used by the first counter 234.

[0068] In addition, as shown in Figure 5, the second counter 236 includes a 4-bit counter register 2362 for recording the current count value. The current count value can be represented by bit B[3] to bit B[0], and the first output terminal of the second counter 236 is coupled to the most significant bit B[3] of the counter register 2362 for outputting a reset signal SIGRST when the count value reaches 8.

[0069] In addition, in the second embodiment, the demodulation circuit 230 includes an OR gate 239. The OR gate 239, in conjunction with the second counter 236, can generate an on-reset signal SIGONRST for resetting the first counter 234. The OR gate 239 has multiple inputs (e.g., three inputs) coupled to multiple most significant bits (e.g., bits B[3] to B[1]) of the counter register 2362. In this case, the OR gate 239 outputs an on-reset signal SIGONRST at a logic high level to reset the first counter 234 as long as the regulated modulation signal SIGRM remains at a logic low level for more than two cycles of the reference clock signal SIGRFCK. However, the invention is not limited thereto. In other embodiments, the size of the counter register 2362 can be adjusted according to the number of off-ghosting thresholds used by the second counter 236, and the bits coupled to the OR gate 239 can be selected according to the maximum allowable off-time measured by the second counter 236.

[0070] Figure 6 illustrates a digital isolator 300 according to a third embodiment of the present invention. The difference between digital isolator 300 and digital isolator 100 is that the delay circuit 3323 of the waveform conditioner 332 in the demodulation circuit 330 uses a resistor R332 and a capacitor C332 instead of the inverter INV in the delay circuit 1323. As shown in Figure 6, resistor R332 includes a first terminal coupled to the input of delay circuit 3323 and a second terminal coupled to the output of delay circuit 3323. Capacitor C332 includes a first terminal coupled to the second terminal of resistor R332 and a second terminal coupled to ground node GND.

[0071] In this embodiment, the delay time provided by the delay circuit 3323 can be set by adjusting the resistance value of resistor R332 and / or the capacitance value of capacitor C332.

[0072] FIG7 illustrates a digital isolator 400 according to a fourth embodiment of the present invention. In the fourth embodiment, the digital isolator 400 uses a waveform modulator 432 instead of the waveform modulator 132 in the digital isolator 100. The waveform modulator 432 includes two hysteresis comparators 4321 and 4322 and an SR latch 4323.

[0073] As shown in Figure 7, the hysteresis comparator 4321 includes: a non-inverting input for receiving the isolated modulation signal SIGMB1; an inverting input for receiving the isolated modulation signal SIGMB2; and an output. The hysteresis comparator 4322 includes: a non-inverting input for receiving the isolated modulation signal SIGMB2; an inverting input for receiving the isolated modulation signal SIGMB1; and an output. The SR latch 4323 includes: a set input coupled to the output of the hysteresis comparator 4322; a reset input coupled to the output of the hysteresis comparator 4321; and an output for outputting the regulated modulation signal SIGRM.

[0074] Figure 8 illustrates a digital isolator 500 according to a fifth embodiment of the present invention. The difference between digital isolator 500 and digital isolator 200 lies in the demodulation circuit 530. In the demodulation circuit 530, the first counter 534 includes an N-bit counter register 5342 for recording the current count value, and the demodulation circuit 530 also includes a logic circuit 539A coupled to bits A[N] and A[0] of the counter register 5342 and the set terminal of the SR latch 138, for outputting a set signal SIGSET according to the current count value of the counter register 5342 and the conduction de-glitch threshold number, where N is a positive integer. In some embodiments, the logic circuit 539A allows the user to set the conduction de-glitch threshold number (i.e., the number of cycles of the regulated modulation signal SIGRM that needs to be counted before the first counter 534 generates the set signal SIGSET), and can be configured accordingly to output the set signal SIGSET when the current count value of the counter register 5342 reaches the predetermined conduction de-glitch threshold number. In other words, the conduction de-glitch threshold number is programmable. For example, if the user sets the conduction de-glitch threshold number to 8, the logic circuit 539A will generate a logic high level set signal SIGSET when bit A[3] becomes a logic high level (i.e., the value becomes "1").

[0075] Similarly, the second counter 536 may include an M-bit counter register 5362 for recording the current count value, and the demodulation circuit 530 further includes a logic circuit 539B coupled to bits B[M] and B[0] of the counter register 5362 and the reset terminal of the SR latch 138, for outputting a reset signal SIGRST based on the current count value of the counter register 5362 and the shutdown de-glitch threshold number, where M is a positive integer. In some embodiments, the logic circuit 539B allows the user to set the shutdown de-glitch threshold number (i.e., the number of cycles of the reference clock signal SIGRFCK that needs to be counted before the second counter 536 generates the reset signal SIGRST), and can be configured accordingly to output the reset signal SIGRST when the current count value of the counter register 5362 reaches the predetermined shutdown de-glitch threshold number. In other words, the shutdown de-glitch threshold number is programmable.

[0076] Furthermore, the demodulation circuit 530 may also include a logic circuit 539C, coupled to bit B[M] and bit B[0] of the counter register 5362 and the reset terminal of the first counter 534, for outputting a turn-on reset signal SIGONRST based on the current count value of the counter register 5362 and the maximum allowable off-time. In some embodiments, the logic circuit 539C allows the user to set the maximum allowable off-time. For example, the logic circuit 539C may allow the user to set the number of cycles of the reference clock signal SIGRFCK that needs to be counted before the second counter 536 generates the turn-on reset signal SIGONRST, and may be configured accordingly to output the turn-on reset signal SIGONRST when the current count value of the counter register 5362 reaches a predetermined value set by the user. In other words, the maximum allowable off-time is programmable. In addition, the demodulation circuit 530 employs an RC-based delay circuit 3323, including a resistor R332 and a capacitor C332. However, the invention is not limited thereto. In other embodiments, other types of delay circuits may be employed. For example, in some embodiments, a delay circuit based on a delay line (such as delay circuit 1323 in Figures 1 and 5) may be used instead of delay circuit 3323.

[0077] In summary, the digital isolator and demodulation circuit provided in this embodiment of the invention employ two counters to control the on and off times of the demodulated output signal. By utilizing the time measurement capability of the counters, the demodulation circuit can ignore noise caused by different types of common-mode transients, thereby reducing glitches in the demodulated output signal and enabling the digital isolator to achieve high CMTI. Furthermore, since the on-state glitches threshold, the off-state glitches threshold, and the maximum allowable off-state time can be programmed through the counters, this also provides great flexibility for circuit design.

[0078] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes described above can be implemented by different methods or replaced by other processes or combinations thereof.

[0079] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacturing methods, material compositions, means, methods, and steps described in the specification. Those skilled in the art will readily understand from this invention that existing or future-developed processes, machines, manufacturing methods, material compositions, means, methods, or steps can perform substantially the same function or achieve substantially the same result using the corresponding embodiments described herein. Therefore, the purpose of the appended claims is to include such processes, machines, manufacturing methods, material compositions, means, methods, or steps within its scope. [Simplified Explanation of the Diagram]

[0029] Figure 1 shows a digital isolator according to a first embodiment of the present invention. Figure 2 shows a signal timing diagram of the digital isolator shown in Figure 1. Figure 3 shows a timing diagram of the de-glitch capability of the digital isolator shown in Figure 1 in one example case. Figure 4 shows a timing diagram of the de-glitch capability of the digital isolator shown in Figure 1 in another example case. Figure 5 shows a digital isolator according to a second embodiment of the present invention. Figure 6 shows a digital isolator according to a third embodiment of the present invention. Figure 7 shows a digital isolator according to a fourth embodiment of the present invention. Figure 8 shows a digital isolator according to a fifth embodiment of the present invention.

Claims

1. A demodulation circuit, comprising: A waveform conditioner is configured to generate a conditioned modulation signal based on a pair of differential isolation modulation signals, wherein the differential isolation modulation signals are generated by modulating an input data signal with a carrier clock signal; A first counter includes: a clock input configured to receive the regulated modulation signal; a reset input; and an output configured to output a set signal; a second counter includes: a clock input configured to receive a reference clock signal; a reset input configured to receive the regulated modulation signal; a first output configured to output a reset signal; and a second output coupled to the reset input of the first counter for outputting a conduction reset signal; a first set-reset (SR) latch includes: a set input coupled to the output of the first counter; a reset input coupled to the first output of the second counter; and an output configured to output a demodulated output signal; wherein the first counter is configured to count the period of the regulated modulation signal to generate the set signal and trigger the first SR latch to pull the demodulated output signal high, and the second counter is configured to count the period of the reference clock signal to generate the reset signal and trigger the first SR latch to pull the demodulated output signal low.

2. The demodulation circuit as described in claim 1, wherein, The second counter is also configured to output the turn-on reset signal through the second output terminal when the duration for which the regulated modulation signal remains at a logic low level exceeds the duration of a first predetermined number of cycles of the reference clock signal.

3. The demodulation circuit as described in claim 2, wherein, The first counter is configured to generate the set signal when a second predetermined number of cycles of the regulated modulation signal has been counted and the conduction reset signal has not been received.

4. The demodulation circuit as described in claim 3, wherein, The second counter is configured to generate the reset signal when the regulated modulation signal is held at a logic low level and the count reaches a third predetermined number of cycles of the reference clock signal.

5. The demodulation circuit as claimed in claim 4, wherein the first predetermined number of cycles, the second predetermined number of cycles, and the third predetermined number of cycles are programmable.

6. The demodulation circuit as described in claim 1, wherein, The first counter further includes a counter register, and the output of the first counter is coupled to the most significant bit of the counter register to output the set signal.

7. The demodulation circuit as described in claim 1, wherein, The second counter further includes a counter register, and the first output terminal of the second counter is coupled to the most significant bit of the counter register to output the reset signal.

8. The demodulation circuit as described in claim 7, wherein, The demodulation circuit further includes an OR gate, comprising: a plurality of input terminals coupled to a plurality of most significant bits of the counter register; and an output terminal coupled to the reset terminal of the first counter, configured to output a conduction reset signal; wherein, the second output terminal of the second counter is coupled to the reset terminal of the first counter through the OR gate.

9. The demodulation circuit as described in claim 1, wherein, The frequency of the reference clock signal is equal to the frequency of the carrier clock signal.

10. The demodulation circuit as described in claim 1, wherein, When the differential isolation modulation signal periodically changes, the waveform adjuster adjusts the duty cycle of the adjusted modulation signal to approximately 50%.

11. The demodulation circuit as described in claim 1, wherein, The waveform conditioner includes: a hysteresis comparator, comprising: a non-inverting input configured to receive a first isolation modulation signal in the differential isolation modulation signal; an inverting input configured to receive a second isolation modulation signal in the differential isolation modulation signal; and an output; a D flip-flop, comprising: a data input configured to receive a power supply voltage; a clock input coupled to the output of the hysteresis comparator; a reset input; and an output configured to output the regulated modulation signal; and a delay circuit, comprising: an input coupled to the output of the D flip-flop; and an output coupled to the reset input of the D flip-flop.

12. The demodulation circuit as described in claim 11, wherein, The delay circuit includes multiple cascaded inverters.

13. The demodulation circuit as described in claim 11, wherein, The delay circuit includes: a resistor, comprising: a first terminal coupled to the input terminal of the delay circuit; a second terminal coupled to the output terminal of the delay circuit; and a capacitor, comprising: a first terminal coupled to the second terminal of the resistor; and a second terminal coupled to a ground node.

14. The demodulation circuit as described in claim 1, wherein, The waveform conditioner includes: a first hysteresis comparator, comprising: a non-inverting input configured to receive a first isolated modulation signal in the differential isolated modulation signal; an inverting input configured to receive a second isolated modulation signal in the differential isolated modulation signal; and an output; a second hysteresis comparator, comprising: a non-inverting input configured to receive the second isolated modulation signal; an inverting input configured to receive the first isolated modulation signal; and an output; and a second SR latch, comprising: a set input coupled to the output of the second hysteresis comparator; a reset input coupled to the output of the first hysteresis comparator; and an output configured to output the adjusted modulation signal.

15. A digital isolator, comprising: The demodulation circuit as described in claim 1; And an isolation circuit configured to receive a pair of differentially modulated input signals generated by modulating an input data signal with a carrier clock signal, and output the differentially isolated modulated signal pair.

16. The digital isolator as claimed in claim 15, wherein, The second counter is also configured to output a turn-on reset signal through the second output terminal when the duration for which the regulated modulation signal remains at a logic low level exceeds the duration of a first predetermined number of cycles of the reference clock signal.

17. The digital isolator as claimed in claim 15, wherein, The isolation circuit includes: a first capacitor, comprising: a first terminal configured to receive a first modulation input signal in the differential modulation input signal; and a second terminal; a second capacitor, comprising: a first terminal configured to receive a second modulation input signal in the differential modulation input signal; and a second terminal; a third capacitor, comprising: a first terminal coupled to a second terminal of the first capacitor; and a second terminal configured to output a first isolation modulation signal in the differential isolation modulation signal; a fourth capacitor, comprising: a first terminal coupled to a second terminal of the second capacitor; and a second terminal configured to output a second isolation modulation signal in the differential isolation modulation signal; a first resistor, comprising: a first terminal coupled to a second terminal of the third capacitor; and a second terminal; and a second resistor, comprising: a first terminal coupled to a second terminal of the fourth capacitor; and a second terminal coupled to a second terminal of the first resistor.

18. The digital isolator as claimed in claim 17, wherein, The isolation circuit further includes: a third resistor, comprising: a first terminal configured to receive the first modulation input signal; a second terminal coupled to a first terminal of the first capacitor; and a fourth resistor, comprising: a first terminal configured to receive the second modulation input signal; and a second terminal coupled to a first terminal of the second capacitor.

19. The digital isolator of claim 15 further includes a modulation circuit configured to generate the differential modulation input signal by modulating the input data signal with the carrier clock signal.

20. The digital isolator as claimed in claim 19, wherein, The modulation circuit includes: a gate, comprising: a first input configured to receive the carrier clock signal; a second input configured to receive the input data signal; and an output configured to output a first modulation input signal from the differential modulation input signal; and an inverter, comprising: an input coupled to the output of the gate; and an output configured to output a second modulation input signal from the differential modulation input signal.

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