Chip package

Abstract

A wafer package includes a semiconductor substrate, an insulating layer, a redistribution layer, a first protective layer, a conductive structure, and a second protective layer. The semiconductor substrate has through-holes and conductive pads within the through-holes. The insulating layer is located on the surface of the semiconductor substrate and on the inner sidewalls of the semiconductor substrate surrounding the through-holes. The redistribution layer is located on the insulating layer and extends to the conductive pads. The first protective layer is located on the redistribution layer and the insulating layer, and a portion of the first protective layer is located within the through-holes. The conductive structure is located on the redistribution layer. The second protective layer covers the first protective layer, the insulating layer, and the outer sidewalls of the semiconductor substrate, wherein the material of the second protective layer is different from the material of the first protective layer, and the second protective layer surrounds and directly contacts the conductive structure.

Description

[Technical Field]

[0001] This disclosure relates to a chip package. [Previous Technology]

[0002] A chip package includes a semiconductor substrate, an insulating layer, a redistribution layer, solder balls, and a protective layer (such as green paint). Generally, the redistribution layer is a metal composite layer, but the thickness of each metal layer within it is not specially designed, which makes it difficult to reduce metal stress when solder balls are placed on the redistribution layer.

[0003] Furthermore, although the under bump metallurgy (UBM) layer can be deposited on the redistribution layer before the solder balls are placed on the UBM layer, the materials of the redistribution layer and the UBM layer are not specially designed, making it difficult to strengthen the structure. The protective layer of a conventional wafer package is only located on the side of the semiconductor substrate with the solder balls, making it difficult to protect the outer wall of the semiconductor substrate. In addition, the insulating layer is usually etched across the entire surface to expose the solder pads in the through-holes of the semiconductor substrate. Therefore, after the insulating layer on the solder pads is removed, the thickness of the insulating layer at the turning point of the semiconductor substrate near the through-holes is significantly thinner, resulting in increased parasitic capacitance. [Summary of the Invention]

[0004] According to some embodiments of this disclosure, a wafer package includes a semiconductor substrate, an insulating layer, a redistribution layer, a first protective layer, a conductive structure, and a second protective layer. The semiconductor substrate has through-holes and conductive pads in the through-holes. The insulating layer is located on the surface of the semiconductor substrate and on the inner sidewalls of the semiconductor substrate surrounding the through-holes. The redistribution layer is located on the insulating layer and extends to the conductive pads. The first protective layer is located on the redistribution layer and the insulating layer, and a portion of the first protective layer is located in the through-holes. The conductive structure is located on the redistribution layer. The second protective layer covers the first protective layer, the insulating layer, and the outer sidewalls of the semiconductor substrate, wherein the material of the second protective layer is different from the material of the first protective layer, and the second protective layer surrounds and directly contacts the conductive structure.

[0005] In some embodiments, the material of the above-mentioned redistribution layer is only copper.

[0006] In some embodiments, the thickness of the redistribution layer is in the range of 3 μm to 4 μm.

[0007] In some embodiments, the wafer package further includes a metal composite layer. The metal composite layer is located between the redistribution layer and the conductive structure.

[0008] In some embodiments, the metal composite layer includes a copper layer, a nickel layer and a gold layer, with the nickel layer located between the copper layer and the gold layer, and the copper layer located between the redistribution layer and the nickel layer.

[0009] In some embodiments, a portion of the first protective layer is located between the metal composite layer and the redistribution layer.

[0010] In some embodiments, the material of the above-described conductive structure is nickel-free.

[0011] In some embodiments, the conductive structure described above directly contacts the redistribution layer.

[0012] In some embodiments, the thickness of the redistribution layer is in the range of 6.5 μm to 7.5 μm.

[0013] In some embodiments, the material of the conductive structure includes nickel, and the weight percentage of nickel in the conductive structure is in the range of 0.045% to 0.055%.

[0014] In some embodiments, the material of the first protective layer is polyimide, and the material of the second protective layer is epoxy resin.

[0015] In some embodiments, the thickness of the insulating layer at the junction of the surface of the semiconductor substrate and the inner sidewall is the same as the thickness of the insulating layer at the surface of the semiconductor substrate.

[0016] In some embodiments, the insulating layer has a foot structure on the conductive pad, and the foot structure gradually tapers away from the inner sidewall.

[0017] In the above-disclosed embodiment, since the wafer package has a first protective layer and a second protective layer, the second protective layer can be prevented from entering the via, which is beneficial for stress reduction. In addition, since the second protective layer can surround the conductive structure and cover the outer wall of the semiconductor substrate, the stability of the conductive structure can be improved and the outer wall of the semiconductor substrate can be protected.

[0018] According to some embodiments of this disclosure, a wafer package includes a semiconductor substrate, an insulating layer, a redistribution layer, a conductive structure, and a protective layer. The semiconductor substrate has through-holes and conductive pads in the through-holes. The insulating layer is located on the surface of the semiconductor substrate and on the inner sidewalls of the semiconductor substrate surrounding the through-holes. The redistribution layer is located on the insulating layer and extends to the conductive pads. The redistribution layer includes a copper layer, a nickel layer, and a gold layer. A nickel layer is located between the copper layer and the gold layer, and a copper layer is located between the insulating layer and the nickel layer. The thickness of the copper layer is greater than the sum of the thicknesses of the nickel layer and the gold layer. The conductive structure is located on the redistribution layer. The protective layer covers the redistribution layer, the insulating layer, and the outer sidewalls of the semiconductor substrate, wherein the protective layer surrounds and directly contacts the conductive structure.

[0019] In some embodiments, the thickness of the copper layer is in the range of 6.5 μm to 7.5 μm, the thickness of the nickel layer is in the range of 0.05 μm to 0.5 μm, and the thickness of the gold layer is in the range of 0.025 μm to 0.035 μm.

[0020] In some embodiments, the material of the above-described conductive structure is nickel-free.

[0021] In some embodiments, the conductive structure described above directly contacts the redistribution layer.

[0022] In some embodiments, a portion of the above-mentioned protective layer is located in the perforation.

[0023] In some embodiments, the thickness of the insulating layer at the junction of the surface of the semiconductor substrate and the inner sidewall is the same as the thickness of the insulating layer at the surface of the semiconductor substrate.

[0024] In some embodiments, the insulating layer has a foot structure on the conductive pad, and the foot structure gradually tapers away from the inner sidewall.

[0025] In the above-disclosed embodiment, since the redistribution layer includes a copper layer, a nickel layer, and a gold layer, with the nickel layer located between the copper layer and the gold layer, and the copper layer located between the insulating layer and the nickel layer, and the thickness of the copper layer being greater than the sum of the thicknesses of the nickel layer and the gold layer, metal stress can be effectively reduced. Furthermore, since the protective layer can surround the conductive structure and cover the outer wall of the semiconductor substrate, the stability of the conductive structure can be improved, and the outer wall of the semiconductor substrate can be protected.

Implementation Method

[0027] The following disclosure of embodiments provides many different implementations or examples for carrying out different features of the provided object. Specific examples of elements and arrangements are described below to simplify the present invention. Of course, these examples are merely examples and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity purposes and does not in itself specify the relationship between the various implementations and / or configurations discussed.

[0028] Spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein for descriptive purposes to describe the relationship between one element or feature as shown in the accompanying drawings and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein may be interpreted accordingly.

[0029] Figure 1 illustrates a cross-sectional view of a wafer package 100 according to an embodiment of the present disclosure. As shown, the wafer package 100 includes a semiconductor substrate 110, an insulating layer 120, a redistribution layer 130, a first protective layer 140, a conductive structure 150, and a second protective layer 160. The semiconductor substrate 110 has a through-hole O and a conductive pad 112, the conductive pad 112 being located in the through-hole O. That is, the conductive pad 112 is positioned corresponding to the through-hole O and overlaps in the vertical direction. The semiconductor substrate 110 has an inner sidewall 113 surrounding the through-hole O. The insulating layer 120 is located on the surface 111 and the inner sidewall 113 of the semiconductor substrate 110. In some embodiments, the material of the semiconductor substrate 110 may include silicon, such as a silicon substrate. The material of the insulating layer 120 may be silicon dioxide. The redistribution layer 130 is located on the insulating layer 120 and extends to the conductive pad 112. A first protective layer 140 is located on the redistribution layer 130 and the insulating layer 120, and a portion of the first protective layer 140 is located in the via O. A conductive structure 150 is located on the redistribution layer 130. A second protective layer 160 covers the first protective layer 140, the insulating layer 120, and the outer sidewall 115 of the semiconductor substrate 110. The material of the second protective layer 160 is different from the material of the first protective layer 140, and the second protective layer 160 surrounds and directly contacts the conductive structure 150. For example, the material of the first protective layer 140 may be polyimide (PI), and the material of the second protective layer 160 may be epoxy resin (e.g., solder resist).

[0030] Specifically, since the wafer package 100 has a first protective layer 140 and a second protective layer 160, the second protective layer 160 can be prevented from entering the through hole O, which is beneficial to reducing stress. In addition, since the second protective layer 160 can surround the conductive structure 150 and cover the outer wall 115 of the semiconductor substrate 110, the stability of the conductive structure 150 can be improved and the outer wall 115 of the semiconductor substrate 110 can be protected.

[0031] In this embodiment, the redistribution layer 130 is made of only copper, that is, the redistribution layer 130 is a pure copper layer. The thickness H1 of the redistribution layer 130 is in the range of 3μm to 4μm, for example, 3.5μm. The conductive structure 150 is made of tin but without nickel. With the above configuration, metal stress can be effectively reduced.

[0032] Figure 2 is a partially enlarged view of the metal composite layer 170 in Figure 1. Referring to both Figure 1 and Figure 2, the wafer package 100 may further include the metal composite layer 170. The metal composite layer 170 is located between the redistribution layer 130 and the conductive structure 150. A portion of the first protective layer 140 is located between the metal composite layer 170 and the redistribution layer 130, and a second protective layer 160 surrounds and directly contacts the metal composite layer 170. The metal composite layer 170 includes a copper layer 172, a nickel layer 174, and a gold layer 176. The nickel layer 174 is located between the copper layer 172 and the gold layer 176, and the copper layer 172 is located between the redistribution layer 130 and the nickel layer 174. With the above configuration, the stability of the conductive structure 150 can be enhanced.

[0033] Figure 3 is a partial enlarged view of the semiconductor substrate 110, insulating layer 120, and redistribution layer 130 in region A of Figure 1. Referring to both Figure 1 and Figure 3, the insulating layer 120 is formed by deposition and photoresist coating followed by etching. Compared to the insulating layer formed by directly oxidizing the silicon substrate, the thickness H2 of the insulating layer 120 at the junction of the surface 111 and the inner sidewall 113 of the semiconductor substrate 110 is the same as the thickness H3 of the insulating layer 120 at the surface 111 of the semiconductor substrate 110, and can also be the same as the thickness at the inner sidewall 113 of the semiconductor substrate 110. That is, the insulating layer 120 has a uniform thickness and does not become significantly thinner at the junction of the surface 111 and the inner sidewall 113, thus without obvious chamfered bevels. With the above configuration, parasitic capacitance can be effectively reduced.

[0034] Figure 4 is a partial enlarged view of the semiconductor substrate 110, insulating layer 120, redistribution layer 130, and conductive pad 112 in region B of Figure 1. Referring to both Figure 1 and Figure 4, the insulating layer 120 has a foot structure 122 on the conductive pad 112, and the foot structure 122 gradually tapers away from the inner sidewall 113. The position of the tip of the foot structure 122 can be defined by the vertical position covered by the photoresist etched into the insulating layer 120.

[0035] It should be understood that the component connections, materials, and functions already described will not be repeated hereafter. Other types of chip packages will be described in the following description. In addition, the insulating layer 120 design of Figures 3 and 4 can be applied to the chip package 100a of Figure 5 and the chip package 100b of Figure 6.

[0036] Figure 5 illustrates a cross-sectional view of a wafer package 100a according to another embodiment of this disclosure. The wafer package 100a includes a semiconductor substrate 110, an insulating layer 120, a redistribution layer 130a, a first protective layer 140, a conductive structure 150a, and a second protective layer 160. This embodiment differs from the embodiment in Figure 1 in that the wafer package 100a lacks the metal composite layer 170 of Figure 1, and the material of the conductive structure 150a includes nickel and tin. The conductive structure 150a of the wafer package 100a directly contacts the redistribution layer 130a. Furthermore, the nickel content of the conductive structure 150a is in the range of 0.045% to 0.055% by weight, for example, 0.05%. The thickness H4 of the redistribution layer 130a is greater than the thickness H1 of the redistribution layer 130 in Figure 1. The thickness H4 of the redistribution layer 130a is in the range of 6.5 μm to 7.5 μm, for example, 7 μm. In this embodiment, the second protective layer 160 of the wafer package 100a has a portion located between the first protective layer 140 and the conductive structure 150a.

[0037] Figure 6 illustrates a cross-sectional view of a wafer package 100b according to yet another embodiment of this disclosure. Figure 7 is a partially enlarged view of the redistribution layer 130b in Figure 6. Referring to both Figures 6 and 7, the wafer package 100b includes a semiconductor substrate 110, an insulating layer 120, a redistribution layer 130b, a conductive structure 150, and a protective layer 160a. This embodiment differs from the embodiment in Figure 5 in that the redistribution layer 130b of the wafer package 100b includes a copper layer 132, a nickel layer 134, and a gold layer 136; the wafer package 100b has only a single protective layer 160a; and the material of the conductive structure 150 includes tin but no nickel. The nickel layer 134 is located between the copper layer 132 and the gold layer 136, and the copper layer 132 is located between the insulating layer 120 and the nickel layer 134. The thickness H5 of the copper layer 132 is greater than the thickness H6 of the nickel layer 134 and the thickness H7 of the gold layer 136, and also greater than the sum of the thicknesses of the nickel layer 134 and the gold layer 136. In this embodiment, the thickness H5 of the copper layer 132 is in the range of 6.5 μm to 7.5 μm (e.g., 7 μm), the thickness H6 of the nickel layer 134 is in the range of 0.05 μm to 0.5 μm (e.g., 0.25 μm), and the thickness H7 of the gold layer 136 is in the range of 0.025 μm to 0.035 μm (e.g., 0.03 μm). The protective layer 160a covers the redistribution layer 130b, the insulating layer 120, and the outer wall 115 of the semiconductor substrate 110, and the protective layer 160a surrounds and directly contacts the conductive structure 150. Furthermore, a portion of the protective layer 160a is located in a through-hole O in the semiconductor substrate 110.

[0038] Since the redistribution layer 130b includes a copper layer 132, a nickel layer 134, and a gold layer 136, with the nickel layer 134 located between the copper layer 132 and the gold layer 136, and the copper layer 132 located between the insulating layer 120 and the nickel layer 134, and the thickness H5 of the copper layer 132 is greater than the sum of the thicknesses of the nickel layer 134 and the gold layer 136, metal stress can be effectively reduced. Furthermore, since the protective layer 160a can surround the conductive structure 150 and cover the outer wall 115 of the semiconductor substrate 110, the stability of the conductive structure 150 can be improved, and the outer wall 115 of the semiconductor substrate 110 can be protected.

[0039] In some embodiments, the nickel layer 134 may be formed by electroplating, while the gold layer 136 may be formed by chemical plating, but this is not intended to limit the present disclosure.

[0040] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0026] The nature of this disclosure can be best understood by reading the accompanying drawings and the embodiments described below. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of explanation. Figure 1 shows a cross-sectional view of a wafer package according to one embodiment of this disclosure. Figure 2 is a partially enlarged view of the metal composite layer in Figure 1. Figure 3 is a partially enlarged view of the semiconductor substrate, insulating layer, and redistribution layer in region A of Figure 1. Figure 4 is a partially enlarged view of the semiconductor substrate, insulating layer, redistribution layer, and conductive pad in region B of Figure 1. Figure 5 shows a cross-sectional view of a wafer package according to another embodiment of this disclosure. Figure 6 shows a cross-sectional view of a wafer package according to yet another embodiment of this disclosure. Figure 7 is a partially enlarged view of the redistribution layer in Figure 6. [Biomaterial Storage]

[0042] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A chip package, comprising: A semiconductor substrate having a through hole and a conductive pad in the through hole; An insulating layer is located on a surface of the semiconductor substrate and on an inner sidewall of the semiconductor substrate surrounding the through-hole; a redistribution layer is located on the insulating layer and extends to the conductive pad; a first protective layer is located on the redistribution layer and the insulating layer, and a portion of the first protective layer is located in the through-hole; a conductive structure is located on the redistribution layer; a metal composite layer is located between the redistribution layer and the conductive structure, wherein another portion of the first protective layer is located between the metal composite layer and the redistribution layer; and a second protective layer covers the first protective layer, the insulating layer and the outer sidewall of the semiconductor substrate, wherein the material of the second protective layer is different from the material of the first protective layer, and the second protective layer surrounds and directly contacts the conductive structure.

2. The wafer package as described in claim 1, wherein the material of the redistribution layer is only copper.

3. The wafer package as described in claim 1, wherein the thickness of the redistribution layer is in the range of 3 μm to 4 μm.

4. The wafer package as claimed in claim 1, wherein the metal composite layer comprises a copper layer, a nickel layer and a gold layer, the nickel layer being located between the copper layer and the gold layer, and the copper layer being located between the redistribution layer and the nickel layer.

5. The wafer package as described in claim 1, wherein the conductive structure is made of nickel-free material.

6. The wafer package as described in claim 1, wherein the conductive structure directly contacts the redistribution layer.

7. The wafer package as claimed in claim 1, wherein the thickness of the redistribution layer is in the range of 6.5 μm to 7.5 μm.

8. The wafer package as claimed in claim 1, wherein the material of the conductive structure includes nickel, and the nickel constitutes a weight percentage of the conductive structure in the range of 0.045% to 0.055%.

9. The wafer package as claimed in claim 1, wherein the first protective layer is made of polyimide and the second protective layer is made of epoxy resin.

10. The wafer package as claimed in claim 1, wherein the thickness of the insulating layer at the junction of the surface of the semiconductor substrate and the inner sidewall is the same as the thickness of the insulating layer on the surface of the semiconductor substrate.

11. The wafer package as claimed in claim 1, wherein the insulating layer has a foot structure on the conductive pad, and the foot structure tapers gradually away from the inner sidewall.

12. A wafer package, comprising: A semiconductor substrate having a through hole and a conductive pad in the through hole; An insulating layer is located on a surface of the semiconductor substrate and on an inner sidewall of the semiconductor substrate surrounding the through-hole, wherein the insulating layer has a foot structure on the conductive pad, and the foot structure gradually tapers away from the inner sidewall; a redistribution layer is located on the insulating layer and extends to the conductive pad, wherein the redistribution layer includes a copper layer, a nickel layer and a gold layer, the nickel layer is located between the copper layer and the gold layer, the copper layer is located between the insulating layer and the nickel layer, and the thickness of the copper layer is greater than the sum of the thicknesses of the nickel layer and the gold layer; a conductive structure is located on the redistribution layer; and a protective layer covers the redistribution layer, the insulating layer and the outer sidewall of the semiconductor substrate, wherein the protective layer surrounds and directly contacts the conductive structure.

13. The wafer package as claimed in claim 12, wherein the thickness of the copper layer is in the range of 6.5 μm to 7.5 μm, the thickness of the nickel layer is in the range of 0.05 μm to 0.5 μm, and the thickness of the gold layer is in the range of 0.025 μm to 0.035 μm.

14. The wafer package as described in claim 12, wherein the conductive structure is made of nickel-free material.

15. The wafer package as described in claim 12, wherein the conductive structure directly contacts the redistribution layer.

16. The wafer package as described in claim 12, wherein a portion of the protective layer is located in the through-hole.

17. The wafer package as claimed in claim 12, wherein the thickness of the insulating layer at the junction of the surface of the semiconductor substrate and the inner sidewall is the same as the thickness of the insulating layer on the surface of the semiconductor substrate.

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