Semiconductor device and methods of forming the same

Abstract

This disclosed embodiment provides a semiconductor device. The semiconductor device includes a gate electrode disposed above a channel region and epitaxial source / drain features inserted into the channel region along a first direction. The gate electrode has a longitudinal axis extending along a second direction and includes a lower portion and an upper portion located above the lower portion. The gate electrode includes a sidewall extending along the first direction. The sidewall includes a main surface, a first protrusion protruding from the main surface at the lower portion of the gate electrode, and a second protrusion protruding from the main surface at the upper portion of the gate electrode. The main surface is a flat surface, and the density of the first protrusion in the lower portion of the gate electrode is less than the density of the second protrusion in the upper portion of the gate electrode.

Claims

1. A semiconductor device, comprising: One substrate; A channel area is disposed above the substrate; A gate dielectric layer is disposed above the channel region; A gate electrode is disposed above the channel region and has a longitudinal axis extending along a first direction, wherein the gate electrode includes a lower portion and an upper portion located above the lower portion, wherein the gate electrode includes a first sidewall extending along the first direction, the first sidewall including a first main surface, a first protrusion protruding from the first main surface in the lower portion of the gate electrode, and a second protrusion protruding from the first main surface in the upper portion of the gate electrode, wherein the first main surface is a flat surface, wherein the density of the first protrusion in the lower portion of the gate electrode is less than the density of the second protrusion in the upper portion of the gate electrode, wherein the gate electrode comprises a titanium-based material; a gate spacer is disposed above the first protrusion, the second protrusion, and the first main surface of the first sidewall of the gate electrode, wherein the gate spacer includes a bottom surface lower than a top surface of the channel region; and a plurality of epitaxial source / drain features inserted into the channel region in a second direction perpendicular to the first direction.

2. The apparatus as claimed in claim 1, wherein, The lower part of the gate electrode has a first height in a vertical direction, and the upper part of the gate electrode has a second height in the vertical direction, wherein the first height is greater than the second height.

3. The apparatus as claimed in claim 2, wherein, The channel region comprises a plurality of vertically stacked nanostructures, wherein the lower portion and the upper portion of the gate electrode are connected at a horizontal level above the top surface of the uppermost nanostructure.

4. The apparatus as claimed in claim 1, wherein, The first protrusion has a first average size in a vertical direction, and the second protrusion has a second average size in the same vertical direction, wherein the second average size is greater than the first average size.

5. A semiconductor device, comprising: One substrate; A channel area is disposed above the substrate; A gate electrode having a longitudinal axis along a first direction and located above a channel region, wherein the gate electrode includes a first sidewall extending along the first direction and a second sidewall extending along a second direction perpendicular to the first direction, wherein the first sidewall includes a first main surface and a plurality of first protrusions protruding above the first main surface, and the second sidewall includes a second main surface and a plurality of second protrusions protruding above the second main surface, wherein both the first main surface and the second main surface are planar; a plurality of epitaxial source / drain features inserted into the channel region along the second direction; an insulating layer disposed above the epitaxial source / drain features; and a contact extending through the insulating layer to be electrically coupled to the epitaxial source / drain features, wherein a conductivity of the contact is greater than a conductivity of the epitaxial source / drain features.

6. The device of claim 5 further includes a third sidewall opposite to the second sidewall, wherein the third sidewall includes a third main surface and a plurality of third protrusions protruding from the third main surface.

7. The apparatus as claimed in claim 6, wherein, The first protrusions and the third protrusions are asymmetrical to each other.

8. A method of forming a semiconductor device, comprising: A semiconductor strip is formed above a substrate, wherein the semiconductor strip includes a plurality of alternating stacked first semiconductor layers and a plurality of second semiconductor layers; A dummy gate layer is formed over the substrate, spanning the semiconductor strip. Forming the dummy gate layer includes: performing a first cycle multiple times and a second cycle at least once, wherein the first cycle includes a first deposition step and a first etching step, and the second cycle includes a second deposition step and no etching step, wherein the first deposition step and the second deposition step operate at a first temperature; and performing a third cycle multiple times and a fourth cycle at least once, wherein the third cycle includes a third deposition step and a second etching step, and the second cycle includes a fourth deposition step and no etching step, wherein the third deposition step and the fourth deposition step operate at a second temperature higher than the first temperature; forming a plurality of gate spacers on opposite sidewalls of the dummy gate layer in a first direction; and etching the first semiconductor layers and the second semiconductor layers along the gate spacers to form a plurality of first nanostructures and a plurality of second nanostructures, respectively. A plurality of epitaxial source / drain features are formed between the first nanostructures, each of the epitaxial source / drain features comprising two layers containing the same semiconductor material but different concentrations; the second nanostructures and the dummy gate layer are replaced with a gate electrode; and an inter-dielectric layer is formed above the gate electrode and the epitaxial source / drain features, wherein the height of the inter-dielectric layer is less than the total height of the gate electrode.

9. As in request item 8, wherein, The first deposition step, the second deposition step, the third deposition step, and the fourth deposition step are all low-pressure chemical vapor deposition.

10. As in request item 8, wherein, The first deposition step, the second deposition step, the third deposition step, and the fourth deposition step are operated at a pressure of about 0.1 torr to about 20 torr, wherein the first temperature is about 350 degrees Celsius to about 500 degrees Celsius, and the second temperature is about 550 degrees Celsius to about 800 degrees Celsius.

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