Memory device and method for forming the same

Abstract

A memory chip includes a substrate and a capacitor structure located above the substrate. The capacitor structure includes a bottom electrode, a dielectric structure above the bottom electrode, and a top electrode above the dielectric structure. The dielectric structure includes a bottom barrier layer made of alumina, a top barrier layer made of alumina and located above the bottom barrier layer, and a stack consisting of a plurality of dielectric layers and at least one insertion layer, the dielectric layers being made of zirconium-doped hafnium oxide, and at least one insertion layer being made of alumina, the stack being located between the bottom barrier layer and the top barrier layer, wherein the at least one insertion layer is located between two adjacent dielectric layers.

Claims

1. A memory chip comprising: a substrate; and a capacitor structure located above the substrate, comprising: a bottom electrode made of polysilicon; a silicon oxide layer located above the bottom electrode; a dielectric structure located above the silicon oxide layer, comprising: a bottom barrier layer made of aluminum oxide; a top barrier layer made of aluminum oxide located above the bottom barrier layer; and a stack comprising a plurality of dielectric layers and at least one insertion layer, the dielectric layers being made of zirconium-doped hafnium oxide, and the at least one insertion layer being made of aluminum oxide, the stack being located between the bottom barrier layer and the top barrier layer, wherein the at least one insertion layer is located between two adjacent dielectric layers, and wherein the thickness of the silicon oxide layer is less than the thickness of the bottom barrier layer, the top barrier layer, the dielectric layers, and the at least one insertion layer; and a top electrode located above the dielectric structure.

2. The memory as claimed in claim 1, wherein the zirconium concentration of the dielectric layers is from about 50% to about 100%.

3. The memory as claimed in claim 1, wherein the top barrier layer contacts the top electrode.

4. The memory as claimed in claim 1, wherein the top electrode is made of titanium nitride.

5. The memory as claimed in claim 1, wherein the zirconium concentration of the top barrier layer and the bottom barrier layer is less than the zirconium concentration of the dielectric layers.

6. The memory as claimed in claim 1, wherein the top barrier layer, the bottom barrier layer and the at least one insertion layer are free of zirconium.

7. The memory as claimed in claim 1, wherein the bottom barrier layer and the top barrier layer are thicker than the at least one insertion layer.

8. The memory as claimed in claim 1, wherein the dielectric structure includes a plurality of the insertion layers, wherein each of the plurality of insertion layers is located between two adjacent dielectric layers.

9. The memory as claimed in claim 1, wherein the dielectric layers have a tetragonal and orthorhombic crystal structure.

10. The memory as claimed in claim 1, further comprising: a word line structure located above the substrate; and a bit line structure located above the substrate and electrically connected to a doped region of the substrate located on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate located on a second side of the word line structure.

11. A method for forming a memory, comprising: forming a capacitor structure above a substrate, comprising: depositing a bottom electrode made of polysilicon; forming a dielectric structure above the bottom electrode, comprising: forming a bottom barrier layer made of aluminum oxide, wherein while forming the bottom barrier layer, a silicon oxide layer is formed between the bottom barrier layer and the bottom electrode; A stack is formed comprising a plurality of dielectric layers and at least one insertion layer, the dielectric layers being made of zirconium-doped hafnium oxide and the at least one insertion layer being made of aluminum oxide, the stack being located above the bottom barrier layer, wherein the at least one insertion layer is located between two adjacent dielectric layers; and a top barrier layer is formed, made of aluminum oxide, and located above the stack of the dielectric layers and the at least one insertion layer, wherein the thickness of the aluminum oxide layer is less than the thickness of the bottom barrier layer, the top barrier layer, the dielectric layers and the at least one insertion layer; and a top electrode is formed above the dielectric structure.

12. The method of claim 11, wherein the zirconium concentration of the dielectric layers is from about 50% to about 100%.

13. The method of claim 11, wherein the top barrier layer contacts the top electrode.

14. The method of claim 11, wherein the top electrode is made of titanium nitride.

15. The method of claim 11, wherein forming the silicon oxide layer comprises oxidizing a portion of the bottom electrode into the oxide layer.

16. The method of claim 11, wherein the zirconium concentration of the top barrier layer and the bottom barrier layer is less than the zirconium concentration of the dielectric layers.

17. The method of claim 11, wherein the top barrier layer, the bottom barrier layer and the at least one insert layer are free of zirconium.

18. The method of claim 11, wherein forming the bottom barrier layer comprises performing an atomic layer deposition (ALD) process by providing an oxygen source and an aluminum source, and wherein the oxygen source oxidizes a portion of the bottom electrode into the silicon oxide layer.

19. The method of claim 11, wherein the bottom barrier layer and the top barrier layer are thicker than the at least one insertion layer.

20. The method of claim 11, further comprising: forming a word line structure above the substrate; and forming a word line structure above the substrate and electrically connected to a doped region of the substrate on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.

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