Resistive switching memory, resistive switching element, resistive switching layer and its preparation method

Abstract

This invention discloses a resistive switching memory, a resistive switching element, a resistive switching layer, and a method for fabricating the same. The method includes etching a bottom electrode using a first photomask to form a first groove; then, depositing a dielectric film on the etched bottom electrode to cover it, and planarizing the dielectric film using a second photomask; next, etching the planarized dielectric film using a third photomask to form a second groove; finally, depositing a transition metal oxide film on the etched dielectric film to cover it, and planarizing the transition metal oxide film to obtain the resistive switching layer. Thus, by splitting the dielectric film deposition process into two steps, the height of the resistive switching element structure is reduced, thereby reducing the size and distance limitations of the resistive switching element and avoiding the risk of failure.

Description

[Technical Field]

[0001] This invention relates to the field of storage technology, and in particular to a method for preparing a resistive switching layer, a resistive switching layer, a resistive switching element, and a resistive switching memory. [Previous Technology]

[0002] In related technologies, resistive random access memory (ReRAM) has a 1T1R structure, where T refers to transistor and R refers to ReRAM. In the process of preparing the resistive switching layer, a metal oxide film is usually deposited on the bottom electrode first, and then the deposited metal oxide film is etched to form the morphology shown in Figure 1. This method limits the height of R, that is, the size and gap of R are limited, thereby increasing the risk of failure. Furthermore, after the transition metal oxide film is etched, sidewall damage is unavoidable. [Summary of the Invention]

[0003] The present invention aims to at least partially solve one of the technical problems in the above-mentioned technology. To this end, one object of the present invention is to provide a method for preparing a resistive switching layer that can reduce the height of R, thereby avoiding the risk of failure, and at the same time reduce the sidewall loss caused by etching by etching before deposition.

[0004] A second objective of the present invention is to provide a resistive switching layer.

[0005] A third objective of the present invention is to provide a resistive switching element.

[0006] The fourth objective of this invention is to propose a resistive switching memory.

[0007] To achieve the above objective, a method for preparing a resistive switching layer according to a first aspect embodiment of the present invention includes the following steps: etching a bottom electrode using a first photomask to form a first groove; depositing a dielectric film on the etched bottom electrode to cover the bottom electrode, and planarizing the dielectric film using a second photomask; etching the planarized dielectric film using a third photomask to form a second groove; depositing a transition metal oxide film on the etched dielectric film to cover the dielectric film, and planarizing the transition metal oxide film to obtain a resistive switching layer.

[0008] According to the method for preparing the resistive switching layer of the present invention, firstly, a first photomask is used to etch the bottom electrode to form a first groove; then, a dielectric film is deposited on the etched bottom electrode to cover the bottom electrode, and a second photomask is used to planarize the dielectric film; then, a third photomask is used to etch the planarized dielectric film to form a second groove; finally, a transition metal oxide film is deposited on the etched dielectric film to cover the dielectric film, and the transition metal oxide film is planarized to obtain the resistive switching layer; thereby avoiding the risk of failure, and reducing the sidewall loss caused by etching by etching before deposition.

[0009] In addition, the method for preparing the resistive switching layer according to the above embodiments of the present invention may also have the following additional technical features:

[0010] Optionally, the transition metal oxide film is planarized by etching, wherein the uniformity of the pit contour is improved by adjusting and monitoring the concentration, flow rate and pressure of the etching gas during etching.

[0011] Optionally, the transition metal oxide film is planarized by chemical mechanical polishing, wherein the chemical reactivity and surface tension during the polishing process are changed by adjusting the pH value and adding different chemical reagents to improve the uniformity of the pit contour.

[0012] Optionally, the deposition method is plasma-enhanced chemical vapor deposition.

[0013] Optionally, the dielectric film serves as a stop layer for the chemical mechanical polishing or etching.

[0014] Optionally, the dielectric thin film includes any one of silicon oxide, silicon nitride, or silicon oxynitride.

[0015] To achieve the above objective, a second aspect of the present invention provides a resistive switching layer, which is prepared by the above-described preparation method.

[0016] According to the resistive switching layer of the present invention, the height of R can be reduced by the above preparation method, thereby reducing the volume and distance of R. At the same time, the sidewall loss caused by etching can be reduced by etching before deposition.

[0017] To achieve the above objectives, the present invention provides a resistive switching element, including a bottom electrode, a top electrode, and a resistive switching layer and an oxygen storage layer disposed between the bottom electrode and the top electrode, wherein the resistive switching layer is prepared by the above-described preparation method.

[0018] To achieve the above objective, a fourth aspect of the present invention provides a resistive switching memory, comprising a plurality of resistive switching elements as described above, wherein the plurality of resistive switching elements are arranged in an array. [Simplified Explanation of the Diagram]

[0019] Figure 1 is a schematic diagram of the structure of an existing resistive switching element;

[0020] Figure 2 is a schematic flowchart of a method for preparing a resistive switching layer according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of the resistive switching layer fabrication process according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of the resistive switching layer preparation process according to another embodiment of the present invention.

Implementation Method

[0023] Embodiments of the present invention will now be described in detail. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0024] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention can be thoroughly understood and its scope can be fully conveyed to those skilled in the art.

[0025] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0026] The preparation method of the resistive switching layer, the resistive switching layer, the resistive switching element, and the resistive switching memory of the present invention will be described below with reference to the accompanying drawings.

[0027] Figure 2 is a schematic flowchart of a method for preparing a resistive switching layer according to an embodiment of the present invention; as shown in Figure 2, the method for preparing the resistive switching layer includes the following steps:

[0028] S101, the bottom electrode is etched using a first photomask to form a first groove.

[0029] That is, the first photomask is used to etch the existing prepared bottom electrode to form a first groove on the bottom electrode, wherein the existing prepared bottom electrode is shown in Figure 3 or Figure 4(a).

[0030] As an embodiment, as shown in FIG3 or FIG4(b), an R photomask is used to etch on the bottom electrode to form a first groove.

[0031] S102, deposit a dielectric film on the etched bottom electrode to cover the bottom electrode, and use a second photomask to flatten the dielectric film.

[0032] As an embodiment, as shown in Figure 3 or Figure 4(c), a dielectric film (Si3N4) is deposited on the etched bottom electrode using plasma-enhanced chemical vapor deposition (PECVD) so that the dielectric film fills the first groove and covers the bottom electrode. Then, the dielectric film is planarized using an etch back photomask. As shown in Figure 3 or Figure 4(d) after planarization, at this time, the aspect ratio of R is 6:10, and the aspect ratio of the PECVD dielectric film is greater than 1, so there is no risk of void formation.

[0033] It should be noted that by filling with a dielectric thin film first and then etching, voids are less likely to exist. After filling with a transition metal oxide thin film, there is no risk of failure due to short circuits caused by voids.

[0034] S103, the flattened dielectric film is etched using a third photomask to form a second groove.

[0035] As an example, as shown in Figure 3 or Figure 4(e), a photomask is used to etch a width of 21nm and a height of 5nm (the aperture size of the 28nm process is about 20~30nm), with 10~20nm overlap on the left and right sides, so the R size can be 41nm*41nm~61nm*61nm.

[0036] S104, deposit a transition metal oxide film on the etched dielectric film to cover the dielectric film, and planarize the transition metal oxide film to obtain a resistive switching layer.

[0037] It should be noted that the schematic diagram after depositing the transition metal oxide (TMO) film is shown in Figure 3 or Figure 4(f). The transition metal oxide film can be HfO, and this application does not make any specific limitation on it.

[0038] As an example, a transition metal oxide film is planarized by etching, wherein the uniformity of the pit contour is improved by adjusting and monitoring the concentration, flow rate and pressure of the etching gas during etching.

[0039] It should be noted that the planarization process is shown in (g1) and (h1) of Figure 3. After the deposition of the transition metal oxide film, there are pits. These pits can be effectively concentrated in the conductive filatments (CF) formed between the electrodes. In order to ensure the uniformity of the pit contour, a cleaning and processing process is performed before etching to ensure that there are no impurities. At the same time, the uniformity of the pit contour is improved by adjusting and monitoring the concentration, flow rate and pressure of the etching gas during the etching condition control using the photoresist fill selectivity. After etching, the material is cleaned to obtain the resistive switching layer.

[0040] As another embodiment, a chemical mechanical polishing method is used to planarize the transition metal oxide film. During polishing, the chemical reactivity and surface tension during the polishing process are changed by adjusting the pH value and adding different chemical reagents, so as to improve the uniformity of the pit contour.

[0041] It should be noted that the planarization process is shown in (g2) and (h2) of Figure 4. After the deposition of the transition metal oxide film, there are pits. These pits can effectively concentrate the conductive filaments formed between the electrodes. In order to ensure the uniformity of the pit contour, chemical mechanical polishing (CMP) is used to planarize the transition metal oxide film. During polishing, the chemical reactivity and surface tension during the polishing process are changed by adjusting the pH value and adding different chemical reagents to improve the uniformity of the pit contour. During intermittent processing, an air gap is introduced in the contact between the polishing pad and the silicon wafer surface to reduce the wear of the CMP polishing pad. The CMP process is monitored in real time. After polishing, the interface is cleaned with an acidic cleaning agent to obtain the resistive switching layer. The dielectric film serves as the stop layer of CMP.

[0042] As shown in (i) and (j) of Figure 3 or Figure 4, an oxygen storage layer can be deposited on the resistive switching layer using existing methods, and a top electrode can be deposited on the oxygen storage layer to obtain the resistive switching unit. In this case, the dielectric film 1 can be used as an air gap, while the dielectric film 2 is a dielectric thin film including but not limited to insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, which can be used as a stop etching layer.

[0043] Thus, this application can reduce the critical dimensions and gaps of R by reducing the height of R without increasing the number of process steps, thereby avoiding the formation of voids, achieving the effect of increasing density, and reducing the area of ​​CF; specifically, the existing R size is 90*90, space 85, and this application can achieve R size 41*41, space 50, (the aperture size of the 28-nanometer process is about 20~30nm, with 10~20nm overlap on the left and right). In addition, by etching first and then filling, the sidewall loss caused by etching can be reduced, thereby reducing the risk of ILR (Initial Low Resistance), where ILR means that the component has many defects when the initial resistance value is low.

[0044] In summary, according to the method for preparing the resistive switching layer according to the embodiments of the present invention, firstly, a first photomask is used to etch the bottom electrode to form a first groove; then, a dielectric film is deposited on the etched bottom electrode to cover the bottom electrode, and a second photomask is used to planarize the dielectric film; then, a third photomask is used to etch the planarized dielectric film to form a second groove; finally, a transition metal oxide film is deposited on the etched dielectric film to cover the dielectric film, and the transition metal oxide film is planarized to obtain the resistive switching layer; thereby avoiding the risk of failure, and reducing the sidewall loss caused by etching by etching before deposition.

[0045] In order to achieve the above embodiments, the present invention provides a resistive switching layer, which is prepared by the above preparation method.

[0046] According to the resistive switching layer of the present invention, the height of R can be reduced by the above preparation method, thereby avoiding the risk of failure. At the same time, the sidewall loss caused by etching can be reduced by etching before deposition.

[0047] In order to achieve the above embodiments, the present invention proposes a resistive switching element, including a bottom electrode, a top electrode, and a resistive switching layer and an oxygen storage layer disposed between the bottom electrode and the top electrode, wherein the resistive switching layer is prepared by the above-described preparation method.

[0048] In order to achieve the above embodiments, the present invention proposes a resistive switching memory, including a plurality of resistive switching elements as described above, wherein the plurality of resistive switching elements are arranged in an array.

[0049] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to magnetic disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0050] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0051] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0052] These computer program instructions may also be loaded onto a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby providing steps for implementing the functions specified in one or more flowcharts and / or one or more blocks of a block diagram.

[0053] It should be noted that any reference signs placed between parentheses in a claim should not be construed as limiting the claim. The word "comprising" does not exclude the presence of components or steps not listed in the claim. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a computer with appropriate programming. In a unit claim listing several means, several of these means may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0054] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0055] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the invention fall within the scope of the claims and their equivalents, the invention also intends to include these modifications and variations.

[0056] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0057] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0058] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower level than the second feature.

[0059] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0060] The above description is merely illustrative and not restrictive. Any equivalent modifications or alterations made to this invention without departing from the spirit and scope thereof should be included in the appended claims.

Claims

1. A method for preparing a resistive switching layer, comprising: A first photomask is used to etch a bottom electrode to form a first groove; a dielectric film is deposited on the etched bottom electrode to cover the bottom electrode, and a second photomask is used to planarize the dielectric film; a third photomask is used to etch the planarized dielectric film to form a second groove; a transition metal oxide film is deposited on the etched dielectric film to cover the dielectric film, and the transition metal oxide film is planarized to obtain a resistive switching layer.

2. The method for preparing the resistive switching layer as described in claim 1, wherein, The transition metal oxide film is planarized by etching, wherein the uniformity of the pit profile is improved by adjusting and monitoring the concentration, flow rate and pressure of the etching gas during etching.

3. The method for preparing the resistive switching layer as described in claim 1, wherein, The transition metal oxide film was planarized by chemical mechanical polishing, wherein the chemical reactivity and surface tension during the polishing process were changed by adjusting the pH value and adding different chemical reagents to improve the uniformity of the pit contour.

4. The method for preparing the resistive switching layer as described in claim 3, characterized in that the dielectric thin film serves as a stop layer for the chemical mechanical polishing or etching.

5. The method for preparing the resistive switching layer as described in claim 1, characterized in that the deposition method is plasma-enhanced chemical vapor deposition.

6. The method for preparing the resistive switching layer as described in claim 1, wherein, The dielectric thin film includes any one of silicon oxide, silicon nitride, or silicon oxynitride.

7. A resistive switching layer, characterized in that it is prepared by any one of claims 1-6.

8. A resistive switching element, comprising a bottom electrode, a top electrode, and a resistive switching layer and an oxygen storage layer disposed between the bottom electrode and the top electrode, wherein, The resistive switching layer is prepared by any one of claims 1-6.

9. A resistive switching memory, characterized in that it comprises a plurality of resistive switching elements as described in claim 8, wherein the plurality of resistive switching elements are arranged in an array.

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