Semiconductor packaging structure and method for manufacturing the packaging structure

Abstract

A method for manufacturing a semiconductor package structure includes the following steps: forming a first packaging unit on the surface of a carrier wafer, comprising a first redistribution layer, a first interconnection portion, a first wafer, a first molding compound, a second redistribution layer, and a second interconnection portion, wherein the second interconnection portion protrudes from and / or is flush with the surface of the second redistribution layer; providing a second packaging unit comprising a third redistribution layer, a third interconnection portion, and a second wafer, wherein the third interconnection portion is flush with and / or protrudes from the surface of the third redistribution layer; assembling and bonding the first packaging unit and the second packaging unit; and removing the carrier wafer to obtain the package structure. This invention employs a silicon-free through-via process, which can reduce costs, improve process yield and capacity utilization, and reduce linewidth and line spacing.

Claims

1. A method for manufacturing a semiconductor package structure, comprising the following steps: A first packaging unit is formed on one surface of a carrier wafer. The first packaging unit includes: a first redistribution layer, a plurality of first connection portions disposed on the surface of the first redistribution layer, at least one first wafer disposed between the first connection portions, a first molding compound layer disposed on the first wafer and the first redistribution layer, a second redistribution layer disposed on the first molding compound layer, and a plurality of second connection portions disposed on the surface of the second redistribution layer. The first connection portions are electrically connected to the first redistribution layer. The surfaces of the first connection portions and the first wafer expose the first molding compound layer. The second redistribution layer is electrically connected to the first connection portions, the first wafer, and the second connection portions. One of the second connection portions protrudes from the surface of the second redistribution layer, and the other of the second connection portions is flush with the surface of the second redistribution layer. A second packaging unit is provided, the second packaging unit including a third redistribution layer, a plurality of third connection portions formed on one surface of the third redistribution layer, and at least one second wafer packaged on another surface of the third redistribution layer, the third redistribution layer being electrically connected to the third connection portions and the second wafer respectively, wherein one of the third connection portions is flush with one surface of the third redistribution layer and the other of the third connection portion protrudes from the surface of the third redistribution layer; the first packaging unit and the second packaging unit are assembled and bonded together, so that the third connection portions are electrically connected to the second connection portions; and the carrier wafer is removed, and a plurality of ball grids are formed on the surface of the first redistribution layer to obtain the packaging structure.

2. The manufacturing method as described in claim 1, wherein the method for preparing the first packaging unit includes: The first interconnect layer is formed on the carrier wafer; A plurality of first connection portions are formed on the surface of the first redistribution layer opposite to the carrier wafer, and the first connection portions are electrically connected to the first redistribution layer; at least one first wafer is flip-chip mounted on the surface of the first redistribution layer opposite to the carrier wafer; the first wafer and the first redistribution layer are encapsulated to form a first encapsulation layer, and the first connection portions and the surface of the first wafer are exposed to the first encapsulation layer; a second redistribution layer is formed on the surface of the first wafer exposed to the first encapsulation layer, and the second redistribution layer is electrically connected to the first connection portions and the first wafer; and a plurality of second connection portions are formed on the surface of the second redistribution layer, and the second connection portions are electrically connected to the second redistribution layer, thereby obtaining the first packaging unit.

3. The manufacturing method as described in claim 1, wherein the method for preparing the second packaging unit includes: The third wiring layer is fabricated, wherein the third wiring layer includes a third trace and a third dielectric layer; a third connection portion is formed on one surface of the third wiring layer, and the third connection portion is electrically connected to the third trace; a second wafer is mounted on the other surface of the third wiring layer opposite to the third connection portion, so that the second wafer is electrically connected to the third trace; and the third wiring layer and the second wafer are encapsulated to form a second encapsulation layer to obtain the second package unit.

4. The manufacturing method as described in claim 1, prior to the step of assembling and bonding the first packaging unit and the second packaging unit, further includes: An adhesive layer is formed on the second rewiring layer, wherein when the second connecting portion protrudes from the surface of the second rewiring layer, the second connecting portion protrudes from the adhesive layer; when the second connecting portion is flush with the surface of the second rewiring layer, the adhesive layer has an opening corresponding to the second connecting portion so that the second connecting portion is exposed in the adhesive layer.

5. The manufacturing method as claimed in claim 1, wherein the first redistribution layer includes a first trace and a first dielectric layer, the first trace being electrically connected to the first connection portion.

6. The manufacturing method as claimed in claim 1, wherein the second redistribution layer includes a second trace and a second dielectric layer, the surface of the first wafer exposed from the first molding compound is provided with at least one metal bump, and the second trace is electrically connected to the first connection portion, the metal bump and the second connection portion.

7. The manufacturing method as claimed in claim 1, wherein the first rewiring layer, the second rewiring layer, and the third rewiring layer are all prepared by layer-addition technology.

8. A semiconductor package structure, comprising: A first packaging unit, comprising: a first redistribution layer; a plurality of ball grids disposed on a surface of the first redistribution layer and electrically connected to the first redistribution layer; a plurality of first connectors disposed on a surface of the first redistribution layer opposite to the ball grids and electrically connected to the first redistribution layer; at least one first wafer disposed between the first connectors; a first molding compound disposed on the first wafer and the first redistribution layer, wherein the surfaces of the first connectors and the first wafer are exposed above the first molding compound; a second redistribution layer disposed on the first molding compound; a plurality of second connectors disposed on the surface of the second redistribution layer; wherein the second redistribution layer is electrically connected to the first connectors, the first wafer, and the second connectors, one of the second connectors protruding from the surface of the second redistribution layer and the other of the second connectors flush with the surface of the second redistribution layer; and a second packaging unit bonded to the first packaging unit, the second packaging unit comprising: a third redistribution layer; A plurality of third connection portions are formed on one surface of the third wiring layer, one of the third connection portions being flush with the surface of the third wiring layer and the other of the third connection portion protruding from the surface of the third wiring layer; at least one second chip is packaged on another surface of the third wiring layer; wherein the third wiring layer is electrically connected to the third connection portion, the second chip, and the second connection portion, respectively, the protruding second connection portion is connected to the flush-mounted third connection portion, and the flush-mounted second connection portion is connected to the protruding third connection portion.

9. The semiconductor packaging structure as claimed in claim 8, characterized in that an adhesive layer is provided between the first packaging unit and the second packaging unit, the second connecting portion passes through the adhesive layer and is electrically connected to the third connecting portion, and the third connecting portion passes through the adhesive layer and is electrically connected to the second connecting portion.

10. The semiconductor packaging structure as claimed in claim 9, wherein the adhesive layer is a photoresist.

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