Static random access memory structure and method of forming the same

TWI939074BActive Publication Date: 2026-09-11UNITED MICROELECTRONICS CORP
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Patent Information

Application Number
TW114123302
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-06-20
Publication Date
2026-09-11
Estimated Expiration
2045-06-19

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  • Figure TWG2TB001910642_003
    Figure TWG2TB001910642_003
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Abstract

This invention provides a static random access memory (SRAM) structure including virtual cells located next to edge cells. Each virtual cell includes six transistors: a first pull-up transistor (PU1), a second pull-up transistor (PU2), a first pull-down transistor (PD1), a second pull-down transistor (PD2), a first transmission gate transistor (PG1), and a second transmission gate transistor (PG2). The first pull-down transistor (PD1) is fixed in an off state. The second transmission gate transistor (PG2), the second pull-down transistor (PD2), the first pull-up transistor (PU1), and the second pull-up transistor (PU2) are each fixed in an on or off state. The virtual cells are configured to stabilize the electrical environment of the edge cells and enhance their noise immunity.
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Claims

1. A static random access memory (SRAM) structure, comprising: a dummy cell located next to an edge cell, the dummy cell comprising six transistors, including a first pull-up transistor (PU1), a second pull-up transistor (PU2), a first pull-down transistor (PD1), a second pull-down transistor (PD2), a first transmission gate transistor (PG1), and a second transmission gate transistor (PG2), wherein: The first pull-down transistor (PD1) is fixed in the OFF state; the second pull-down transistor (PD2) is fixed in the ON state, and the first pull-up transistor (PU1) is fixed in the ON state; the second pull-up transistor (PU2) is fixed in the OFF state; the second transmission transistor (PG2) is fixed in either the ON or OFF state, wherein the virtual unit is configured to stabilize the electrical environment of the edge unit and enhance its noise immunity.

2. The SRAM structure as described in claim 1, wherein the second transmission gate transistor (PG2) is fixed in the OFF state.

3. The SRAM structure as described in claim 1, wherein the edge cell is located on the outermost side of an SRAM array, wherein the SRAM array contains a plurality of main bit cells.

4. The SRAM structure as described in claim 3, wherein the edge cell includes a standard 6T-SRAM circuit structure configured to perform the same read and write operations as the main bit cell of the SRAM array.

5. The SRAM structure as described in claim 1, wherein the virtual cell includes a first internal node (N1) and a second internal node (N2).

6. The SRAM structure as described in claim 5, wherein a voltage source (Vcc) is connected to the first internal node (N1) and a second bit line (BLB).

7. The SRAM structure as described in claim 5, wherein another voltage source (Vss) is connected to a first bit line (BL), the second internal node (N2), and a second word line (WL2).

8. The SRAM structure as described in claim 1, wherein the first transmission gate transistor (PG1) within the virtual cell is connected to a first word line (WL) of the edge cell.

9. A method for forming a static random access memory (SRAM) structure, comprising: forming a dummy cell located next to an edge cell, the dummy cell comprising six transistors, including a first pull-up transistor (PU1), a second pull-up transistor (PU2), a first pull-down transistor (PD1), a second pull-down transistor (PD2), a first transmission gate transistor (PG1), and a second transmission gate transistor (PG2), wherein: The first pull-down transistor (PD1) is fixed in the OFF state; the second pull-down transistor (PD2) is fixed in the ON state, and the first pull-up transistor (PU1) is fixed in the ON state; the second pull-up transistor (PU2) is fixed in the OFF state; the second transmission gate transistor (PG2) is fixed in either the ON or OFF state, wherein the virtual unit is configured to stabilize the electrical environment of the edge unit and enhance its noise immunity.

10. The method as described in claim 9, wherein forming the virtual unit further comprises fixing the second transmission gate transistor (PG2) in an OFF state.

11. The method as described in claim 9 further includes forming the edge cell located on the outermost side of an SRAM array, wherein the SRAM array contains a plurality of main bit cells.

12. The method as described in claim 11, wherein forming the edge cell includes forming a standard 6T-SRAM circuit structure configured to perform the same read and write operations as the main bit cell of the SRAM array.

13. The method as described in claim 9, wherein forming the virtual unit comprises forming a first internal node (N1) and a second internal node (N2).

14. The method as described in claim 13, wherein forming the virtual cell further comprises connecting a voltage source (Vcc) to the first internal node (N1) and a second bit line (BLB).

15. The method as described in claim 13, wherein forming the virtual cell further comprises connecting another voltage source (Vss) to a first word line (BL), the second internal node (N2), and a second word line (WL2).

16. The method as described in claim 9, wherein forming the virtual cell further comprises connecting the first transmission gate transistor (PG1) to a first word line (WL) of the edge cell.

Citation Information

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