Power semiconductor package

Abstract

A power semiconductor package includes a substrate; a wafer attached to the substrate via a double-layer sintered silver bonding structure; and an epoxy molding compound that at least molds the wafer and a portion of the double-layer sintered silver bonding structure. The double-layer sintered silver bonding structure includes a first sintered silver layer on the substrate; and a second sintered silver layer on the first sintered silver layer, with the wafer located on the second sintered silver layer. The first sintered silver layer has a low porosity of less than 5%, and the second sintered silver layer has a low Young's modulus of less than 20 GPa.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and in particular to a power semiconductor package. [Previous Technology]

[0002] In the field of electronics manufacturing, especially for the bonding of discrete components (such as processes that fix chips onto substrates), the current mainstream practice is to use high-lead tin for bonding because it is less expensive. In addition, the heat dissipation efficiency of traditional high-lead tin bonding methods is about 45 W / m·K.

[0003] As the application of high-power chips (e.g., GaN / SiC MOSFETs) becomes more widespread, the requirements for heat dissipation performance are also increasing. In order to further improve the heat dissipation performance of chips, it is necessary to consider using materials with better heat dissipation performance than high lead tin, and sintered silver technology has been proposed as an alternative for this reason.

[0004] However, when applied to wafer bonding, the existing pressureless sintering silver technology still faces some technical challenges. Its main drawback is that the pressureless sintering silver paste may crack and delamination at certain critical locations, such as the interface between the silver paste and the substrate (or support) or the interface between the silver paste and the wafer sidewall. These interface problems will directly affect the reliability of the product. [Summary of the Invention]

[0005] The main objective of this invention is to provide an improved high-power semiconductor package and its manufacturing method to overcome the shortcomings or disadvantages of the prior art.

[0006] One aspect of the present invention provides a power semiconductor package, comprising a substrate; a wafer fixed to the substrate via a double-layer sintered silver bonding structure; and an epoxy molding compound (EMC) that at least molds the wafer and a portion of the double-layer sintered silver bonding structure. The double-layer sintered silver bonding structure includes a first sintered silver layer located on the substrate; and a second sintered silver layer located on the first sintered silver layer, with the wafer located on the second sintered silver layer.

[0007] According to an embodiment of the present invention, the first sintered silver layer has a low porosity of less than 5%, and the second sintered silver layer has a low Young's modulus of less than 20 GPa.

[0008] According to an embodiment of the present invention, the first sintered silver layer has uniform spherical particles at the nanometer to submicron level.

[0009] According to an embodiment of the present invention, the second sintered silver layer has columnar or blocky distributed particles.

[0010] According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer is less than that of the first sintered silver layer.

[0011] According to an embodiment of the present invention, the adhesion between the first sintered silver layer and the substrate is greater than 15 MPa.

[0012] According to an embodiment of the present invention, the wafer is a power wafer.

[0013] According to an embodiment of the present invention, the substrate is a ceramic substrate.

[0014] According to an embodiment of the present invention, the ceramic substrate has a coating, wherein the first sintered silver layer is disposed on the coating.

[0015] According to an embodiment of the present invention, the coating is selected from the group consisting of copper, gold and silver.

[0016] According to an embodiment of the present invention, the first sintered silver layer is used to resist the transverse shear force generated by the mismatch in the coefficients of thermal expansion between the epoxy molding compound and the substrate.

[0017] According to an embodiment of the present invention, the second sintered silver layer is used to buffer the positive shear force caused by the mismatch in the coefficients of thermal expansion between the epoxy molding compound and the edge of the wafer.

[0018] According to an embodiment of the present invention, when a crack begins to appear, the second sintered silver layer is used to prevent the crack from expanding.

[0019] Another aspect of the present invention provides a method for forming a power semiconductor package. First, a substrate is provided; a first silver paste is applied to the substrate; then a second silver paste is applied to the first silver paste; a wafer is disposed on the second silver paste; the first and second silver pastes are subjected to a sintering process to form a double-layer sintered silver bonding structure that fixes the wafer to the substrate; and the wafer is encapsulated with an epoxy molding compound. The double-layer sintered silver bonding structure includes a first sintered silver layer and a second sintered silver layer.

[0020] According to an embodiment of the present invention, the first sintered silver layer has a low porosity of less than 5%.

[0021] According to an embodiment of the present invention, the first sintered silver layer comprises uniform spherical particles at the nanometer to submicron level.

[0022] According to an embodiment of the present invention, the second sintered silver paste layer comprises columnar or blocky distributed particles, and its Young's modulus is less than 20 GPa.

[0023] According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer is less than that of the first sintered silver layer.

[0024] According to an embodiment of the present invention, the adhesion between the first sintered silver layer and the substrate is greater than 15 MPa.

[0025] According to an embodiment of the present invention, the wafer is a power wafer.

[0026] According to an embodiment of the present invention, the substrate is a ceramic substrate.

[0027] According to an embodiment of the present invention, the ceramic substrate has a coating, wherein the first sintered silver layer is disposed on the coating.

[0028] According to an embodiment of the present invention, the coating is selected from the group consisting of copper, gold and silver.

Implementation Method

[0030] The following specific embodiments illustrate the implementation of the "power semiconductor packaging and manufacturing method thereof" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0031] It should be understood that although terms such as “first,” “second,” and “third” may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. In addition, the term “or” as used herein may include, as appropriate, any combination of any one or more of the associated listed items.

[0032] Please refer to Figures 1 to 7, which are schematic diagrams illustrating a method for manufacturing a power semiconductor package according to an embodiment of the present invention. As shown in Figure 1, firstly, a substrate 100 is provided, for example, the substrate may be a ceramic substrate. According to an embodiment of the present invention, the above-mentioned ceramic substrate includes, for example, a direct plated copper (DPC) ceramic substrate, a direct bonded copper (DBC) ceramic substrate, or an active metal brazing (AMB) ceramic substrate, but is not limited thereto. According to another embodiment of the present invention, the substrate 100 may be a leadframe.

[0033] According to an embodiment of the present invention, the substrate 100 includes at least one first plating layer 101 and at least one second plating layer 102. According to an embodiment of the present invention, for example, the first plating layer 101 may be selected from the group consisting of copper, gold and silver, but is not limited thereto. According to an embodiment of the present invention, for example, the second plating layer 102 may be selected from the group consisting of copper, gold and silver, but is not limited thereto.

[0034] Next, a dispensing process is performed to apply a first silver paste 201 onto the first plating layer 101. According to an embodiment of the present invention, the first silver paste 201 can be a pressureless sintered silver paste, which must meet the following three requirements: (1) small and uniform particles; (2) low porosity; and (3) free of columnar or blocky silver particles. According to an embodiment of the present invention, for example, the first silver paste 201 contains uniform spherical particles at the nanometer to submicron level. According to an embodiment of the present invention, for example, the first silver paste 201 has a low porosity of less than 5%. Subsequently, a baking process can be performed on the first silver paste 201 to bring it to a semi-cured state.

[0035] As shown in Figure 2, the dispensing process is then performed again to apply a second silver paste 202 onto the first silver paste 201. According to an embodiment of the present invention, the area of ​​the second silver paste 202 applied can be less than or equal to the top surface area of ​​the first silver paste 201. According to an embodiment of the present invention, the first silver paste 201 can be a pressureless sintered silver paste, which must meet the following two requirements: (1) it contains columnar or blocky silver particles; and (2) the Young's modulus after sintering is less than 20 GPa.

[0036] As shown in Figure 3, a wafer 10 is then placed on the second silver paste 202. According to an embodiment of the present invention, the wafer 10 is, for example, a power wafer. According to an embodiment of the present invention, the wafer 10 is a high-power wafer, for example comprising a gallium nitride metal oxide semiconductor field-effect transistor (GaN MOSFET) or a silicon carbide metal oxide semiconductor field-effect transistor (SiC MOSFET), but is not limited thereto. According to an embodiment of the present invention, the second silver paste 202 contacts the sidewall 10S of the wafer 10. According to an embodiment of the present invention, the wafer 10 does not directly contact the first silver paste 201.

[0037] Then, as shown in Figure 4, the stacked structure in Figure 3 is subjected to a sintering process SP, so that the first silver paste 201 and the second silver paste 202 are sintered to form a double-layer sintered silver bonding structure 200 that fixes the wafer 10 to the substrate 100. According to an embodiment of the present invention, the double-layer sintered silver bonding structure 200 includes a first sintered silver layer 201S and a second sintered silver layer 202S. According to an embodiment of the present invention, the wafer 10 does not directly contact the first sintered silver layer 201S.

[0038] According to an embodiment of the present invention, the first sintered silver layer 201S comprises uniform spherical particles at the nanometer to submicron level and has a low porosity of less than 5%. According to an embodiment of the present invention, the second sintered silver paste layer 202S comprises columnar or blocky particles at the nanometer to micron level, and its Young's modulus is, for example, less than 20 GPa. According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer 202S is less than the Young's modulus of the first sintered silver layer 201S. According to an embodiment of the present invention, the adhesion between the first sintered silver layer 201S and the substrate 100 is greater than 15 MPa.

[0039] According to an embodiment of the present invention, the silver content of the first sintered silver layer 201S is, for example, about 91-93% by weight, and the silver content of the second sintered silver paste layer 202S is, for example, about 85-90% by weight. According to an embodiment of the present invention, the coefficient of thermal expansion of the first sintered silver layer 201S is, for example, about 20-25 PPM / °C, and the coefficient of thermal expansion of the second sintered silver paste layer 202S is, for example, about 26-40 PPM / °C. According to an embodiment of the present invention, the Young's modulus of the first sintered silver layer 201S is, for example, about 17.5-21 GPa, and the Young's modulus of the second sintered silver paste layer 202S is, for example, about 8-17.5 GPa. According to an embodiment of the present invention, the porosity of the first sintered silver layer 201S is, for example, less than 5%, and the porosity of the second sintered silver paste layer 202S is, for example, 10-20%.

[0040] As shown in Figure 5, a wire bonding process is then performed to electrically connect the wafer 10 to the second plating layer 102 using bonding wires WB. According to an embodiment of the present invention, the bonding wires WB may contain copper or gold, but are not limited thereto.

[0041] As shown in Figure 6, a molding process is then performed to form an epoxy molding compound (EMC) 30, which at least molds a portion of the wafer 10, the bonding wire WB, and the double-layer sintered silver bonding structure 200. According to an embodiment of the present invention, the epoxy molding compound 30 directly contacts the sidewall 10S of the wafer 10, the first sintered silver layer 201S, and the second sintered silver layer 202S.

[0042] Finally, as shown in Figure 7, the packaged product is cut, for example, by mechanical cutting or laser cutting, to form a plurality of power semiconductor packages 1. According to an embodiment of the present invention, the first sintered silver layer 201S is composed of uniform spherical silver paste particles at the nanometer to submicron level with a dense and continuous structure, and has low porosity. Furthermore, its adhesion to the substrate 100 is greater than 15 MPa, which is sufficient to resist the lateral shear force generated by the mismatch in the coefficient of thermal expansion (CTE) between the first plating layer 101 and the epoxy molding compound 30, thus preventing cracking at the interface between the first sintered silver layer 201S and the substrate 100. The second sintered silver layer 202S has a low modulus and its silver paste particles are blocky and columnar, thus it can be used to buffer the positive shear force caused by the mismatch in the coefficient of thermal expansion between the epoxy molding compound 30 and the wafer 10. In addition, if conventional nano-sized spherical sintered silver paste is used as the material for the intercalation wafer 10, cracking may occur at the interface between the sintered silver paste and the sidewall of the wafer 10. In a preferred embodiment of the present invention, a second sintered silver layer 202S comprising columnar or blocky particles at the nanometer to micrometer scale is used as the material for the intercalation wafer 10. Because the silver particles in the second sintered silver layer 202S are distributed in a columnar or blocky shape and have a low Young's modulus, crack propagation can be prevented when cracks begin to appear in the second sintered silver layer 202S, thus avoiding cracking at the interface between the second sintered silver layer 202S and the wafer 10.

[0043] This invention combines two pressureless silver pastes with different properties, solving the problem of cracking that may occur at different locations in power semiconductor packaging. The advantages of this invention are that it can maintain high heat dissipation efficiency, reduce the possibility of cracking between the silver paste and the chip side, and maintain the high reliability and performance of power semiconductor packaging.

[0044] Structurally, as shown in Figure 7, the power semiconductor package 1 of the present invention includes a substrate 100 and a wafer 10, which is fixed to the substrate 100 through a double-layer sintered silver bonding structure 200. According to an embodiment of the present invention, the wafer is a power wafer. According to an embodiment of the present invention, the substrate 100 includes, for example, a ceramic substrate, but is not limited thereto. According to an embodiment of the present invention, the ceramic substrate has a first plating layer 101, wherein a first sintered silver layer 201S is disposed on the first plating layer 101. According to an embodiment of the present invention, the first plating layer 101 is selected from the group consisting of copper, gold, and silver.

[0045] According to an embodiment of the present invention, the power semiconductor package 1 further includes an epoxy molding compound 30 molding a portion of the wafer 10 and a portion of a double-layer sintered silver bonding structure 200. According to an embodiment of the present invention, the double-layer sintered silver bonding structure 200 includes a first sintered silver layer 201S located on the substrate 100; and a second sintered silver layer 202S located on the first sintered silver layer 201S.

[0046] According to an embodiment of the present invention, the wafer 10 is fixed on the second sintered silver layer 202S, and the wafer 10 does not directly contact the first sintered silver layer 201S.

[0047] According to an embodiment of the present invention, the first sintered silver layer 201S has a low porosity of less than 5%, and the second sintered silver layer 202S has a low Young's modulus of less than 20 GPa. According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer 202S is less than the Young's modulus of the first sintered silver layer 201S.

[0048] According to an embodiment of the present invention, the first sintered silver layer 201S has uniform spherical particles at the nanometer to submicron level. According to an embodiment of the present invention, the second sintered silver layer 202S has columnar or blocky distributed particles.

[0049] According to an embodiment of the present invention, the adhesion between the first sintered silver layer 201S and the substrate 100 is greater than 15 MPa.

[0050] According to an embodiment of the present invention, the first sintered silver layer 201S is used to resist the transverse shear force generated by the mismatch of the coefficients of thermal expansion between the epoxy molding compound 30 and the substrate 100.

[0051] According to an embodiment of the present invention, the second sintered silver layer 202S is used to buffer the positive shear force caused by the mismatch in the coefficients of thermal expansion between the epoxy molding compound 30 and the wafer 10.

[0052] According to an embodiment of the present invention, when a crack begins to appear, the second sintered silver layer 202S is used to prevent the crack from expanding. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be considered within the scope of the present invention. [Simplified Explanation of the Diagram]

[0029] Figures 1 to 7 are schematic diagrams illustrating a method for manufacturing a power semiconductor package according to an embodiment of the present invention.

Claims

1. A power semiconductor package comprising: a substrate; a wafer, the wafer being fixed to the substrate via a double-layer sintered silver bonding structure; and an epoxy molding compound that at least molds the wafer and a portion of the double-layer sintered silver bonding structure; wherein, The double-layer sintered silver bonding structure comprises: a first sintered silver layer located on the substrate, wherein the adhesion between the first sintered silver layer and the substrate is greater than 15 MPa; and a second sintered silver layer located on the first sintered silver layer and the wafer located on the second sintered silver layer; wherein the first sintered silver layer has a low porosity of less than 5% and has uniform spherical particles at the nanometer to submicron level, and the second sintered silver layer has a low Young's modulus of less than 20 GPa and has columnar or blocky distributed particles.

2. A power semiconductor package, comprising: a substrate; a wafer, the wafer being fixed to the substrate via a double-layer sintered silver bonding structure; and an epoxy molding compound, which at least molds a portion of the wafer and the double-layer sintered silver bonding structure; wherein, The dual-layer sintered silver bonding structure comprises: a first sintered silver layer located on the substrate, wherein the adhesion between the first sintered silver layer and the substrate is greater than 15 MPa; and a second sintered silver layer located on the first sintered silver layer and the wafer located on the second sintered silver layer; wherein the first sintered silver layer has a low porosity of less than 5%, and the second sintered silver layer has a low Young's modulus of less than 20 GPa, wherein the first sintered silver layer has uniform spherical particles at the nanometer to submicron level.

3. A power semiconductor package, comprising: a substrate; a wafer, the wafer being fixed to the substrate via a double-layer sintered silver bonding structure; and an epoxy molding compound, which at least molds a portion of the wafer and the double-layer sintered silver bonding structure; wherein, The double-layer sintered silver bonding structure comprises: a first sintered silver layer located on the substrate, wherein the adhesion between the first sintered silver layer and the substrate is greater than 15 MPa; and a second sintered silver layer located on the first sintered silver layer and the wafer located on the second sintered silver layer; wherein the first sintered silver layer has a low porosity of less than 5%, and the second sintered silver layer has a low Young's modulus of less than 20 GPa, wherein the second sintered silver layer has columnar or blocky distributed particles.

4. The power semiconductor package as described in claim 1, wherein, The Young's modulus of the second sintered silver layer is less than that of the first sintered silver layer.

5. The power semiconductor package as described in claim 1, wherein, The substrate is a ceramic substrate, and the chip is a power chip.

6. The power semiconductor package as described in claim 5, wherein, The ceramic substrate has a coating, wherein the first sintered silver layer is disposed on the coating.

7. The power semiconductor package as described in claim 6, wherein, The coating is selected from the group consisting of copper, gold and silver.

8. The power semiconductor package as described in claim 1, wherein, The first sintered silver layer is used to resist the lateral shear force generated by the mismatch in the coefficients of thermal expansion between the epoxy molding compound and the substrate.

9. The power semiconductor package as described in claim 1, wherein, The second sintered silver layer is used to buffer the positive shear force caused by the mismatch in the coefficients of thermal expansion between the epoxy molding compound and the wafer.

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