Register circuit and register circuit control

Abstract

A temporary register circuit includes: a first D-type flip-flop, each including a first scan control terminal; a second D-type flip-flop, each including a second scan control terminal; a first test circuit that generates a first control signal to the first scan control terminals based on a test mode signal and a scan enable signal; and a second test circuit that generates a second control signal to the second scan control terminals based on the test mode signal and the scan enable signal. The first D-type flip-flop and the second D-type flip-flop operate in one of a normal mode, a scan shift mode, and a scan acquisition mode, respectively, based on the first control signal and the second control signal.

Claims

1. A register circuit, comprising: a plurality of first D-type flip-flops, each of the first D-type flip-flops including a first scan control terminal; a plurality of second D-type flip-flops, each of the second D-type flip-flops including a second scan control terminal, wherein at least one of the first D-type flip-flops directly outputs to one of the second D-type flip-flops; a first test circuit coupled to the first scan control terminals, the first test circuit being configured to receive a test mode signal and a scan enable signal, and generate a first control signal to the first scan control terminals based on the test mode signal and the scan enable signal; and a second test circuit coupled to the second scan control terminals, the second test circuit being configured to receive the test mode signal and the scan enable signal and generate a second control signal to the second scan control terminals; The first D-type flip-flops operate in one of a normal mode, a scan shift mode, and a scan acquisition mode according to the first control signal; the second D-type flip-flops operate in one of the normal mode, the scan shift mode, and the scan acquisition mode according to the second control signal.

2. The register circuit as claimed in claim 1, wherein one of the first D-type flip-flops is an initial D-type flip-flop among the first D-type flip-flops and the second D-type flip-flops; the initial D-type flip-flops perform the function of a D-type flip-flop in the normal mode; wherein in the scan shift mode, a data terminal of the initial D-type flip-flop receives a test signal; wherein in the scan acquisition mode, a test terminal of the initial D-type flip-flop receives a predetermined signal, and an output terminal of the initial D-type flip-flop outputs an output signal, the output signal being related to the predetermined signal.

3. The register circuit as described in claim 2, wherein the output signal and the predetermined signal have the same value.

4. The register circuit as claimed in claim 2, wherein if both the test mode signal and the scan enable signal are first logic values, the start D-type flip-flop operates in the normal mode; if both the test mode signal and the scan enable signal are second logic values, the start D-type flip-flop operates in the scan shift mode; and if the test mode signal is the second logic value and the scan enable signal is the first logic value, the start D-type flip-flop operates in the scan acquisition mode.

5. The register circuit as claimed in claim 1, wherein the first test circuit comprises: a first multiplexer, a first input of the first multiplexer receiving the scan enable signal, a selection input of the first multiplexer receiving the test mode signal, and outputting the first control signal; and a first OR gate, the output of which is coupled to a second input of the first multiplexer, a first input of the first OR gate receiving a first controllable value, and a second input of the first OR gate receiving the scan enable signal.

6. The register circuit as claimed in claim 5, wherein the first controllable value is generated by a D-type flip-flop.

7. The register circuit as claimed in claim 5, wherein the second test circuit comprises: a second multiplexer, a first input of the second multiplexer receiving the scan enable signal, a selection input of the second multiplexer receiving the test mode signal, and outputting the second control signal; and a second OR gate, the output of which is coupled to a second input of the second multiplexer, a first input of the second OR gate receiving a second controllable value, and a second input of the second OR gate receiving the scan enable signal.

8. The register circuit as claimed in claim 7, wherein the second controllable value is generated by a D-type flip-flop.

9. The register circuit as claimed in claim 1, the circuit test system further comprising: a third test circuit for receiving the test mode signal and the scan enable signal, and generating a third control signal to the integrated clock gating circuit based on the test mode signal and the scan enable signal; wherein the ICG circuit operates in one of the normal mode, the scan shift mode, and the scan acquisition mode based on the third control signal.

10. A register circuit control method, comprising: generating a first control signal to a plurality of first D-type flip-flops according to a test mode signal and a scan enable signal; generating a second control signal to a plurality of second D-type flip-flops according to the test mode signal and the scan enable signal; the first D-type flip-flops operating according to the first control signal in one of a normal mode, a scan shift mode, and a scan acquisition mode; and the second D-type flip-flops operating according to the second control signal in one of the normal mode, the scan shift mode, and the scan acquisition mode, wherein at least one of the first D-type flip-flops directly outputs to one of the second D-type flip-flops.

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