Method of manufacturing semiconductor structure using hard mask between nitride-containing layer and carbon-containing layer

TWI939098BActive Publication Date: 2026-09-11NAN YA TECH
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Patent Information

Application Number
TW114125462
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Priority Date
2025-03-24
Filing Date
2025-07-04
Publication Date
2026-09-11
Estimated Expiration
2045-07-03

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Abstract

This application discloses a method for manufacturing a semiconductor structure. The method includes: sequentially forming a bit line stack on a substrate; forming a nitride-containing layer on the bit line stack; forming a hard mask layer on the nitride-containing layer; and forming a carbon-containing layer on the hard mask layer, wherein the hard mask layer comprises a metal oxide, and the hard mask layer is etched at a rate greater than the nitride-containing layer is etched with an etchant; patterning the carbon-containing layer to expose the hard mask layer; removing a portion of the hard mask layer to form a hard mask, thereby exposing a portion of the nitride-containing layer; removing the carbon-containing layer after forming the hard mask; and using the hard mask to pattern the nitride-containing layer and the bit line stack to form a bit line and a nitride-containing component.
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Claims

1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided having an active region, wherein the active region includes an isolation structure and a contact adjacent to the isolation structure; a bit line stack is formed on the substrate; a nitride-containing layer is formed on the bit line stack; a hard mask layer is formed on the nitride-containing layer, wherein the hard mask layer includes a metal oxide, and the hard mask layer is etched at a rate greater than the nitride-containing layer is etched by the etchant; a carbon-containing layer is formed on the hard mask layer; and the carbon-containing layer is patterned to expose a portion of the hard mask layer. Remove a portion of the hard mask layer to form a hard mask with an opening, thereby exposing a portion of the nitride layer; after forming the hard mask, remove the carbon layer; and use the hard mask to pattern the nitride layer and the bit line stack to form a bit line on the contact and a nitride component on the bit line.

2. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the bit line is formed after the carbon-containing layer is removed.

3. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the hard mask layer does not contain carbon or nitrides.

4. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the hard mask layer comprises a metal oxide.

5. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the hard mask layer comprises zirconium dioxide (ZrO2), hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si-doped HfO2, HSO), lanthanum trioxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium silicon oxide (ZrSiO4), or a combination thereof.

6. The method for manufacturing a semiconductor structure as described in claim 1 further includes: After the bit line is formed, remove the hard mask.

7. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the carbon-containing layer is less than the thickness of the nitride-containing layer.

8. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the nitride-containing layer is greater than twice the thickness of the carbon-containing layer.

9. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the bit line stack is less than the thickness of the nitride-containing layer.

10. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the hard mask layer is less than the thickness of the carbon-containing layer.

11. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the formation of the bit line stack comprises: A barrier layer is formed on the substrate; A conductive layer is formed on the barrier layer, wherein the nitride-containing layer is formed on the conductive layer.

12. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein patterning the stack of bit lines to form the bit lines comprises: A first portion is formed coupled to the contact; And forming a second portion disposed on the first portion, wherein the second portion is formed prior to the first portion, and a first width of the first portion is substantially equal to a second width of the second portion.

13. A method for manufacturing a semiconductor structure as claimed in claim 12, wherein the first part comprises titanium nitride.

14. A method of manufacturing a semiconductor structure as claimed in claim 12, wherein the second part comprises tungsten.

Citation Information

Patent Citations

  • Semiconductor device

    TW202512470A