Semiconductor device and method of fabricating thereof

Abstract

A semiconductor device includes: a substrate layer; a first transistor and a second transistor located above the substrate layer; a first memory cell located above the substrate layer; a first word line located above the substrate layer and electrically connected to the first memory cell, wherein the first word line is located at a first height and the first transistor is electrically connected to the first word line; a second memory cell located above the substrate layer; and a second word line located above the substrate layer and electrically connected to the second memory cell, wherein the second word line is located at a second height above the first height and the second transistor is electrically connected to the second word line.

Claims

1. A semiconductor device, comprising: One substrate layer; A first transistor and a second transistor are located above the substrate layer; A first memory cell located above the substrate layer; A first word line located above the substrate layer and electrically connected to the first memory cell, wherein the first word line is at a first height and the first transistor is electrically connected to the first word line; a first conductive via located above the substrate layer and electrically connected to the first transistor and the first word line; a second memory cell located above the substrate layer; a second word line located above the substrate layer and electrically connected to the second memory cell, wherein the second word line is at a second height above the first height and the second transistor is electrically connected to the second word line; and a second conductive via located above the substrate layer and electrically connected to the second transistor and the second word line, wherein a top surface of the first conductive via is lower than a top surface of the second conductive via, and wherein a bottom surface of the first conductive via and a bottom surface of the second conductive via are located on a top surface of the substrate layer.

2. The apparatus as claimed in claim 1, wherein a height of the second memory cell is greater than a height of the first memory cell.

3. The apparatus as claimed in claim 1, wherein the first memory cell includes a first access transistor and a first capacitor, the first access transistor being located above the first capacitor.

4. The apparatus as claimed in claim 3, wherein the second memory cell includes a second access transistor and a second capacitor, the second capacitor being located above the second access transistor.

5. The apparatus as claimed in claim 3 further includes a bottom dielectric layer located between the substrate layer and the first capacitor of the first memory cell.

6. The apparatus as claimed in claim 1 further includes a bit line located between and electrically connected to the first memory cell and the second memory cell.

7. The apparatus as claimed in claim 6, wherein the bit line is located at a third height between the first height and the second height.

8. A method for manufacturing a semiconductor device, comprising: Form a substrate layer; A first transistor and a second transistor are formed above the substrate layer; A first conductive via is formed above the substrate layer and electrically connected to the first transistor; a first word line and a first memory cell are formed above the substrate layer and electrically connected to each other, wherein the first word line is located at a first height and the first transistor is electrically connected to the first word line, wherein the first word line is electrically connected to the first conductive via; a second conductive via is formed above the substrate layer and electrically connected to the second transistor, wherein a top surface of the first conductive via is lower than a top surface of the second conductive via, and wherein a bottom surface of the first conductive via and a bottom surface of the second conductive via are located at a top surface of the substrate layer; and a second word line and a second memory cell are formed above the substrate layer and electrically connected to each other, wherein the second word line is located at a second height higher than the first height and the second transistor is electrically connected to the second word line, wherein the second word line is electrically connected to the second conductive via.

9. The method as described in claim 8, wherein the second memory cell is formed at a higher height than the first memory cell.

10. The method as described in claim 8, wherein the first memory cell includes a first capacitor and a first access transistor located above the first capacitor.

11. The method of claim 10, wherein the second memory cell includes a second capacitor and a second access transistor located below the second capacitor.

12. The method as described in claim 8, further comprising: Before forming the first memory cell, a bottom dielectric layer is formed above the substrate layer, wherein the first memory cell is formed on the bottom dielectric layer.

13. The method as described in claim 8, further comprising: A bit line is formed that is electrically connected to the first memory cell, wherein the second memory cell is formed on the bit line and electrically connected to it.

14. The method as described in claim 13, further comprising: Before the bit line is formed, a first contact is formed above the first memory cell and electrically connected to the first memory cell, wherein the bit line is formed above the first contact; and after the bit line is formed, a second contact is formed above the bit line and electrically connected to the bit line.

15. The method as described in claim 13, wherein the bit line is formed at a third height between the first height and the second height.

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