Electronic device

TWI939108BActive Publication Date: 2026-09-11GLOBAL UNICHIP CORPORATION +1
View PDF 6 Cites 0 Cited by

Patent Information

Application Number
TW114126523
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-07-14
Publication Date
2026-09-11
Estimated Expiration
2045-07-13

Smart Images

  • Figure TWG2TB001910676_001
    Figure TWG2TB001910676_001
  • Figure TWG2TB001910676_002
    Figure TWG2TB001910676_002
  • Figure TWG2TB001910676_003
    Figure TWG2TB001910676_003
Patent Text Reader

Abstract

An electronic device includes a packaging substrate and a semiconductor wafer bonded to the wafer side of the packaging substrate. The packaging substrate provides a first signal transmission pair and a second signal transmission pair. The first signal transmission pair includes two adjacent first signal transmission structures. Each first signal transmission structure includes a first wafer-side vertical segment, a first outer vertical segment, and a first intermediate segment. The second signal transmission pair includes two second signal transmission structures. Each second signal transmission structure includes a second wafer-side vertical segment, a second outer vertical segment, and a second intermediate segment. The overlap length between the first wafer-side vertical segment and the second wafer-side vertical segment is L, and the lateral spacing between the first signal transmission pair and the second signal transmission pair is P, where 0.1 < L / P < 0.38.
Need to check novelty before this filing date? Find Prior Art

Claims

1. An electronic device comprising: A packaging substrate having a wafer side and an outer side relative to the wafer side, and providing: a first signal transmission pair including two first signal transmission structures, wherein each of the two first signal transmission structures includes a first wafer-side longitudinal segment, a first outer longitudinal segment, and a first intermediate segment connecting the first wafer-side longitudinal segment and the first outer longitudinal segment; a second signal transmission pair adjacent to the first signal transmission pair and including two second signal transmission structures, wherein each of the two second signal transmission structures includes a second wafer-side longitudinal segment, a second outer longitudinal segment, and a second intermediate segment connecting the second wafer-side longitudinal segment and the second outer longitudinal segment, wherein the overlap length of the first wafer-side longitudinal segment and the second wafer-side longitudinal segment is L, the lateral spacing between the first signal transmission pair and the second signal transmission pair is P, and 0.1 < L / P < 0.38; a semiconductor wafer bonded to the wafer side of the packaging substrate and electrically connected to the first signal transmission pair and the second signal transmission pair.

2. The electronic device of claim 1, wherein the lateral spacing between the first signal transmission pair and the second signal transmission pair is the distance between the centerline of the first wafer-side longitudinal segment of the two first signal transmission structures and the centerline of the second wafer-side longitudinal segment of the two second signal transmission structures.

3. The electronic device as claimed in claim 1, wherein the extending direction of the first wafer-side longitudinal segment is parallel to the extending direction of the second wafer-side longitudinal segment.

4. The electronic device as claimed in claim 1, wherein the packaging substrate further includes a plurality of wafer bonding pads located on the wafer side and a plurality of outer bonding pads located on the outer side.

5. The electronic device as claimed in claim 4, wherein the spacing of the wafer bonding pads is smaller than the spacing of the outer bonding pads.

6. The electronic device of claim 4, wherein the two first signal transmission structures are connected on the wafer side to two wafer bonding pads of the wafer bonding pads and on the outer side to two outer bonding pads of the outer bonding pads.

7. The electronic device of claim 6, wherein the spacing between the two first signal transmission structures is equal to the spacing between the two wafer bonding pads.

8. The electronic device of claim 4, wherein the two second signal transmission structures are connected on the wafer side to two wafer bonding pads of the wafer bonding pads and on the outer side to two outer bonding pads of the outer bonding pads.

9. The electronic device as claimed in claim 4 further includes a plurality of wafer bonding members through which the semiconductor wafer is bonded to the wafer bonding pad.

10. The electronic device of claim 1, wherein one of the first signal transmission pair and the second signal transmission pair transmits a transmission signal and the other transmits a reception signal.

11. The electronic device of claim 1, wherein the spacing of the first wafer-side longitudinal segments is smaller than the spacing of the first outer longitudinal segments.

12. The electronic device of claim 1, wherein the spacing of the second wafer-side longitudinal segments is smaller than the spacing of the second outer longitudinal segments.

13. The electronic device of claim 1, wherein the packaging substrate includes multiple conductive wiring layers and multiple conductive via layers, the conductive wiring layers and the conductive via layers being alternately disposed to establish the first signal transmission pair and the second signal transmission pair.

14. The electronic device of claim 13, wherein the first wafer-side longitudinal segment is formed by an M layer in the conductive wiring layer adjacent to the wafer side and an M layer in the conductive via layer adjacent to the wafer side, and M is a positive integer.

15. The electronic device of claim 14, wherein the second wafer-side longitudinal segment is formed by N layers of the conductive wiring layer adjacent to the wafer side and N layers of the conductive via layer adjacent to the wafer side, and N is a positive integer.

16. The electronic device as claimed in claim 15, wherein M is not equal to N.

17. The electronic device as claimed in claim 15, wherein M equals N.

18. The electronic device as claimed in claim 1 further includes a plurality of outer bonding members disposed on the outer side of the packaging substrate.

19. The electronic device of claim 1, further comprising a cover coupled to the packaging substrate, and the semiconductor wafer encapsulated between the packaging substrate and the cover.

20. The electronic device of claim 19 further includes an interface material disposed between the semiconductor wafer and the cover.

Citation Information

Patent Citations

  • Ball grid array package and packaging substratre thereof

    TW202220137A

  • Molded direct contact interconnect structure without capture pads and method for the same

    TW202412117A

  • Semiconductor device and method of forming the same

    TW202416478A

  • Integrated circuit chip, package substrate and electronic assembly

    US11735502B2

  • Fan-out semiconductor package

    US20240162132A1