Bit line stack structure of memory device and manufacturing method thereof

Abstract

A bitline stacking structure for a memory element and a method for manufacturing the same. The bitline stacking structure includes bitlines, bitline contact structures, and spacer structures. The bitlines are disposed on a substrate, wherein the substrate has an active region, and the bitlines extend in a first direction across the active region. The bitline contact structures are disposed between the bitlines and the active region, and electrically connect the bitlines to the active region. The spacer structures cover the sidewalls of the bitlines and the sidewalls of the bitline contact structures, and include a first spacer, a second spacer, and a third spacer. The first spacer includes a first portion and a second portion, the first portion covering the sidewall of the bitlines, the second portion covering the sidewall of the bitline contact structures, and a first thickness of the first portion being less than a second thickness of the second portion. The second spacer is located on the first portion of the first spacer. The third spacer is located on the second portion of the first spacer.

Claims

1. A bit-line stacking structure for memory elements, comprising: A bit line is disposed on a substrate, wherein the substrate has an active region, and the bit line extends in a first direction across the active region; A bit line contact structure is disposed between the bit line and the active region, and electrically connects the bit line to the active region; The system includes a gap wall structure covering the sidewalls of the bit lines and the sidewalls of the bit line contact structure, comprising a first gap wall, a second gap wall, and a third gap wall, wherein: the first gap wall comprises a first portion and a second portion, the first portion covering the sidewalls of the bit lines, the second portion covering the sidewalls of the bit line contact structure, and the first thickness of the first portion being less than the second thickness of the second portion; the second gap wall is located on the first portion of the first gap wall; and the third gap wall is located on the second portion of the first gap wall.

2. The bit-line stacking structure of memory elements as claimed in claim 1, wherein the material of the first spacer wall comprises a low dielectric constant material.

3. The bit-line stacking structure of memory elements as claimed in claim 1, wherein the material of the second spacer wall comprises a low dielectric constant material.

4. The bit line stacking structure of memory elements as claimed in claim 1, wherein the material of the first spacer wall is the same as the material of the second spacer wall.

5. The bit line stacking structure of the memory element as claimed in claim 1, wherein the total thickness of the second gap wall and the first portion of the first gap wall is not less than the second thickness of the second portion of the first gap wall.

6. The bit line stacking structure of the memory element as claimed in claim 5, wherein the ratio of the total thickness of the second spacer wall and the first portion of the first spacer wall to the second thickness of the second portion of the first spacer wall is between 1 and 2.

7. The bit-line stacking structure of memory elements as claimed in claim 1, wherein the material of the third spacer wall comprises a high dielectric constant material.

8. The bit-line stacking structure of memory elements as claimed in claim 1, wherein the second portion of the first gap wall covers the sidewall and bottom surface of the third gap wall.

9. The bit line stacking structure of the memory element as claimed in claim 1, further comprising a cover layer, wherein the cover layer is disposed on the top surface of the bit line.

10. The bit line stacking structure of memory elements as claimed in claim 9, wherein the first gap wall further includes a third portion, the third portion covering the sidewall of the cover layer, and the third thickness of the third portion being greater than the first thickness of the first portion and less than the second thickness of the second portion.

11. A method for manufacturing a bit-line stacked structure of a memory element, comprising: A substrate is provided, wherein the substrate has an active region; A bit line is formed on the substrate, wherein the bit line extends in a first direction and crosses the active region; a bit line contact structure is formed between the bit line and the active region, wherein the bit line contact structure electrically connects the bit line to the active region; A gap wall structure is formed to cover the sidewalls of the bit line and the sidewalls of the bit line contact structure, wherein the gap wall structure includes a first gap wall, a second gap wall, and a third gap wall, wherein: the first gap wall includes a first portion and a second portion, the first portion covers the sidewalls of the bit line, the second portion covers the sidewalls of the bit line contact structure, and the first thickness of the first portion is less than the second thickness of the second portion; the second gap wall is located on the first portion of the first gap wall; and the third gap wall is located on the second portion of the first gap wall.

12. A method for manufacturing a bit line stack structure of a memory element as claimed in claim 11, wherein the total thickness of the second gap wall and the first portion of the first gap wall is not less than the second thickness of the second portion of the first gap wall.

13. A method of manufacturing a bit-line stack structure of a memory element as claimed in claim 12, wherein the ratio of the total thickness of the second spacer wall to the first portion of the first spacer wall to the second thickness of the second portion of the first spacer wall is between 1 and 2.

14. A method for manufacturing a bit-line stacked structure of a memory element as described in claim 11, wherein the method for forming the spacer wall structure includes: After forming the bit line and the bit line contact structure, a first gap wall material layer is conformally formed on the substrate to form the first gap wall; A second spacer wall material layer is conformally formed on the first spacer wall; a portion of the second spacer wall material layer is removed to form the third spacer wall; a third spacer wall material layer is conformally formed on the substrate; and a portion of the third spacer wall material layer is removed to form the second spacer wall.

15. A method for manufacturing a bit-line stack structure of a memory element as claimed in claim 14, wherein the method for removing a portion of the second spacer wall material layer includes performing an isotropic etching process.

16. A method for manufacturing a bit-line stack structure of a memory element as claimed in claim 14, wherein the method for removing a portion of the third spacer wall material layer includes performing an anisotropic etching process.

17. A method for manufacturing a bit-line stack structure of a memory element as claimed in claim 14, wherein the materials of the first spacer layer and the third spacer layer each comprise a low dielectric constant material.

18. A method for manufacturing a bit-line stack structure of a memory element as claimed in claim 14, wherein the material of the second spacer wall material layer comprises a high dielectric constant material.

19. The method of manufacturing a bit line stack structure of a memory element as described in claim 11, further comprising forming a capping layer on the top surface of the bit lines.

20. A method of manufacturing a bit-line stack structure of a memory element as claimed in claim 19, wherein the first gap wall further includes a third portion, the third portion covering the sidewall of the cover layer, and the third thickness of the third portion being greater than the first thickness of the first portion and less than the second thickness of the second portion.

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