Analog-to-digital conversion apparatus and reset method thereof having lookahead mechanism of reset activation

Abstract

An analog-to-digital converter (ADC) with a pre-start reset mechanism is disclosed. The ADC circuit includes a capacitor array, a comparator circuit, and a control circuit. The control circuit causes the capacitor array to receive a sampled voltage at the start of the conversion process. Based on a sequential asymptotic mechanism, the comparator circuit continuously compares the output voltage of the capacitor array to generate a comparison result. It then sequentially generates counting signals with drive states transitioning from a first state to a second state to control the capacitor array to switch the switchable bit capacitors bit by bit. The pre-start reset circuit generates a pre-start reset signal with a reset state based on the second state of the pre-start count signal, where the drive state is earlier than the last comparison by the comparator circuit. This resets the switchable bit capacitors in the capacitor array.

Claims

1. An analog-to-digital converter with a lookahead reset mechanism, comprising: an analog-to-digital conversion circuit including: a capacitor array comprising a plurality of switchable bit capacitors; a comparator circuit; and a control circuit configured to receive at least one sampled voltage at the start of a current conversion sequence and, during the current conversion sequence, according to a successive... An approximation mechanism controls the comparator circuit to continuously compare at least one output voltage generated by the capacitor array to produce a comparison result. Based on the comparison result, a plurality of count signals with a drive transition state that transitions from a first state to a second state are generated sequentially to control the capacitor array to switch the plurality of switchable bit capacitors bit by bit. A pre-start reset circuit generates a pre-start reset signal with a reset state based on the second state of the pre-start count signal with the drive transition state that is earlier than the last comparison of the comparator circuit, to control the capacitor array to reset the plurality of switchable bit capacitors for the next conversion procedure.

2. The analog-to-digital converter as described in claim 1, wherein the pre-start reset circuit generates the pre-start reset signal having the reset state at the moment when the pre-start count signal has the drive state, or generates the pre-start reset signal having the reset state after a preset time following the pre-start count signal having the drive state.

3. The analog-to-digital converter as described in claim 1, wherein each of the plurality of switchable bit capacitors includes an upper plate for receiving the at least one sampled voltage and connected to the comparator circuit, and a lower plate for switching to receive one of two DC voltages; the capacitor array is reset by switching the lower plate of each of the plurality of switchable bit capacitors to receive one of the two DC voltages.

4. The analog-to-digital converter as described in claim 1, wherein each of the plurality of switchable bit capacitors includes an upper plate for receiving the at least one sampling voltage and connected to the comparator circuit, and a lower plate for switching to receive one of two DC voltages; the capacitor array is reset by connecting the upper plate of each of the plurality of switchable bit capacitors to a reset DC voltage, short-circuiting the upper plates of each of the plurality of switchable bit capacitors to each other, or short-circuiting the upper plates of each of the plurality of switchable bit capacitors to each other and connecting them to the reset DC voltage.

5. The analog-to-digital converter as claimed in claim 1, wherein the capacitor array further includes a switching circuit comprising: a plurality of flip-flops, each flip-flop corresponding to one of the plurality of switchable bit capacitors, and comprising: a data input configured to receive the comparison result of the comparison circuit, the comparison result being one of two DC voltages; and a data output. A driving terminal is configured to receive one of the plurality of counting signals corresponding to a counting signal, so as to cause the data output terminal to output the comparison result to the corresponding switchable bit capacitor when the corresponding counting signal has the driving transition state; and a reset terminal; and wherein the pre-start reset circuit is configured to receive a sampling control signal and the pre-start counting signal, so as to generate the pre-start reset signal having the reset state to the reset terminal of each of the plurality of switching flip-flops according to a sampling state of the sampling control signal or the second state of the pre-start counting signal, so as to cause each of the plurality of switching flip-flops to output one of the two DC voltages to reset the corresponding switchable bit capacitor; wherein the sampling control signal controls the capacitor array to receive the sampling voltage in the sampling state, and controls the capacitor array to stop receiving the sampling voltage in a non-sampling state, and the control circuit controls the capacitor array to switch the plurality of switchable bit capacitors bit by bit according to the sequential asymptotic mechanism.

6. An analog-to-digital converter as described in claim 5, wherein the drive terminal of each of the plurality of flip-flops outputs the comparison result to the corresponding switchable bit capacitor via a plurality of inverters.

7. The analog-to-digital converter as claimed in claim 1, wherein the control circuit includes a counting circuit for generating the plurality of counting signals, the counting circuit including a plurality of counter flip-flops connected in series, each counter flip-flop including: a data input terminal; a data output terminal electrically coupled to the data input terminal of a subsequent counter flip-flop; a drive terminal configured to receive a comparison control signal controlling the operation of the comparison circuit; and a reset terminal; The plurality of counterswitches includes a first counter that receives an input signal having the second state; each counter that receives the data input signal outputs a data signal as one of the plurality of counter signals when the comparison control signal has a comparison stop state; and stops outputting the data input signal to the data output when the comparison control signal has a comparison proceed state; and each counter that receives the pre-start reset signal having the reset state at the reset terminal resets the data output to the first state.

8. A method for resetting an analog-to-digital converter (ADC) device with a pre-start reset mechanism, comprising: causing a control circuit included in an analog-to-digital converter circuit to cause a capacitor array included in the analog-to-digital converter circuit to receive at least one sampled voltage at the start of a current conversion program, wherein the capacitor array includes a plurality of switchable bit capacitors; and during the current conversion program, causing the control circuit to control a comparator circuit included in the analog-to-digital converter circuit to continuously compare with at least one output voltage generated by the capacitor array according to a sequential asymptotic mechanism to generate a comparison result; The control circuit generates a plurality of count signals, each having a drive transition state that transitions from a first state to a second state, according to the comparison result, to control the capacitor array to switch the plurality of switchable bit capacitors bit by bit; and a pre-start reset circuit generates a pre-start reset signal having a reset state according to the second state of the pre-start count signal with the drive transition state that is earlier than the last comparison of the comparison circuit, according to the plurality of count signals, to control the capacitor array to reset the plurality of switchable bit capacitors to perform the next conversion procedure.

9. The analog-to-digital converter reset method as described in claim 8 further comprises: generating the pre-start reset signal having the reset state at the moment when the pre-start count signal has the drive state, or generating the pre-start reset signal having the reset state after a preset time delay following the pre-start count signal having the drive state.

10. The analog-to-digital converter reset method as described in claim 8, wherein the control circuit includes a counting circuit for generating the plurality of counting signals, the counting circuit including a plurality of counter flip-flops connected in series, each counter flip-flop including a data input terminal, a data output terminal electrically coupled to the data input terminal of a subsequent counter flip-flop, a drive terminal configured to receive a comparison control signal controlling the operation of the comparison circuit, and a reset terminal, the analog-to-digital converter reset method further including: causing a first counter flip-flop of the plurality of counter flip-flops to receive an input signal having the second state; Each of the plurality of counter flip-flops outputs a data signal from its data input terminal to its data output terminal as one of the plurality of counting signals when the comparison control signal has a comparison stop state, and stops outputting the data signal from its data input terminal to its data output terminal when the comparison control signal has a comparison in progress state; and each of the plurality of counter flip-flops resets its data output terminal to the first state when it receives the pre-start reset signal having the reset state at the reset terminal.

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