Semiconductor device, semiconductor structure, and method for manufacturing semiconductor structure

Abstract

A semiconductor device includes a substrate, a plurality of bumps, and a wafer. The substrate has a top surface and a bottom surface. The substrate includes a plurality of bottom contacts, a plurality of top contacts, a first wiring layer, a second wiring layer, a metal heat sink, a recess, and a voltage regulator. The first wiring layer is disposed between the top and bottom surfaces. The second wiring layer is located on the first wiring layer. The metal heat sink is disposed between the first and second wiring layers. The recess is disposed on one side of the substrate. A portion of the first wiring layer is exposed at the bottom of the recess. The voltage regulator is disposed in the recess and electrically connected to the first wiring layer. Each bump is electrically connected to its respective top contact.

Description

Technical Field

[0001] This case relates to an advanced packaging technology, and in particular to a semiconductor device and semiconductor structure that can improve transmission speed, heat dissipation performance and power supply stability. Prior Technology

[0002] In the current common upper and lower layer packaging structures, the upper layer packaging structure usually adopts the wire-bonding process, while the lower layer packaging structure adopts the flip chip process.

[0003] However, this structure has the following technical drawbacks. First, the wire bonding process used in the upper packaging structure limits high-speed signal transmission, hindering the achievement of higher data transmission speeds in this upper and lower packaging structure. Second, due to the characteristics of the molding process, the upper die cannot effectively dissipate heat, potentially causing overheating problems and affecting its stability and performance. Third, the substrate design and materials limit the heat dissipation efficiency of the lower die, causing heat accumulation and affecting its performance and stability. Finally, because the power stabilizing components (such as voltage regulators) in the lower packaging structure are usually placed on the outside of the substrate, the power supply path is longer, leading to decreased power output stability and an inability to effectively support stable and efficient operation. Summary of the Invention

[0004] In some embodiments, a semiconductor device includes a substrate, a plurality of bumps, and a wafer. The substrate has an upper surface and a lower surface. The substrate includes a plurality of lower contacts, a plurality of upper contacts, a first wiring layer, a second wiring layer, a plurality of first conductive vias, a plurality of second conductive vias, a plurality of third conductive vias, a metal heat sink, a recess, and a voltage regulator. The plurality of lower contacts are disposed on the lower surface. The plurality of upper contacts are disposed on the upper surface. The first wiring layer is disposed between the upper and lower surfaces. The second wiring layer is disposed between the upper and lower surfaces and is located on the first wiring layer. The first wiring layer is electrically connected to the plurality of lower contacts via the plurality of first conductive vias. The second wiring layer is electrically connected to the first wiring layer via the plurality of second conductive vias. The plurality of upper contacts are electrically connected to the second wiring layer via the plurality of third conductive vias. The metal heat sink is disposed between the first wiring layer and the second wiring layer. A recess is disposed on one side of the substrate. A portion of the first wiring layer is exposed at the bottom of the recess. The voltage regulator is disposed in the recess and electrically connected to the first wiring layer. Each bump is electrically connected to its respective upper contact. Multiple chip contacts are provided on the active surface of the chip. Each chip contact is electrically connected to its respective bump. The location of the metal heat sink unit corresponds to the chip configuration.

[0005] In some embodiments, the projected area of ​​the wafer in the projection direction covers the projected area of ​​the metal heat dissipation unit in the projection direction.

[0006] In some embodiments, the metal heat dissipation unit is disposed directly below the chip.

[0007] In some embodiments, a semiconductor device includes a substrate, a first wafer, a second wafer, a plurality of first metal interconnects, a plurality of second metal interconnects, a metal heat sink, and a molding layer. The substrate has an upper surface and a lower surface. The substrate includes a plurality of lower contacts and a plurality of upper contacts. The plurality of lower contacts are disposed on the lower surface. The plurality of upper contacts are disposed on the upper surface. The plurality of upper contacts include a plurality of first contacts and a plurality of second contacts. The active surface of the first wafer faces the upper surface of the substrate. The second wafer is disposed on the back side of the first wafer. The active surface of the second wafer faces the upper surface of the substrate. The second wafer and the first wafer partially overlap in a projection direction. The active surface of the first wafer is electrically connected to the plurality of first contacts via the plurality of first metal interconnects. The active surface of the second wafer is electrically connected to the plurality of second contacts via the plurality of second metal interconnects. The metal heat sink covers the first wafer and the second wafer. The metal heat sink includes a horizontal portion and a side portion. The horizontal portion is in thermal contact with the back side of the second wafer. One side of the side portion is connected to one side of the horizontal portion, and the other side of the side portion is connected to the upper surface of the substrate. The molding layer encapsulates the first chip, the second chip, and the metal heat sink, while exposing the horizontal portion of the metal heat sink.

[0008] In some embodiments, the substrate further includes conductive vias. A plurality of lower contacts include ground contacts. The other side of the side portion is electrically connected to the ground contact via a conductive via.

[0009] In some embodiments, a semiconductor structure includes a first substrate, a plurality of bumps, a wafer, a second substrate, a first wafer, a second wafer, a plurality of first metal connection pillars, a plurality of second metal connection pillars, a metal heat sink, a molding layer, and a plurality of third metal connection pillars. The substrate has an upper surface and a lower surface. The first substrate includes a plurality of first lower contacts, a plurality of first upper contacts, a first wiring layer, a second wiring layer, a plurality of first conductive vias, a plurality of second conductive vias, a plurality of third conductive vias, a metal heat sink unit, a recess, and a voltage regulator. The plurality of first lower contacts are disposed on the lower surface of the first substrate. The plurality of first upper contacts are disposed on the upper surface of the first substrate. The plurality of first upper contacts include a plurality of bump contacts and a plurality of first connection pillar contacts. The first wiring layer is disposed between the upper surface and the lower surface of the first substrate. The second wiring layer is disposed between the upper surface and the lower surface of the first substrate and is located on the first wiring layer. The first wiring layer is electrically connected to the plurality of first lower contacts via a plurality of first conductive vias. The second wiring layer is electrically connected to the first wiring layer via a plurality of second conductive vias. Multiple bump contacts are electrically connected to the second trace layer via multiple third conductive vias. A metal heat sink is disposed between the first and second trace layers. A recess is disposed on one side of the first substrate. A portion of the first trace layer is exposed at the bottom of the recess. A voltage regulator is disposed in the recess and electrically connected to the first trace layer. Each bump is electrically connected to its respective bump contact. Multiple chip contacts are disposed on the active surface of the chip. Each chip contact is electrically connected to its respective bump. The second substrate has an upper surface and a lower surface. The second substrate includes multiple second lower contacts and multiple second upper contacts. Multiple second lower contacts are disposed on the lower surface of the second substrate. Multiple second upper contacts are disposed on the upper surface of the second substrate. Multiple second upper contacts include multiple first contacts and multiple second contacts. The active surface of the first chip faces the upper surface of the second substrate. The second chip is disposed on the back side of the first chip. The active surface of the second chip faces the upper surface of the second substrate. The second chip and the first chip partially overlap in the projection direction. The active surface of the first wafer is electrically connected to multiple first contacts via multiple first metal connection posts. The active surface of the second wafer is electrically connected to multiple second contacts via multiple second metal connection posts. A metal heat sink covers the first and second wafers. The metal heat sink includes a horizontal portion and a side portion. The horizontal portion is in thermal contact with the back surface of the second wafer. One side of the side portion is connected to one side of the horizontal portion, and the other side of the side portion is connected to the upper surface of the second substrate. A molding layer encapsulates the first wafer, the second wafer, and the metal heat sink, exposing the horizontal portion of the metal heat sink. The first connection post contacts are electrically connected to multiple second connection post contacts via multiple third metal connections. The positions of the metal heat sink units correspond to the wafer arrangement.

[0010] In some embodiments, the second substrate further includes conductive vias. The other side of the side portion is electrically connected to a grounding contact via the conductive vias.

[0011] In some embodiments, a method for manufacturing a semiconductor structure includes: providing a first substrate, the first substrate having an upper surface and a lower surface, the first substrate including a plurality of first upper contacts disposed on the upper surface of the first substrate, the plurality of first upper contacts including a plurality of bump contacts and a plurality of first connecting post contacts; providing a wafer, the active surface of the wafer being provided with a plurality of wafer contacts; forming a plurality of bumps on the plurality of wafer contacts, each wafer contact being connected to each bump; contacting the plurality of bumps with corresponding plurality of bump contacts; performing reflow soldering to solder each bump contact to each bump; providing a second substrate, the second substrate having an upper surface and a lower surface, the second substrate including a plurality of second upper contacts disposed on the upper surface of the second substrate and a plurality of second lower contacts disposed on the lower surface of the second substrate, the plurality of second upper contacts including a plurality of first contacts and a plurality of second contacts, the plurality of second lower contacts including a plurality of second connecting post contacts and a ground contact; providing a first wafer; providing a second wafer, the second wafer being disposed on the back side of the first wafer, and the second wafer partially overlapping the first wafer in the projection direction; forming The process involves: forming multiple first metal connectors on multiple first contacts and forming multiple second metal connectors on multiple second contacts; contacting the multiple first metal connectors with the active surface of a first wafer and contacting the multiple second metal connectors with the active surface of a second wafer; performing reflow soldering to solder the active surface of the first wafer to the multiple first metal connectors and the active surface of the second wafer to the multiple second metal connectors; forming a metal heat sink covering the first wafer and the second wafer, the metal heat sink including a horizontal portion and a side portion, the horizontal portion being in thermal contact with the back surface of the second wafer, one side of the side portion being connected to one side of the horizontal portion, and the other side of the side portion being connected to the upper surface of the second substrate; forming a molding layer encapsulating the first wafer, the second wafer, and the metal heat sink, and exposing the horizontal portion of the metal heat sink; forming multiple third metal connectors on the multiple second connector contacts; contacting the multiple third metal connectors with the multiple first connector contacts; and performing reflow soldering to solder the multiple first connector contacts to the multiple third metal connectors.

[0012] In some embodiments, the first substrate further includes a plurality of first lower contacts, a first wiring layer, a second wiring layer, a plurality of first conductive vias, a plurality of second conductive vias, a plurality of third conductive vias, a metal heat sink unit, a recess, and a voltage regulator. The plurality of first lower contacts are disposed on the lower surface of the first substrate. The first wiring layer is disposed between the upper surface and the lower surface of the first substrate. The second wiring layer is disposed between the upper surface and the lower surface of the first substrate and is located on the first wiring layer. The first wiring layer is electrically connected to the plurality of first lower contacts via the plurality of first conductive vias. The second wiring layer is electrically connected to the first wiring layer via the plurality of second conductive vias. The plurality of bump contacts are electrically connected to the second wiring layer via the plurality of third conductive vias. The metal heat sink unit is disposed between the first wiring layer and the second wiring layer. The recess is disposed on one side of the first substrate. A portion of the first wiring layer is exposed at the bottom of the recess. The voltage regulator is disposed in the recess and electrically connected to the first wiring layer. Each bump is electrically connected to its respective bump contact. The active surface of the chip has multiple chip contacts. Each chip contact is electrically connected to a bump. The location of the metal heat sink unit corresponds to the chip configuration.

[0013] The following detailed description of the features and advantages of this invention is sufficient to enable anyone skilled in the art to understand the technical content of this invention and implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the relevant purpose and advantages of this invention. Simple Explanation of the Diagram

[0014] Figure 1 is a cross-sectional schematic diagram of one embodiment of a semiconductor device. Figure 2 is a cross-sectional schematic diagram of one embodiment of another semiconductor device. Figure 3 is a cross-sectional schematic diagram of one embodiment of a semiconductor structure. Figures 4A and 4B are flowcharts of one embodiment of a semiconductor structure manufacturing method. Figures 5A to 5L are schematic diagrams of one embodiment of a semiconductor structure manufacturing method. Implementation

[0015] Figure 1 is a cross-sectional schematic diagram of one embodiment of a semiconductor device 10. Referring to Figure 1, the semiconductor device 10 includes a substrate 11, a plurality of bumps 12, and a wafer 13. The substrate 11 has an upper surface and a lower surface. The substrate 11 includes a plurality of lower contacts 111, a plurality of upper contacts 112, a first wiring layer 113, a second wiring layer 114, a plurality of first conductive vias 115, a plurality of second conductive vias 116, a plurality of third conductive vias 117, a metal heat sink unit 118, a recess 119, and a voltage regulator 120. The plurality of lower contacts 111 are disposed on the lower surface. The plurality of upper contacts 112 are disposed on the upper surface. The first wiring layer 113 is disposed between the upper surface and the lower surface. The second wiring layer 114 is disposed between the upper surface and the lower surface and is located on the first wiring layer 113. The first wiring layer 113 is electrically connected to the plurality of lower contacts 111 via the plurality of first conductive vias 115. The second wiring layer 114 is electrically connected to the first wiring layer 113 via a plurality of second conductive vias 116. A plurality of upper contacts 112 are electrically connected to the second wiring layer 114 via a plurality of third conductive vias 117. A metal heat sink unit 118 is disposed between the first wiring layer 113 and the second wiring layer 114. A recess 119 is disposed on one side of the substrate 11. A portion of the first wiring layer 113 is exposed at the bottom of the recess 119. A voltage regulator 120 is disposed in the recess 119 and electrically connected to the first wiring layer 113. Each bump 12 is electrically connected to each upper contact 112. A plurality of chip contacts 14 are disposed on the active surface of the chip 13. Each chip contact 14 is electrically connected to each bump 12.

[0016] In some embodiments, each upper contact 112 is directly soldered to each bump 12 in a vertical direction, but this embodiment is not limited to this. In some embodiments, the upper contact 112 may be, but is not limited to, a solder ball. In some embodiments, the lower contact 111 may be, but is not limited to, being electroplated on the lower surface of the substrate 11. In some embodiments, the upper contact 112 may be, but is not limited to, being electroplated on the upper surface of the substrate 11. In some embodiments, the material of the lower contact 111 and the upper contact 112 may be, but is not limited to, copper, aluminum, or tin. In some embodiments, each lower contact 111 is the same size. In some embodiments, each upper contact 112 is the same size.

[0017] In some embodiments, bump 12 may be, but is not limited to, a solder ball or a copper pillar. In some embodiments, each bump 12 may be electrically connected to each chip contact 14 by means of balling, solder paste printing, or electroplating. In some embodiments, each bump 12 may be eutectic bonded to each upper contact 112. In some embodiments, each bump 12 is the same size. In some embodiments, multiple bumps 12 are used to transmit high-speed signals, but this invention is not limited thereto, and multiple bumps 12 may also be used to transmit low-speed signals.

[0018] In some embodiments, the metal heat dissipation unit 118 may be, but is not limited to, a large bar via. In some embodiments, the material of the metal heat dissipation unit 118 may be, but is not limited to, copper. In some embodiments, the position of the metal heat dissipation unit 118 corresponds to the wafer 13. In some embodiments, the projected area of ​​the wafer 13 in the projection direction Z covers the projected area of ​​the metal heat dissipation unit 118 in the projection direction Z. In other words, in some embodiments, the projected area of ​​the metal heat dissipation unit 118 is completely within the projected area of ​​the wafer 13, or the two completely overlap. That is, from the projection direction Z, the wafer 13 is larger than or at least equal in size to the metal heat dissipation unit 118. In some embodiments, the metal heat dissipation unit 118 is disposed directly below the wafer 13.

[0019] In some embodiments, since the metal heat dissipation unit 118 is a large through-hole filled with copper or other highly thermally conductive material, the larger diameter of the metal heat dissipation unit 118 can provide higher thermal conductivity compared to ordinary through-holes. Therefore, in some embodiments, the substrate 11 has a highly efficient heat conduction path in the projection direction Z. The heat generated inside the substrate 11 and the wafer 13 can be quickly and effectively guided to the outer layer of the semiconductor device 10 through this heat conduction path, thereby improving the heat dissipation efficiency of the semiconductor device 10. That is, in some embodiments, through the provision of the metal heat dissipation unit 118, the semiconductor device 10 can avoid overheating, and the performance and stability of the wafer 13 will not be affected by heat accumulation.

[0020] In some embodiments, the first conductive via 115, the second conductive via 116, and the third conductive via 117 may be made of, but are not limited to, copper.

[0021] In some embodiments, the plurality of lower contacts 111 are electrically connected to a plurality of solder balls 15. In some embodiments, the plurality of lower contacts 111 are electrically connected to an external circuit (not shown) via the plurality of solder balls 15.

[0022] In some embodiments, the voltage regulator 120 is electrically connected to the first wiring layer 113 through a plurality of voltage regulator contacts 121. In some embodiments, the voltage regulator contacts 121 may be, but are not limited to, electroplated on the upper surface of the first wiring layer 113.

[0023] In some embodiments, since the recess 119 is disposed within the substrate 11 rather than outside the substrate 11, and the voltage regulator 120 is disposed within the recess 119, the voltage regulator 120 can be closer to the core components requiring stable power supply (such as the chip 13). The shorter power supply path reduces current transmission losses and impedance, thereby achieving a more stable voltage output. Furthermore, due to the shortened power supply path, power transmission losses are also reduced, resulting in a lower overall power consumption of the semiconductor device 10. In addition, the shorter power supply path also shortens signal transmission time, contributing to improved efficiency of the internal components of the semiconductor device 10. That is, in some embodiments, by providing the recess 119 within the substrate 11 and disposing of the voltage regulator 120 within the recess 119, the power supply path of the semiconductor device 10 is shortened, thereby improving the power output stability of the semiconductor device 10, and reducing the power consumption and latency of the semiconductor device 10, thus improving the performance of the semiconductor device 10.

[0024] Figure 2 is a cross-sectional schematic diagram of one embodiment of a semiconductor device 20. The semiconductor device 20 includes a substrate 21, a first wafer 22, a second wafer 23, a plurality of first metal connection pillars 24, a plurality of second metal connection pillars 25, a metal heat sink 26, and a molding layer 27. The substrate 21 has an upper surface and a lower surface. The substrate 21 includes a plurality of lower contacts 211 and a plurality of upper contacts 212. The plurality of lower contacts 211 are disposed on the lower surface. The plurality of upper contacts 212 are disposed on the upper surface. The plurality of upper contacts 212 include a plurality of first contacts 2121 and a plurality of second contacts 2122. The active surface of the first wafer 22 faces the upper surface of the substrate 21. The second wafer 23 is disposed on the back side of the first wafer 22. The active surface of the second wafer 23 faces the upper surface of the substrate 21. The second wafer 23 and the first wafer 22 partially overlap in the Z-direction of projection. The active surface of the first wafer 22 is electrically connected to the plurality of first contacts 2121 via the plurality of first metal connection pillars 24. The active surface of the second chip 23 is electrically connected to a plurality of second contacts 2122 via a plurality of second metal connecting posts 25. A metal heat sink 26 covers the first chip 22 and the second chip 23. The metal heat sink 26 includes a horizontal portion 261 and a side portion 262. The horizontal portion 261 is in thermal contact with the back surface of the second chip 23. One side of the side portion 262 is connected to one side of the horizontal portion 261, and the other side of the side portion 262 is connected to the upper surface of the substrate 21. A molding layer 27 encapsulates the first chip 22, the second chip 23, and the metal heat sink 26, and exposes the horizontal portion 261 of the metal heat sink 26.

[0025] In some embodiments, the lower contact 211 may be, but is not limited to, electroplated onto the lower surface of the substrate 11. In some embodiments, the upper contact 212 may be, but is not limited to, electroplated onto the upper surface of the substrate 21. In some embodiments, the materials of the lower contact 211 and the upper contact 212 may be, but are not limited to, copper, aluminum, or tin. In some embodiments, the size of each lower contact 211 is the same. In some embodiments, the size of each upper contact 212 is the same.

[0026] In some embodiments, the active surface of the first chip 22 is provided with a plurality of first chip contacts, and the active surface of the first chip 22 is electrically connected to a plurality of first metal connection posts 24 through the plurality of first chip contacts, so as to be electrically connected to a plurality of first contacts 2121 via the plurality of first metal connection posts 24. In some embodiments, the active surface of the second chip 23 is provided with a plurality of second chip contacts, and the active surface of the second chip 23 is electrically connected to a plurality of second metal connection posts 25 through the plurality of second chip contacts, so as to be electrically connected to a plurality of second contacts 2122 via the plurality of second metal connection posts 25. In some embodiments, solder paste is coated on the active surface of the first chip 22, and the active surface of the first chip 22 is electrically connected to a plurality of first metal connection posts 24 through the solder paste coated thereon, so as to be electrically connected to a plurality of first contacts 2121 via the plurality of first metal connection posts 24. In some embodiments, solder paste is applied to the active surface of the second chip 23, and the active surface of the second chip 23 is electrically connected to a plurality of second metal connection posts 25 through the solder paste applied thereon, so as to be electrically connected to a plurality of second contacts 2122 via the plurality of second metal connection posts 25.

[0027] In some embodiments, the second chip 23 is disposed on the back side of the first chip 22 in a thermally contact manner. In some embodiments, the second chip 23 is disposed on the back side of the first chip 22 in direct contact with the first chip 22. In some embodiments, a highly thermally conductive adhesive layer is provided between the second chip 23 and the first chip 22. The second chip 23 is disposed on the back side of the first chip 22 via the highly thermally conductive adhesive layer disposed between the second chip 23 and the first chip 22.

[0028] In some embodiments, the horizontal portion 261 directly contacts the back surface of the second wafer 23. In some embodiments, a highly thermally conductive adhesive layer is provided between the horizontal portion 261 and the back surface of the second wafer 23. The second wafer 23 is attached to the back surface of the second wafer 23 via the highly thermally conductive adhesive layer disposed between the horizontal portion 261 and the back surface of the second wafer 23.

[0029] In some embodiments, the molding layer 27 includes a polishing process during its formation. In some embodiments, the material of the molding layer 27 above the horizontal portion 261 of the metal heat sink 26 has been removed during the polishing process, thereby exposing the horizontal portion 261 of the metal heat sink 26 after the molding layer 27 is completed.

[0030] In some embodiments, the first metal connecting post 24 and the second metal connecting post 25 may be made of, but are not limited to, copper, gold, or a mixture of metals. In some embodiments, the height of the first metal connecting post 24 may be dynamically adjusted according to the desired distance between the first wafer 22 and the substrate 21. In some embodiments, the height of the second metal connecting post 25 may be dynamically adjusted according to the desired distance between the second wafer 23 and the substrate 21. In some embodiments, the width of each first metal connecting post 24 may be dynamically adjusted according to user needs, and the widths of each first metal connecting post 24 may be different. In some embodiments, the width of each second metal connecting post 25 may be dynamically adjusted according to user needs, and the widths of each second metal connecting post 25 may be different.

[0031] In some embodiments, due to the material properties of the first metal connector 24 and the second metal connector 25, they provide higher conductivity than conventional wire bonding, effectively reducing power loss. Furthermore, the first metal connector 24 and the second metal connector 25 have excellent thermal conductivity, rapidly dissipating the heat generated during the operation of the first wafer 22 and the second wafer 23, helping to prevent performance degradation or damage to the first wafer 22 and the second wafer 23 due to overheating. In addition, the first metal connector 24 and the second metal connector 25 can directly connect different components, resulting in a shorter electrical path compared to conventional wire bonding, thereby significantly reducing resistance and signal delay, and improving the semiconductor device 20's ability to support high-speed signals. That is, in some embodiments, through the arrangement of the first metal connector 24 and the second metal connector 25, the semiconductor device 20 can support high-speed signals, and the heat dissipation capacity of the semiconductor device 20 is also significantly improved.

[0032] In some embodiments, the metal heat sink 26 may be made of, but is not limited to, copper, gold, or a mixture of metals.

[0033] In some embodiments, since the horizontal portion 261 of the metal heat sink 26 is in thermal contact with the back surface of the second chip 23, and the horizontal portion 261 of the metal heat sink 26 is exposed, the metal heat sink 26 can quickly absorb the heat generated by the first chip 22 and the second chip 23 during operation and quickly transfer the heat to the outside through its exposed horizontal portion 261, preventing the performance degradation or damage of the first chip 22 and the second chip 23 due to overheating. Furthermore, since the metal heat sink 26 is made of conductive metal, it can be considered a metal shield for the first chip 22 and the second chip 23, thus providing electromagnetic shielding for them and effectively shielding against electromagnetic interference between them, reducing signal noise between them. That is, in some embodiments, the heat dissipation capacity of the semiconductor device 20 is significantly improved through the provision of the metal heat sink 26, and the metal heat sink 26 can also provide electromagnetic interference (EMI) shielding for the first chip 22 and the second chip 23.

[0034] In some embodiments, the substrate 21 further includes a conductive via 213, and the plurality of lower contacts 211 further include a ground contact 2111. In some embodiments, the other side of the side portion 262 is electrically connected to the ground contact 2111 via the conductive via 213.

[0035] Figure 3 is a cross-sectional schematic diagram of one embodiment of semiconductor structure 1. Semiconductor structure 1 is a two-layer package structure, the upper package structure being the semiconductor device 20 shown in Figure 2, and the lower package structure being the semiconductor device 10 shown in Figure 1. Semiconductor structure 1 includes semiconductor device 10, semiconductor device 20, and a plurality of third metal connecting pillars 30.

[0036] In some embodiments, the plurality of upper contacts 112 include a plurality of bump contacts 1121 and a plurality of first connecting post contacts 1122. The plurality of bump contacts 1121 are electrically connected to the second trace layer 114 via a plurality of third conductive vias 117, and each bump 12 is connected to each bump contact 1121. In some embodiments, the plurality of lower contacts 211 include a plurality of second connecting post contacts 2112 and a ground contact 2111. In some embodiments, the plurality of first connecting post contacts 1122 are electrically connected to the plurality of second connecting post contacts 2112 via a plurality of third metal connecting posts 30.

[0037] In some embodiments, the material of the third metal connecting post 30 may be, but is not limited to, copper, gold, or a mixture of metals. In some embodiments, the height of the third metal connecting post 30 may be dynamically adjusted according to the desired distance between the semiconductor device 10 and the semiconductor device 20. In some embodiments, the width of each third metal connecting post 30 may be dynamically adjusted according to user needs, and the widths of each third metal connecting post 30 may be different.

[0038] In some embodiments, the semiconductor structure 1 further includes an adhesive layer 40. In some embodiments, the back side of the wafer 13 is bonded to the substrate 21 via the adhesive layer 40.

[0039] Figures 4A and 4B are flowcharts of one embodiment of the manufacturing method of semiconductor structure 1. Figures 5A to 5L are schematic diagrams of one embodiment of the manufacturing method of semiconductor structure 1. Please refer to Figures 4A to 4B and Figures 5A to 5L.

[0040] First, a substrate 11 is provided (step S01). The substrate 11 has an upper surface and a lower surface. The substrate 11 includes a plurality of first upper contacts 112 disposed on the upper surface of the substrate 11. The plurality of first upper contacts 112 include a plurality of bump contacts 1121 and a plurality of first connecting post contacts 1122 (as shown in FIG. 5A). Next, a wafer 13 is provided (step S02). A plurality of wafer contacts 14 are disposed on the active surface of the wafer 13 (as shown in FIG. 5B). Next, a plurality of bumps 12 are formed on the plurality of wafer contacts 14 (step S03). Each wafer contact 14 is connected to each bump 12 (as shown in FIG. 5C). Next, the plurality of bumps 12 are brought into contact with the corresponding plurality of bump contacts 1121 (step S04). Next, reflow soldering is performed to solder each bump contact 1121 to each bump 12 (step S05) (as shown in FIG. 5D). Steps S01 to S05 complete the lower packaging structure of semiconductor structure 1 (i.e., semiconductor device 10).

[0041] Next, substrate 21 is provided (step S06). Substrate 21 has an upper surface and a lower surface. Substrate 21 includes a plurality of second upper contacts 212 disposed on the upper surface of substrate 21 and a plurality of second lower contacts 211 disposed on the lower surface of substrate 21. The plurality of second upper contacts 212 include a plurality of first contacts 2121 and a plurality of second contacts 2122. The plurality of second lower contacts 211 include a plurality of second connecting post contacts 2112 and a ground contact 2111 (as shown in FIG5E). Next, first wafer 22 is provided (step S07). Next, second wafer 23 is provided (step S08). Second wafer 23 is disposed on the back side of first wafer 22, and second wafer 23 and first wafer 22 partially overlap in the projection direction Z (as shown in FIG5F). Next, a plurality of first metal connecting posts 24 are formed on the plurality of first contacts 2121 and a plurality of second metal connecting posts 25 are formed on the plurality of second contacts 2122 (step S09) (as shown in FIG5G). Next, multiple first metal connection posts 24 are brought into contact with the active surface of the first wafer 22, and multiple second metal connection posts 25 are brought into contact with the active surface of the second wafer 23 (step S10). Next, reflow soldering is performed, so that the active surface of the first wafer 22 is soldered to the multiple first metal connection posts 24, and the active surface of the second wafer 23 is soldered to the multiple second metal connection posts 25 (step S11) (as shown in FIG. 5H). Next, a metal heat sink 26 is formed (step S12). The metal heat sink 26 covers the first wafer 22 and the second wafer 23. The metal heat sink 26 includes a horizontal portion 261 and a side portion 262. The horizontal portion 261 is in thermal contact with the back surface of the second wafer 23, one side of the side portion 262 is connected to one side of the horizontal portion 261, and the other side of the side portion 262 is connected to the upper surface of the substrate 21 (as shown in FIG. 5I). Next, a molding layer 27 is formed (step S13). The molding layer 27 encapsulates the first wafer 22, the second wafer 23, and the metal heat sink 26, exposing the horizontal portion 261 of the metal heat sink 26 (as shown in Figure 5J). Steps S06 to S13 complete the upper packaging structure of the semiconductor structure 1 (i.e., the semiconductor device 20).

[0042] Next, a plurality of third metal connection pillars 30 are formed on a plurality of second connection pillar contacts 2112 (step S14) (as shown in Figure 5K). Next, the plurality of third metal connection pillars 30 are brought into contact with a plurality of first connection pillar contacts 1122 (step S15). Finally, reflow soldering is performed to solder the plurality of first connection pillar contacts 1122 to the plurality of third metal connection pillars 30 (step S16) (as shown in Figure 5L). Steps S14 to S16 complete the electrical connection between the upper packaging structure and the lower packaging structure of the semiconductor structure 1.

[0043] In some embodiments, in step S09, the method of forming a plurality of first metal connecting posts 24 on a plurality of first contacts 2121 and forming a plurality of second metal connecting posts 25 on a plurality of second contacts 2122 is to deposit metal on the plurality of first contacts 2121 and deposit metal on the plurality of second contacts 2122. In some embodiments, the first metal connecting posts 24 and the second metal connecting posts 25 are pre-formed metal posts. In some embodiments, in step S09, the method of forming a plurality of first metal connecting posts 24 on a plurality of first contacts 2121 and forming a plurality of second metal connecting posts 25 on a plurality of second contacts 2122 is to directly place the pre-formed plurality of first metal connecting posts 24 on a plurality of first contacts 2121 and directly place the pre-formed plurality of second metal connecting posts 25 on a plurality of second contacts 2122.

[0044] In some embodiments, in step S14, the method of forming a plurality of third metal connecting posts 30 on a plurality of second connecting post contacts 2112 is to deposit metal on the plurality of second connecting post contacts 2112. In some embodiments, the third metal connecting posts 30 are pre-formed metal posts. In some embodiments, in step S14, the method of forming a plurality of third metal connecting posts 30 on a plurality of second connecting post contacts 2112 is to directly place the pre-formed plurality of third metal connecting posts 30 on the plurality of second connecting post contacts 2112.

[0045] In the embodiments shown in Figures 4A and 4B, a plurality of first metal connection posts 24 are first formed on a plurality of first contacts 2121 and then soldered to the active surface of the first wafer 22, but this invention is not limited thereto. In some embodiments, a plurality of first metal connection posts 24 are first formed on the active surface of the first wafer 22 and then soldered to a plurality of first contacts 2121.

[0046] In the embodiments shown in Figures 4A and 4B, a plurality of second metal connection posts 25 are first formed on a plurality of second contacts 2122 and then soldered to the active surface of the second wafer 23, but this invention is not limited thereto. In some embodiments, a plurality of second metal connection posts 25 are first formed on the active surface of the second wafer 23 and then soldered to a plurality of second contacts 2122.

[0047] In the embodiments shown in Figures 4A and 4B, the plurality of third metal connecting posts 30 are first formed on the plurality of second connecting post contacts 2112 and then welded to the plurality of first connecting post contacts 1122, but this invention is not limited thereto. In some embodiments, the plurality of first metal connecting posts 24 are first formed on the plurality of first connecting post contacts 1122 and then welded to the plurality of second connecting post contacts 2112.

[0048] In some embodiments, the method of manufacturing the semiconductor structure 1 further includes forming a conductive via 213 on the substrate 21. In some embodiments, the other side of the side portion 262 of the metal heat sink 26 is electrically connected to the grounding contact 2111 via the conductive via 213.

[0049] In some embodiments, the method of manufacturing the semiconductor structure 1 further includes forming an adhesive layer 40. In some embodiments, the back side of the wafer 13 is bonded to the substrate 21 via the adhesive layer 40.

[0050] In summary, in some embodiments, the lower packaging structure (i.e., semiconductor device 10) of semiconductor structure 1 can avoid overheating through the provision of metal heat dissipation unit 118, and the performance and stability of chip 13 will not be affected by heat accumulation. In some embodiments, by providing a groove 119 in the substrate 11 and placing the voltage regulator 120 in the groove 119, the power supply path of semiconductor device 10 is shortened, thereby improving the power output stability of semiconductor device 10, and reducing the power consumption and latency of semiconductor device 10, thereby improving the performance of semiconductor device 10. In some embodiments, through the provision of first metal connecting post 24 and second metal connecting post 25, the upper packaging structure (i.e., semiconductor device 20) of semiconductor structure 1 can support high-speed signals, and the heat dissipation capacity of semiconductor device 20 is also significantly improved. In some embodiments, through the provision of metal heat sink 26, the heat dissipation capacity of semiconductor device 20 is significantly improved, and metal heat sink 26 can also provide electromagnetic interference shielding for first chip 22 and second chip 23.

[0051] Although the technical content of this case has been disclosed above with reference to preferred embodiments, it is not intended to limit this case. Any modifications and refinements made by those skilled in the art without departing from the spirit of this case should be included within the scope of this case. Therefore, the scope of protection of this case shall be determined by the appended claims.

[0052] 10: Semiconductor devices 11:Substrate 12: Bumps 13: Chip 14: Chip Contact 15: Tin Ball 111: Next node 112: Upper connection point 1121: Bump contact 1122: First connecting post joint 113: First wiring layer 114: Second wiring layer 115: First conductive via 116: Second conductive via 117: Third conductive via 118: Metal heat dissipation unit 119: Groove 120: Voltage regulator 121: Voltage regulator contact 20: Semiconductor devices 21:Substrate 22: First chip 23: Second chip 24: First metal connecting post 25: Second metal connecting post 26: Metal heat sink 27: Mold sealing layer 211: Next node 212: Upper connection point 2111: Grounding contact 2112: Second connecting post joint 2121: First Node 2122: Second Node 213: Conductive via 261: Horizontal section 262: Side section 1: Semiconductor Structure 30: Third metal connecting post 40: Adhesive layer S01~S16: Steps X, Y, Z: Projection direction

Claims

1. A semiconductor device comprising: a substrate having an upper surface and a lower surface, the substrate comprising: a plurality of lower contacts disposed on the lower surface; a plurality of upper contacts disposed on the upper surface; a first wiring layer disposed between the upper surface and the lower surface; a second wiring layer disposed between the upper surface and the lower surface and located on the first wiring layer; a plurality of first conductive vias, the first wiring layer being electrically connected to the lower contacts via the first conductive vias; a plurality of second conductive vias, the second wiring layer being electrically connected to the first wiring layer via the second conductive vias; a plurality of third conductive vias, the upper contacts being electrically connected to the second wiring layer via the third conductive vias; and a metal heat sink unit disposed between the first wiring layer and the second wiring layer. A groove is disposed on one side of the substrate, with a portion of the first wiring layer exposed at the bottom of the groove; a voltage regulator is disposed in the groove and electrically connected to the first wiring layer; a plurality of bumps are electrically connected to each of the upper contacts; and a chip has a plurality of chip contacts on its active surface, each of the chip contacts being electrically connected to each of the bumps; wherein the position of the metal heat sink unit corresponds to the chip.

2. The semiconductor device as claimed in claim 1, wherein the projected area of ​​the wafer in a projection direction covers the projected area of ​​the metal heat sink in a projection direction.

3. The semiconductor device as claimed in claim 2, wherein the metal heat sink is disposed directly below the wafer.

4. A semiconductor device comprising: a substrate having an upper surface and a lower surface, the substrate including: a plurality of lower contacts disposed on the lower surface; and a plurality of upper contacts disposed on the upper surface, the upper contacts including a plurality of first contacts and a plurality of second contacts; a first wafer having an active surface facing the upper surface of the substrate; a second wafer disposed on the back side of the first wafer, the active surface of the second wafer facing the upper surface of the substrate, wherein the second wafer and the first wafer partially overlap in a projection direction; a plurality of first metal connection pillars, the active surface of the first wafer being electrically connected to the first contacts via the first metal connection pillars; and a plurality of second metal connection pillars, the active surface of the second wafer being electrically connected to the second contacts via the second metal connection pillars. A metal heat sink covers the first chip and the second chip, including a horizontal portion and a side portion. The horizontal portion is in thermal contact with the back of the second chip. One side of the side portion is connected to one side of the horizontal portion, and the other side of the side portion is connected to the upper surface of the substrate. A molding layer encapsulates the first chip, the second chip and the metal heat sink, and exposes the horizontal portion of the metal heat sink.

5. The semiconductor device of claim 4, wherein the substrate further includes a conductive via, the lower contacts include a ground contact, and the other side of the side portion is electrically connected to the ground contact via the conductive via.

6. A semiconductor structure comprising: a first substrate having an upper surface and a lower surface, the first substrate comprising: a plurality of first lower contacts disposed on the lower surface of the first substrate; a plurality of first upper contacts disposed on the upper surface of the first substrate, the first upper contacts comprising a plurality of bump contacts and a plurality of first connecting post contacts; a first wiring layer disposed between the upper surface of the first substrate and the lower surface of the first substrate; a second wiring layer disposed between the upper surface of the first substrate and the lower surface of the first substrate and located on the first wiring layer; a plurality of first conductive vias, the first wiring layer being electrically connected to the first lower contacts via the first conductive vias; a plurality of second conductive vias, the second wiring layer being electrically connected to the first wiring layer via the second conductive vias; a plurality of third conductive vias, the bump contacts being electrically connected to the second wiring layer via the third conductive vias; and a metal heat sink unit disposed between the first wiring layer and the second wiring layer. A groove is disposed on one side of the first substrate, with a portion of the first wiring layer exposed at the bottom of the groove; and a voltage regulator is disposed in the groove and electrically connected to the first wiring layer; a plurality of bumps are connected to a plurality of bump contacts; a chip has a plurality of chip contacts on its active surface, each chip contact being connected to a respective bump; a second substrate has an upper surface and a lower surface, the second substrate comprising: a plurality of second lower contacts disposed on the lower surface of the second substrate, the second lower contacts including a plurality of second connecting post contacts and a ground contact; and a plurality of second upper contacts disposed on the upper surface of the second substrate, the second upper contacts including a plurality of first contacts and a plurality of second contacts; a first chip with its active surface facing the upper surface of the second substrate; and a second chip disposed on the back side of the first chip, with its active surface facing the upper surface of the second substrate, wherein the second chip and the first chip partially overlap in a projection direction; A plurality of first metal connection pillars, wherein the active surface of the first wafer is electrically connected to the first contacts via the first metal connection pillars; a plurality of second metal connection pillars, wherein the active surface of the second wafer is electrically connected to the second contacts via the second metal connection pillars; a metal heat sink covering the first wafer and the second wafer, comprising a horizontal portion and a side portion, the horizontal portion being in thermal contact with the back surface of the second wafer, one side of the side portion being connected to one side of the horizontal portion, and the other side of the side portion being connected to the upper surface of the second substrate; a molding layer encapsulating the first wafer, the second wafer, and the metal heat sink, and exposing the horizontal portion of the metal heat sink; and a plurality of third metal connection pillars, wherein the contacts of the first connection pillars are electrically connected to the contacts of the second connection pillars via the third metal connection pillars; wherein the metal heat dissipation unit is disposed corresponding to the wafer.

7. The semiconductor structure as claimed in claim 6, wherein the projected area of ​​the wafer in the projection direction covers the projected area of ​​the metal heat sink in the projection direction.

8. The semiconductor structure as claimed in claim 6, wherein the metal heat dissipation unit is disposed directly below the wafer.

9. The semiconductor structure as claimed in claim 6, wherein the second substrate further includes a conductive via, and the other side of the side portion is electrically connected to the grounding contact via the conductive via.

10. A method for manufacturing a semiconductor structure, comprising: providing a first substrate having an upper surface and a lower surface, the first substrate including a plurality of first upper contacts disposed on the upper surface of the first substrate, the first upper contacts including a plurality of bump contacts and a plurality of first connecting post contacts; providing a wafer having a plurality of wafer contacts disposed on an active surface; forming a plurality of bumps on the wafer contacts, each wafer contact being connected to each of the bumps; contacting the bumps with corresponding bump contacts; performing reflow soldering to solder each bump contact to each of the bumps; providing a second substrate having an upper surface and a lower surface, the second substrate including a plurality of second upper contacts disposed on the upper surface of the second substrate and a plurality of second lower contacts disposed on the lower surface of the second substrate, the second upper contacts including a plurality of first contacts and a plurality of second contacts, the second lower contacts including a plurality of second connecting post contacts and a ground contact; and providing a first wafer; A second wafer is provided, disposed on the back side of the first wafer, and the second wafer partially overlaps the first wafer in a projection direction; a plurality of first metal connection pillars are formed on the first contacts and a plurality of second metal connection pillars are formed on the second contacts; the first metal connection pillars are contacted with the active surface of the first wafer and the second metal connection pillars are contacted with the active surface of the second wafer; reflow soldering is performed to solder the active surface of the first wafer to the first metal connection pillars and the active surface of the second wafer to the second metal connection pillars; a metal heat sink is formed, covering the first wafer and the second wafer, the metal heat sink including a horizontal portion and a side portion, the horizontal portion being in thermal contact with the back side of the second wafer, one side of the side portion being connected to one side of the horizontal portion, and the other side of the side portion being connected to the upper surface of the second substrate; a molding layer is formed, the molding layer encapsulating the first wafer, the second wafer and the metal heat sink, and exposing the horizontal portion of the metal heat sink; Form multiple third metal connecting posts on the second connecting post joints; contact the third metal connecting posts with the first connecting post joints; and perform reflow soldering to weld the first connecting post joints to the third metal connecting posts.

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