Semiconductor device
Patent Information
- Application Number
- TW114128877
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2025-03-17
- Filing Date
- 2025-07-30
- Publication Date
- 2026-09-11
- Estimated Expiration
- 2045-07-29
Smart Images

Figure TWG2TB001910701_001 
Figure TWG2TB001910701_002 
Figure TWG2TB001910701_003
Abstract
Claims
1. A semiconductor element, comprising: A substrate having multiple doped regions; Two-dimensional linear structures are formed on the substrate, extending along a first direction and separated from each other; Two separating layers are disposed on the substrate, extend along a second direction perpendicular to the first direction, are separated from each other along the first direction, and simultaneously contact the two-dimensional line structure; And a unit contact structure, disposed on the substrate, including: a bottom contact layer, disposed on the substrate and closed through the two-element line structure and the two separation layers; A liner is disposed between the substrate and the bottom contact layer, between the two-bit wire structure and the bottom contact layer, and between the two separator layers and the bottom contact layer; and a top contact layer is disposed on the liner and the bottom contact layer, wherein the two-bit wire structure includes an air gap disposed therebetween, wherein the plurality of doped regions are formed of silicon phosphide, phosphorus-doped silicon-carbon, silicon carbide, silicon-germanium, silicon-germanium-tin alloy or silicon-germanium-boron alloy.
2. The semiconductor device as claimed in claim 1, wherein the bottom contact layer comprises tungsten, titanium, or titanium nitride.
3. The semiconductor device as claimed in claim 2, wherein the top contact layer includes a material, wherein the material of the top contact layer is the same as a material of the bottom contact layer.
4. The semiconductor device as claimed in claim 2, wherein a top surface of the top contact layer is lower than the top surface of the plurality of bit line structures.
5. The semiconductor device as claimed in claim 4, wherein the substrate comprises an n-type dopant or a p-type dopant.
6. The semiconductor device as claimed in claim 4, wherein the substrate comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium.
7. The semiconductor device as claimed in claim 4, wherein, viewed from a top perspective view, the bottom contact layer includes a rectangular cross-sectional profile or a square cross-sectional profile.
8. The semiconductor element as claimed in claim 1 further includes a plurality of spacer structures disposed between the cell contact structure and the two-cell line structure.
9. The semiconductor device as claimed in claim 8, wherein the plurality of spacer structures each includes an inner spacer layer disposed between one of the two bit line structures and the cell contact structure, an intermediate spacer layer disposed between the inner spacer layer and the cell contact structure, and an outer spacer layer disposed between the intermediate spacer layer and the cell contact structure.
Citation Information
Patent Citations
Contact structure, semiconductor device with the same, and method for fabricating the same
TW202533411A
Magnetic memory and memory cell thereof and method of manufacturing the memory cell
US20080278995A1