Data decoding device and memory system

Abstract

This invention provides a data decoding apparatus capable of increasing processing capacity. According to an embodiment, the data decoding apparatus includes a first memory unit, a second memory unit, a decoding unit, a first selection unit, and a second selection unit. The first memory unit stores a data stream comprising one or more first blocks, each of which includes a first-type data unit and a second-type data unit. The second memory unit stores second-type data units. The decoding unit decodes the second-type data units. The first selection unit switches the transmission destination for transmitting second-type data units from the first memory unit. The second selection unit switches the transmission source for transmitting second-type data units to the decoding unit. When a second block within one or more first blocks is the final block in the data stream, the first selection unit transmits the second-type second data units included in the second block from the first memory unit to the second memory unit, and the second selection unit transmits the second data units stored in the second memory unit to the decoding unit.

Description

Technical Field

[0001] The embodiments of the present invention relate to a technique for decoding data. Prior Technology

[0002] Entropy coding is a variable-length coding method that generates a coding table based on the frequency of occurrence of each symbol in the symbol row of the object to be coded. The coding table represents the correspondence between symbols and the codewords assigned to those symbols. In entropy coding, symbols with high occurrence frequency are assigned short codewords, and symbols with low occurrence frequency are assigned long codewords. Therefore, each symbol of the object to be coded can be converted into a variable-length code using the coding table.

[0003] The compressed data (compressed stream) obtained through entropy coding comprises one or more compression units (CUs). Each CU comprises one or more blocks. Each block comprises a header and a payload. The header contains data for reconstructing the encoding table. The payload comprises one or more variable-length codes. Each variable-length code is decoded using the reconstructed encoding table. Therefore, for each block, the variable-length code is decoded using the reconstructed encoding table, thereby expanding the compressed data. Summary of the Invention

[0004] In one embodiment of the present invention, the objective is to provide a data decoding device and a memory system capable of increasing the processing capacity of data decoding.

[0005] According to an embodiment, the data decoding apparatus includes a first memory unit, a first decoding unit, a second memory unit, a second decoding unit, a first selection unit, and a second selection unit. The first memory unit stores a first data stream comprising one or more first blocks, each of which includes a first-type data section and a second-type data section. The first decoding unit decodes the first-type data section. The second memory unit stores second-type data sections. The second decoding unit decodes the second-type data sections. The first selection unit switches the transmission destination from the first memory unit to transmit the second-type data section. The second selection unit switches the transmission source to transmit the second-type data section to the second decoding unit. When the second block within one or more first blocks is the final block in the first data stream, the first selection unit transmits the second-type second data section of the second block from the first memory unit to the second memory unit, and the second selection unit transmits the second data section stored in the second memory unit to the second decoding unit. Simple Explanation of the Diagram

[0006] Figure 1 is a block diagram showing a structural example of an information processing system including a data decoding device according to an embodiment. Figure 2 is a diagram showing an example of the data structure of the compressed stream input to the data decoding device of the embodiment, and the final signal. Figure 3 is a block diagram showing the structure of the data decoding device of the comparative example. Figure 4 is a timing diagram showing the execution time of header decoding and payload decoding in the data decoding device of the comparative example. Figure 5 is a block diagram showing a structural example of the data decoding device according to the embodiment. Figure 6 is a flowchart illustrating an example of the sequence of the first processes performed in the data decoding apparatus of the embodiment. Figure 7 is a flowchart illustrating an example of the sequence of the second processing performed in the data decoding apparatus of the embodiment. Figure 8 is a flowchart illustrating an example of the sequence of the third processing performed in the data decoding apparatus of the embodiment. Figure 9 is a timing diagram showing an example of the execution time of header decoding processing and payload decoding processing in the data decoding apparatus of the embodiment. Implementation

[0007] The embodiments will now be described with reference to the drawings.

[0008] Figure 1 shows a structural example of an information processing system including the data decoding device of the embodiment. The information processing system 1 includes a host device 2 and a memory system 3.

[0009] Host device 2 is an information processing device that stores data in memory system 3. Host device 2 is, for example, a storage server or a personal computer that stores large amounts and various types of data in memory system 3. Hereinafter, host device 2 will be referred to as host 2.

[0010] Memory system 3 is a semiconductor storage device configured to write data to and read data from non-volatile memory. The non-volatile memory is, for example, a Not-And-NAND flash memory 4. Memory system 3 is implemented, for example, in the form of a solid-state drive (SSD). Hereinafter, an example of memory system 3 implemented as an SSD including NAND flash memory 4 will be given. Furthermore, memory system 3 can also be implemented as other types of storage devices such as hard disk drives (HDDs).

[0011] The memory system 3 can be used as storage for the host 2. The memory system 3 can be built into the host 2 or connected to the host 2 via cable or network.

[0012] The interface used to connect host 2 and memory system 3 conforms to standards such as Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Advanced Technology Attachment (ATA), Serial ATA (SATA), Peripheral Component Interconnect (PCIe™), Ethernet™, Fibre Channel, and Node Version Manager (NVM) Express™ (NVMe™).

[0013] The memory system 3 includes, for example, NAND flash memory 4, dynamic random access memory (DRAM) 5, and a controller 6.

[0014] NAND flash memory 4 includes one or more memory chips. Each memory chip includes multiple blocks. These blocks function as the smallest unit for data erasure operations. A block is also called an erase block or a physical block. Each block includes multiple pages. Each page includes multiple memory cells connected to a single word line. Each page functions as a unit for data write and data read operations. Furthermore, the word line also functions as a unit for data write and data read operations.

[0015] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, which is called the maximum number of P / E cycles. A single P / E cycle for a block includes an erase operation to erase all memory cells in the block and a write operation to write data to the pages of the block.

[0016] DRAM 5 is volatile memory. The memory areas of DRAM 5 are allocated for purposes such as firmware (FW) storage, caching of logical-physical address translation tables, and buffering of user data. User data is data sent from host 2 to memory system 3 upon request. User data stored in the buffer includes, for example, user data to be written to NAND flash memory 4 and user data read from NAND flash memory 4. User data to be written to NAND flash memory 4 can be written to NAND flash memory 4 after compression. Furthermore, user data read from NAND flash memory 4 is compressed user data and is expandable.

[0017] The interface used to connect DRAM 5 to external elements (such as data decoding device 15) conforms to the Advanced eXtensible Interface 4-Stream (AXI4-Stream) standard. In an AXI4-Stream interface, signals are used to control the start of data transmission (VALID and READY signals), signals to transmit data (DATA signals), and signals indicating the last data transmission (LAST signals). Signal lines are configured for these signals.

[0018] Controller 6 is a memory controller that controls NAND flash memory 4 and DRAM 5. Controller 6 is implemented, for example, by circuitry such as that of a System-on-a-chip (SoC).

[0019] The controller 6 functions, for example, as a flash memory translation layer (FTL) configured to perform data management and block management of the NAND flash memory 4. The data management performed by this FTL includes: (1) managing mapping information representing the correspondence between logical addresses and physical addresses of the NAND flash memory 4; and (2) handling the differences between data read / write operations of page units and data erase operations of block units. Block management includes the management of bad blocks, wear-leveling, and garbage collection.

[0020] Logical addresses are used by host 2 to assign addresses to memory regions in memory system 3. A logical address is, for example, a logical block address (LBA).

[0021] The management of the mapping between logical addresses and physical addresses is performed, for example, using a logical-physical address translation table (LPTD). The controller 6 uses the LPTD to manage the mapping information between logical addresses and physical addresses in specific management units. The physical address corresponding to a given logical address represents the physical memory location within the NAND flash memory 4 where user data for that logical address is written. The LPTD can be downloaded from the NAND flash memory 4 to the DRAM 5 during memory system 3 startup.

[0022] Data writing to a page can only be performed once per P / E cycle. Therefore, controller 6 writes the updated user data corresponding to a certain logical address to another physical memory location instead of the physical memory location that stores the previous user data corresponding to that logical address. Then, controller 6 updates the logical physical address translation table by associating the logical address with that other physical memory location, thereby invalidating the previous user data.

[0023] The controller 6 includes, for example, a central processing unit (CPU) 11, a NAND interface (NAND I / F) 12, a DRAM interface (DRAM I / F) 13, a host interface (host I / F) 14, and a data decoding device 15. These components, such as the CPU 11, NAND I / F 12, DRAM I / F 13, host I / F 14, and data decoding device 15, are connected, for example, via a bus 10.

[0024] Furthermore, the controller 6 can have built-in static random access memory (SRAM) or DRAM. In this case, the external DRAM 5 of the controller 6 is not required.

[0025] SRAM is a volatile memory. The memory area of ​​SRAM can be allocated as at least one of the following: storage area for FW, cache area for logical-physical address translation table, and buffer area for user data.

[0026] CPU 11 is a processor configured to control NAND I / F 12, DRAM I / F 13, host I / F 14, and data decoding device 15. CPU 11 performs various processes by executing a file system (FW) downloaded from NAND flash memory 4 to DRAM 5. The FW is a control program that includes a set of commands used to instruct CPU 11 to perform various processes. In addition to executing the FTL (File Transfer Language) processing described above, CPU 11 performs instruction processing to handle various instructions from host 2. The operation of CPU 11 is controlled by the FW executed by CPU 11. Furthermore, some or all of the FTL processing and instruction processing can be executed by dedicated hardware within controller 6.

[0027] NAND I / F 12 electrically connects controller 6 to NAND flash memory 4. NAND I / F 12 corresponds to interface standards such as Toggle DDR (double data rate) and Open NAND Flash Interface (ONFI).

[0028] NAND I / F 12 functions as a NAND control circuit that controls NAND flash memory 4. NAND I / F 12 can be connected to multiple memory chips within NAND flash memory 4 via multiple channels. By driving multiple memory chips in parallel, the access bandwidth between NAND flash memory 4 and controller 6 can be increased.

[0029] DRAM I / F 13 functions as a DRAM control circuit configured to control access to DRAM 5.

[0030] The host I / F 14 is a circuit that functions as an interface for communication between the memory system 3 and the host 2. The host I / F 14 includes circuitry for receiving various instructions (e.g., input / output (I / O) instructions and control instructions) and data from the host 2. I / O instructions include, for example, read instructions or write instructions. Control instructions include, for example, unmap instructions (trim instructions) or format instructions. The host I / F 14 also includes circuitry for sending responses and data corresponding to the instructions to the host 2.

[0031] The data decoding device 15 is an extender that expands (decodes) the compressed stream. The compressed stream is also called compressed data. The compressed stream is, for example, data sent from the host 2 to the memory system 3, or data read from the NAND flash memory 4. The CPU 11, for example, stores the compressed stream read from the NAND flash memory 4 according to a read command received from the host 2 in the DRAM 5. The Direct Memory Access Controller (DMAC) inputs the data stored in the DRAM 5 into the data decoding device 15 by means of data transfer using Direct Memory Access (DMA). The DMAC is, for example, located in the controller 6, and controls the data transfer between structural elements within the controller 6 (e.g., data transfer from the DRAM 5 to the data decoding device 15). Furthermore, the CPU 11 can read the compressed stream stored in the DRAM 5 and input the read compressed stream into the data decoding device 15. Moreover, the data decoding device 15 can also read the compressed stream stored in the DRAM 5. Then, the data decoding device 15 expands the input (read) compressed stream to generate expanded data (decoded data). More specifically, the data decoding device 15 expands the compressed stream for each compression unit (CU). A compression unit is a set of data units that are compressed at once.

[0032] When storing the compressed stream in NAND flash memory 4, pre-defined processes such as error correction or randomization can be performed. In this case, CPU 11 writes the data processed by the compressed stream into NAND flash memory 4 via NAND I / F 12. That is, CPU 11 writes data based on the compressed stream into NAND flash memory 4. Here, controller 6 may include a compression circuit, and the compressed stream is data compressed by the compression circuit of controller 6. Moreover, in this case, when CPU 11 reads the compressed stream from NAND flash memory 4, it reads the data based on the read command from host 2 from NAND flash memory 4 via NAND I / F 12. After performing pre-defined processes such as error correction and randomization removal on the data read from NAND flash memory 4, the data is stored as a compressed stream by CPU 11 in DRAM 5. The compressed stream stored in DRAM 5 is input to data decoding device 15 via CPU 11. The data decoding device 15 expands the input compressed stream to generate extended data (decoded data). That is, the data decoding device 15 expands the compressed stream based on the data read from the NAND flash memory 4 to generate extended data (decoded data).

[0033] Furthermore, when the data decoding device 15 reads the compressed stream from the DRAM 5, the DRAM 5 can begin data transmission to the data decoding device 15 via the DRAM I / F 13, for example, using the VALID and READY signals, thereby outputting the compressed stream of the compressed unit as a DATA signal to the data decoding device 15. Then, at the point in time when the last data in the compressed stream of the compressed unit is output, the DRAM 5 outputs a LAST signal indicating the end of the transmission of the compressed stream of the compressed unit. That is, the LAST signal indicates the end of the compressed stream of the compressed unit. In this way, the data decoding device 15 can read the compressed stream from the DRAM 5 for each compressed unit. The compressed stream may include multiple compressed units. When the compressed stream includes multiple compressed units, the LAST signal indicates the end of the compressed stream including multiple compressed units. The DRAM 5 outputs the LAST signal at the point in time when the transmission of the last compressed unit (more specifically, the last data of the last compressed unit) in the multiple compressed units included in the compressed stream ends. The following mainly illustrates the case where DRAM 5 outputs compressed data from the compression unit to the data decoding device 15 and outputs the LAST signal.

[0034] Figure 2 shows an example of the data structure of the compressed stream input to the data decoding device 15 and the LAST signal.

[0035] Compressed stream 7 is, for example, a data stream transmitted from a specific memory region to the data decoding device 15. The specific memory region is, for example, DRAM 5. Compressed stream 7 includes, for example, data compressed using entropy encoding. Furthermore, compressed stream 7 can also be data compressed by entropy encoding after performing arbitrary processing such as dictionary compression. That is, the data subject to entropy encoding can be data written as instructed by host 2, or data obtained by performing arbitrary processing such as dictionary compression on the data to be written. Specifically, compressed stream 7 sequentially includes compressed stream 70, compressed stream 71, ... of one or more compression units (CUs) from the beginning. Compressed streams 70, 71, ... of the compression units are data compressed using entropy encoding to compress the uncompressed data of the compression unit (e.g., data compressed by entropy encoding after dictionary compression). The compressed stream of the compression unit is also simply referred to as the compression unit.

[0036] Furthermore, dictionary-based compression is an encoding method that uses a history buffer to store past input data (i.e., symbol rows) to convert the data of the object to be compressed into indicators. Dictionary-based compression is also called dictionary encoding. Indices include, for example, consistency distance and consistency length. In dictionary-based compression, the history buffer is searched to retrieve at least a portion of past data that is consistent with the data of the object to be compressed, thus obtaining the consistency distance and consistency length. The consistency distance is the distance from the position in the history buffer where the data of the object to be compressed is stored to the position where the retrieved past data is stored. The consistency length is the length of the portion of the retrieved past data that is consistent with the data of the object to be compressed. In dictionary-based compression, data compression is achieved by converting the data of the object to be compressed into indicators (i.e., symbols including consistency distance and consistency length).

[0037] Compression unit 70, compression unit 71, ... each include one or more blocks. Specifically, compression unit 70 includes one or more blocks 70-1, 70-2, ..., and 70-N. Compression unit 71 includes one or more blocks 71-1, 71-2, ..., and 71-N.

[0038] Each block includes a header and a payload. Within a block, the header and payload are configured sequentially.

[0039] The header is a type 1 data section that includes the data (information) used to decode the payload. Specifically, the header includes final block information and data used to reconstruct the encoding table.

[0040] The final block information indicates whether the corresponding block is the final block in the compression unit (flag). The final block information is, for example, equivalent to the BFINAL field defined by the DEFLATE standard. If the corresponding block is the final block in the compression unit, the final block information displays, for example, "1". If the corresponding block is not the final block in the compression unit, the final block information displays, for example, "0". Furthermore, the values ​​indicating whether the corresponding block is the final block in the compression unit and whether the corresponding block is not the final block in the compression unit can be arbitrarily set.

[0041] An encoding table is a set of information that represents the correspondence between one or more symbols and one or more codewords (variable-length codes) assigned to each of those symbols. The codewords are converted (decoded) back into symbols using the restored encoding table. The restored encoding table is also called a decoding table.

[0042] The payload is a type II data section that includes the data to be decoded (encoded data). The data to be decoded may include, for example, codewords converted from symbols by entropy encoding.

[0043] In the example shown in Figure 2, the initial block 70-1 of the compression unit includes a header 80 and a payload 81. For example, final block information 80F is configured at the beginning of the header 80. Final block information 80F corresponds to the initial block 70-1. Therefore, the final block information 80F is set to a value (e.g., 0) indicating that block 70-1 is not the final block.

[0044] Furthermore, the final block 70-N of the compression unit 70 includes a header 85 and a payload 86. For example, final block information 85F is configured at the beginning of the header 85. Final block information 85F corresponds to the final block 70-N. Therefore, the final block information 85F is set with a value (e.g., 1) indicating that block 70-N is the final block.

[0045] Furthermore, at the time point when the last data is transmitted from compression unit 70, compression unit 71, etc. (i.e., the time point when the transmission of each compression unit ends), the LAST signal 9, indicating the end of each compression unit, is input to the data decoding device 15. In the example shown in FIG2, at the time point when the last data is transmitted from compression unit 70, the LAST signal 90 is input to the data decoding device 15. Moreover, at the time point when the last data is transmitted from compression unit 71, the LAST signal 91 is input to the data decoding device 15. By inputting the LAST signal 9, the data decoding device 15 can detect the end of the transmission of the corresponding compression unit.

[0046] Based on the data structure of compressed stream 7 and the LAST signal 9 described above, the data decoding device 15 expands compressed stream 7. Furthermore, the data structure of compressed stream 7 and the LAST signal 9 shown in FIG2 are examples. The data structure of compressed stream 7 and the LAST signal 9 can be replaced by any structure in which the data decoding device 15 can detect the terminals of one or more compression units and the final blocks in each compression unit. Hereinafter, any unspecified compressed stream 70, compressed stream 71, ... within a compression unit will also be referred to as compressed stream 7 of the compression unit.

[0047] Here, the data decoding device 15C of the comparative example will be described with reference to Figures 3 and 4.

[0048] Figure 3 is a block diagram showing the structure of the data decoding device 15C of the comparative example. The data decoding device 15C is a device that decodes the compressed stream 7C input from the outside and outputs the decoded data 43C obtained by decoding. The data decoding device 15C includes a header decoding unit 32C and a payload decoding unit 36C.

[0049] The header decoding unit 32C includes a shift register 31C. The shift register 31C stores the compressed stream 7C.

[0050] The header decoding unit 32C sequentially reads the compressed stream 7C from the shift register 31C starting from the beginning. The header decoding unit 32C obtains the header of the current block from the read data. The header decoding unit 32C uses the data included in the header to reconstruct the encoding table 42C. The header decoding unit 32C outputs the encoding table 42C to the payload decoding unit 36C. Furthermore, the header decoding unit 32C sequentially outputs the data stream following the header in the compressed stream 7C to the payload decoding unit 36C via the pipeline (decoding pipeline) from the header decoding unit 32C to the payload decoding unit 36C.

[0051] The payload decoding unit 36C uses the encoding table 42C to decode the data stream received via the decoding pipeline, thereby generating one or more symbols. Then, the payload decoding unit 36C outputs decoded data 43C including one or more symbols.

[0052] More specifically, the payload decoding unit 36C uses encoding table 42C to sequentially convert the data stream received via the decoding pipeline into symbols from the beginning. Then, based on the symbols obtained through the conversion as End Of Block (EOB) symbols, the payload decoding unit 36C detects the boundary between the current block and the next block. The EOB symbol is a symbol representing the end of the corresponding block.

[0053] As described above, the boundaries between blocks in the compressed stream 7C are detected based on the generation of EOB symbols using the payload decoding unit 36C. Therefore, there is a possibility that the data stream output from the header decoding unit 32C to the payload decoding unit 36C via the decoding pipeline includes the header of the next block.

[0054] When the payload decoding unit 36C receives the data stream of the payload following the current block, it inputs the data stream back into the header decoding unit 32C via the recycle path 40C (recycled input). In this way, the header decoding unit 32C and the payload decoding unit 36C can begin the decoding process of the next block.

[0055] In the decoding process of this comparative example data decoding apparatus 15C, for example, when decoding the compressed stream 7C for each compression unit, after detecting the boundary (i.e., EOB symbol) between the final block of the current compression unit and the starting block of the next compression unit through the payload decoding process, the decoding process of the header of the starting block begins. Therefore, in the data decoding apparatus 15C, during the execution of the payload decoding process of the final block of the current compression unit, the decoding process of the header of the starting block of the next compression unit is not executed. That is, in the data decoding apparatus 15C, the decoding process of the payload of the final block of the current compression unit and the decoding process of the header of the starting block of the next compression unit cannot be executed in parallel. Therefore, in the data decoding apparatus 15C, the processing volume (decoding efficiency) of data decoding is reduced.

[0056] Figure 4 is a timing diagram showing the execution time of header decoding and payload decoding in the comparative example data decoding apparatus 15C. In timing diagram 51C, the horizontal axis represents time. Here, a compression unit (CU) is assumed to include one block. In timing diagram 51C, the time for decoding the header of each compression unit by the header decoding unit 32C and the time for decoding the payload of each compression unit by the payload decoding unit 36C are shown in sequence.

[0057] In the data decoding apparatus 15C, header decoding processing performed by the header decoding unit 32C and payload decoding processing performed by the payload decoding unit 36C are executed alternately. Specifically, in the data decoding apparatus 15C, header decoding processing of compression unit CU0, payload decoding processing of compression unit CU0, header decoding processing of compression unit CU1, payload decoding processing of compression unit CU1, header decoding processing of compression unit CU2, payload decoding processing of compression unit CU2, header decoding processing of compression unit CU3, and payload decoding processing of compression unit CU3 are executed sequentially.

[0058] As described above, in the data decoding apparatus 15C, there is no situation where the decoding processing of the payload of the current compression unit (e.g., the decoding processing of the payload of compression unit CU0) and the decoding processing of the header of the next compression unit (e.g., the decoding processing of the header of compression unit CU1) are performed concurrently (i.e., in parallel) within overlapping time periods. In other words, in the data decoding apparatus 15C, the decoding processing of the headers of each compression unit is performed intermittently, and the decoding processing of the payload of each compression unit is performed intermittently. Therefore, in the data decoding apparatus 15C, the processing workload of decoding the compressed stream 7C is reduced.

[0059] In contrast, the data decoding apparatus 15 of this embodiment is configured to overlap at least a portion of the decoding processing of the payload of the block (e.g., the final block) included in the current compression unit with the decoding processing of the header of the block (e.g., the start block) included in the next compression unit. Specifically, for example, when the payload of the final block of the current compression unit needs to be decoded, the data decoding apparatus 15 transfers the payload from a first memory section of the compressed stream 7 containing the compression unit to a second memory section. Thereby, the compressed stream 7 of the next compression unit is written to the first memory section.

[0060] The structure of the data decoding device 15 is based on the following premises: (a) the boundary between the final block of the current compression unit and the starting block of the subsequent input compression unit can be determined by an external signal (e.g., LAST signal 9); (b) the payload of the final block in the compression unit is not followed by the header of the same compression unit, therefore it is not necessary to accurately segment the beginning of the header from the self-compression stream 7. Based on these premises (a) and (b), in the decoding of the payload of the final block, there is no need for a shift operation of the compression stream 7 corresponding to the amount of code consumed corresponding to the generated symbol. The amount of code consumed corresponding to the symbol is the amount of data of the codeword used to generate the symbol. Therefore, the data decoding device 15 stores the payload of the final block before decoding in the second memory unit and then performs decoding. The data decoding device 15 stores the next compression unit in the first memory unit by storing the payload of the final block in the second memory unit. In this way, the data decoding device 15 can begin decoding the header of the starting block of the next compression unit.

[0061] In this way, the data decoding device 15 can, for example, perform at least a portion of the process of decoding the payload of the final block of the current compressed unit read from the second memory and the process of decoding the header of the starting block of the next compressed unit read from the first memory. Therefore, compared with the data decoding device 15C of the comparative example, the data decoding device 15 can improve the amount of decoding (expansion) processing of the compressed stream 7.

[0062] Figure 5 is a block diagram showing an example of the structure of the data decoding device 15. The data decoding device 15 is input with, for example, a compressed stream 7 and a LAST signal 9 representing the terminal of the compressed stream 7. The data decoding device 15 decodes the compressed stream 7 and outputs decoded data 43.

[0063] The data decoding device 15 includes, for example, an input data receiving unit 30, a shift register 31, a header decoding unit 32, a demultiplexer (DEMUX) 33, a multiplexer (MUX) 34, a data buffer 35, and a payload decoding unit 36.

[0064] The structural elements within the data decoding device 15, including the input data receiving unit 30, shift register 31, header decoding unit 32, DEMUX 33, MUX 34, data buffer 35, and payload decoding unit 36, are implemented, for example, by at least one of a register, memory, adder, multiplier, selector, and other arithmetic units. The register is implemented, for example, by a timing circuit such as a flip-flop. The memory is implemented, for example, by memory elements such as SRAM or DRAM. The adder, multiplier, selector, and other arithmetic units are implemented, for example, by combinational logic circuits.

[0065] The input data receiving unit 30 receives data input (supply) from an external source. The received data includes, for example, compressed stream 7 and a LAST signal 9. Specifically, the input data receiving unit 30 receives compressed stream 7 from a compression unit until it receives the LAST signal 9 representing the end of compressed stream 7. Alternatively, the input data receiving unit 30 may receive uncompressed data streams from specific units instead of compressed stream 7 until it receives the LAST signal 9 representing the end of that data stream. The input data receiving unit 30 sequentially stores the received compressed stream 7 (or uncompressed data streams from specific units) in the shift register 31. Hereinafter, the case where the externally input data is compressed stream 7 from a compression unit and the LAST signal 9 representing the end of compressed stream 7 will be explained.

[0066] The input data receiving unit 30 disables (stops) writing data to the shift register 31 based on storing the compressed stream 7 of the compression unit in the shift register 31 to the terminal. Specifically, the input data receiving unit 30 determines to store the compressed stream 7 of the compression unit in the shift register 31 to the terminal based on receiving the LAST signal 9. Then, the input data receiving unit 30 sets the write permission / disable state of the shift register 31 to disabled (i.e., changes from permitted to disabled). The write permission / disable state of the shift register 31 indicates whether writing data to the shift register 31 is permitted or prohibited.

[0067] Furthermore, the input data receiving unit 30 restarts writing data to the shift register 31 by storing the payload 41 of the final block of the compressed stream 7 belonging to the compression unit in the data buffer 35. Specifically, the input data receiving unit 30 restarts writing data to the shift register 31 by setting the write enable / disable state of the shift register 31 to enable. In this way, the input data receiving unit 30 can begin the process of storing the compressed stream 7 of the next compression unit in the shift register 31.

[0068] The shift register 31 is a memory unit for storing data. The shift register 31 is, for example, a timing circuit comprising multiple flip-flops connected in sequence. The data capacity of the shift register 31 is, for example, smaller than the data size of the compression unit. The shift register 31 shifts the data stored in each flip-flop and stores new data. By performing this shift operation, at least a portion of the compressed stream 7 received by the input data receiving unit 30 is stored. In other words, the shift register 31 discards previously stored old data and stores new data by performing a shift operation.

[0069] The header decoding unit 32 decodes the headers 40 of each block included in the compressed stream 7. Specifically, the header decoding unit 32 reads the header 40 of a block (hereinafter referred to as the current block) included in the compressed stream 7 from the shift register 31. The header decoding unit 32 restores the encoding table 42 by decoding the read header 40. The header decoding unit 32 outputs the restored encoding table 42 to the payload decoding unit 36. The encoding table 42 can be used for decoding the payload 41 included in the current block.

[0070] Here, the operation of the header decoding unit 32 reading the header 40 from the shift register 31 will be specifically described. The header decoding unit 32 sequentially reads data (data stream) from the shift register 31. The read data is at least a portion of the header 40. The header decoding unit 32 dynamically determines the overall size of the header 40 to be read by referring to one or more fields representing the structure of the header 40 included in the read data. The header decoding unit 32 reads data of the determined size, including the read data, from the shift register 31. Alternatively, the header decoding unit 32 reads from the shift register 31 until the end of the data used to reconstruct the encoding table 42 is detected. By reading data from the shift register 31 in this way, the header decoding unit 32 obtains the data portion corresponding to the header 40. Therefore, the header decoding unit 32 is able to decode the header 40 of the current block.

[0071] The header decoding unit 32 notifies the shift register 31 of the size 46 (hereinafter also referred to as the header consumption code amount 46) of the data read from the header 40. The header decoding unit 32 can determine that it is part of the header 40 and successively notifies the shift register 31 of the size of the data read from the shift register 31. In the shift register 31, during the compression stream 7 of the current compression unit input from the outside, a shift operation is performed based on the notified header consumption code amount 46. In this way, the previously stored old data is discarded and new data is stored in the shift register 31.

[0072] Furthermore, the header decoding unit 32 includes a final block determination unit 321.

[0073] The final block determination unit 321 obtains final block information 44 from the header 40. Final block information 44 indicates whether the current block described in the header 40 is the final block in the compressed stream 7 of the current compression unit. Based on the obtained final block information 44, the final block determination unit 321 determines whether the current block is the final block in the compressed stream 7 of the current compression unit. Furthermore, the final block determination unit 321 outputs the final block information of the block to the shift register 31, DEMUX 33, and MUX 34, for example, until the payload 41 belonging to that block is transferred from the shift register 31 to the transmission destination. In the following description, the final block information is displayed as "1" when the corresponding block is the final block, and as "0" when the corresponding block is not the final block.

[0074] When the current block is the final block in the compressed stream 7 of the current compression unit, the header decoding unit 32 starts the process of decoding the header 40 by writing the header 40 of the beginning block in the compressed stream 7 of the next compression unit into the shift register 31.

[0075] DEMUX 33 is a selection circuit that switches the transmission destination of the payload 41 from the shift register 31 based on the final block information 44 output by the final block determination unit 321.

[0076] If the final block information indicates that the current block is not the final block (represented by "0" in Figure 5), DEMUX 33 selects MUX 34 as the transmission destination for payload 41. That is, DEMUX 33 outputs (transmits) the payload 41 read from shift register 31 to MUX 34.

[0077] When the final block information indicates that the current block is the final block (represented by "1" in Figure 5), the DEMUX 33 selects the data buffer 35 as the transmission destination for the payload 41. That is, the DEMUX 33 stores (transmits) the payload 41 read from the shift register 31 to the data buffer 35. Specifically, the DEMUX 33 reads the data from the end of the compressed stream 7 of the compressed unit stored in the shift register 31 as the payload 41 belonging to the current block. Then, the DEMUX 33 writes the read payload into the data buffer 35. In this way, the payload 41 of the final block is deferred to the data buffer 35. Furthermore, the payload 41 of the final block may include data other than the codewords to be decoded.

[0078] MUX 34 is a selection circuit that switches the transmission source of the payload 41 transmitted to the payload decoding unit 36 ​​based on the final block information 44 output by the final block determination unit 321.

[0079] If the final block information indicates that the current block is not the final block (represented by "0" in Figure 5), MUX 34 selects DEMUX 33 as the transmission source for payload 41. Then, MUX 34 outputs the payload 41, which is output via DEMUX 33, to the payload decoding unit 36. That is, if the final block information indicates that the current block is not the final block, the payload decoding unit 36 ​​reads the payload 41 from the shift register 31 via DEMUX 33 and MUX 34.

[0080] When the final block information indicates that the current block is the final block (represented by "1" in Figure 5), the MUX 34 selects the data buffer 35 as the transmission source for the payload 41. Then, the MUX 34 outputs the payload 41 stored in the data buffer 35 to the payload decoding unit 36. That is, when the final block information indicates that the current block is the final block, the payload decoding unit 36 ​​reads the payload 41 from the data buffer 35 via the MUX 34.

[0081] As described above, if the final block information indicates that the current block is not the final block, the path from DEMUX 33 to MUX 34 is valid. On the other hand, if the final block information indicates that the current block is the final block, the path from DEMUX 33 to MUX 34 via data buffer 35 is valid.

[0082] Data buffer 35 is a memory unit capable of temporarily storing payload 41. Data buffer 35 is, for example, a volatile memory such as first-in-first-out (FIFO) memory. Specifically, data buffer 35 stores the final block of payload 41 read from shift register 31 and written to data buffer 35 by DEMUX 33. The final block of payload 41 stored in data buffer 35 is read by MUX 34 and output to payload decoding unit 36.

[0083] The payload decoding unit 36 ​​decodes the payload 41 of each block included in the compressed stream 7. Specifically, the payload decoding unit 36 ​​receives the encoding table 42 corresponding to the current block from the header decoding unit 32. Furthermore, the payload decoding unit 36 ​​receives the payload 41 belonging to the current block from the MUX 34. Using the encoding table 42, the payload decoding unit 36 ​​decodes (converts) one or more codewords included in the payload 41 into one or more symbols. Then, the payload decoding unit 36 ​​outputs the decoded data 43, which includes one or more symbols, obtained through decoding.

[0084] Furthermore, the payload decoding unit 36 ​​outputs one or more symbols obtained through decoding to the header decoding unit 32. When the symbol received from the payload decoding unit 36 ​​is an EOB symbol 45, the header decoding unit 32 begins processing to decode the header 40 of the next block. In this case, the next block is the block following the current block in the compressed stream 7 of the current compression unit.

[0085] Furthermore, when the payload decoding unit 36 ​​receives a payload from an uncompressed data stream instead of the payload 41 from the compressed data stream 7, it directly outputs the symbols included in that data stream as decoded data 43. Moreover, the payload decoding unit 36 ​​directly outputs the symbols included in that data stream to the header decoding unit 32. Based on the symbol count information included in the header 40, the header decoding unit 32 detects the block termination of the symbols decoded by the payload decoding unit 36.

[0086] Here, the operation of the payload decoding unit 36 ​​receiving the payload 41 will be further explained in detail.

[0087] If the current block is not the final block, the payload decoding unit 36 ​​sequentially receives data (data stream) read from the shift register 31 via DEMUX 33 and MUX 34. The received data is at least a portion of the payload 41. The payload decoding unit 36 ​​uses the encoding table 42 to decode the codewords included in the received data into symbols. If the symbol obtained by decoding is EOB symbol 45, the payload decoding unit 36 ​​ends the reception of the payload 41 belonging to the current block. That is, by reading data from the shift register 31 until obtaining EOB symbol 45, the payload decoding unit 36 ​​obtains the data portion corresponding to the payload 41 of the current block. In this way, the payload decoding unit 36 ​​is able to decode the payload 41 of the current block.

[0088] When the current block is the final block, the payload decoding unit 36 ​​receives the payload 41 of the final block read from the data buffer 35 via the MUX 34. The payload decoding unit 36 ​​can sequentially receive the data (data stream) constituting the payload 41 of the final block from the beginning. The payload decoding unit 36 ​​uses the encoding table 42 to decode the codewords included in the received payload 41 into symbols. In this way, the payload decoding unit 36 ​​can decode the payload 41 of the final block. After the payload decoding unit 36 ​​receives the entire payload 41 of the final block, the data stored in the data buffer 35 can be discarded.

[0089] Furthermore, if the current block is not the final block, the payload decoding unit 36 ​​notifies the shift register 31 of the size 47 of the data read as payload 41 (hereinafter also referred to as payload consumption code amount 47). The payload decoding unit 36 ​​may notify the shift register 31 of the size of a portion of the decoded payload 41 sequentially. In the shift register 31, during the compression stream 7 of the current compression unit input from the outside, a shift operation is performed based on the notified payload consumption code amount 47. In this way, in the shift register 31, previously stored old data is discarded and new data is stored.

[0090] If the current block is the final block, the payload decoding unit 36 ​​may not notify the shift register 31 of the payload consumption code amount 47. This is because the boundary between the final block of the current compression unit and the starting block of the next compression unit can be determined by an external signal (e.g., the LAST signal 9). That is, the shift register 31 can perform a shift operation based on, for example, the LAST signal 9, to discard the data of the current compression unit and store the data of the next compression unit.

[0091] Using the above structure, the data decoding device 15 decodes the header 40 and payload 41 of each block included in the compressed stream 7 and expands the compressed stream 7. Specifically, the header decoding unit 32 recovers the encoding table 42 by parsing the header 40 and obtains the final block information 44. The payload decoding unit 36 ​​uses the encoding table 42 to decode the codewords included in the payload 41 into symbols.

[0092] Furthermore, DEMUX 33 stores the payload 41 of the final block of the compressed stream 7 of the current compression unit in the data buffer 35. This allows the compressed stream 7 of the next compression unit to be stored in the shift register 31. Then, the header decoding unit 32 begins processing to decode the header 40 by writing the header 40 of the beginning block of the compressed stream 7 of the next compression unit into the shift register 31.

[0093] Therefore, in the data decoding apparatus 15, at least a portion of the processing of the payload 41 of the final block of the compressed stream 7 of the current compression unit by the payload decoding unit 36 ​​and the processing of the header 40 of the beginning block of the compressed stream 7 of the next compression unit by the header decoding unit 32 can be overlapped (executed in parallel). Therefore, compared to the comparative example data decoding apparatus 15C, which starts the header decoding unit 32C decoding the beginning block of the compressed stream 7C of the next compression unit after the payload decoding unit 36C has completed the processing of the payload of the final block of the compressed stream 7C of the current compression unit, the data decoding apparatus 15 can improve the decoding throughput.

[0094] Next, referring to Figures 6 to 8, the processing performed in the data decoding device 15 will be described.

[0095] Figure 6 is a flowchart illustrating an example of the sequence of the first processes executed in the data decoding apparatus 15. The first process is the process of controlling the writing (storage) of data to the shift register 31. The input data receiving unit 30 executes the first process, for example, when there is a compressed stream 7 to be decoded. The compressed stream 7 to be decoded is, for example, stored in DRAM 5.

[0096] First, the input data receiving unit 30 receives input data (step S101). The input data is, for example, at least a portion of the compressed stream 7 transmitted from the DRAM 5 to the data decoding device 15. The input data receiving unit 30 writes the received input data into the shift register 31 (step S102).

[0097] The input data receiving unit 30 determines whether to store the compressed stream 7 of the compression unit to the end in the shift register 31 (step S103). Specifically, the input data receiving unit 30 determines whether to store the compressed stream 7 of the compression unit to the end in the shift register 31 based, for example, on the LAST signal 9 specified by the AXI-4 Stream interface standard. For example, if the LAST signal 9 is "1", the input data receiving unit 30 determines that the compressed stream 7 of the compression unit will be stored to the end in the shift register 31. Moreover, if the LAST signal is "0", the input data receiving unit 30 determines that the compressed stream 7 of the compression unit will not be stored to the end in the shift register 31.

[0098] If the compressed stream 7 of the compression unit is not stored to the end in the shift register 31 (No in step S103), the input data receiving unit 30 returns to step S101. That is, the input data receiving unit 30 continues to receive input data and write to the shift register 31.

[0099] When the compressed stream 7 of the compression unit is stored to the end in the shift register 31 (yes in step S103), the input data receiving unit 30 prohibits writing data to the shift register 31 (step S104). That is, the input data receiving unit 30 sets the write permission / prohibition state of the shift register 31 to prohibited. Herein, no new input data (e.g., the compressed stream 7 of the next compression unit) is written to the shift register 31.

[0100] Next, the input data receiving unit 30 checks the write permission / prohibition status of the shift register 31 (step S105). The write permission / prohibition status of the shift register 31 changes from prohibited to permitted, for example, based on the write permission notification from the header decoding unit 32 (more specifically, the final block determination unit 321). Furthermore, the shift register 31 can input the final block information 44 representing the final block in the compressed stream 7 of the current compression unit from the header decoding unit 32 into the shift register 31, and change the write permission / prohibition status to permitted based on reading the payload 41 of the final block from the shift register 31 (i.e., based on the data buffer 35). Then, the input data receiving unit 30 determines whether to permit data writing to the shift register 31 (step S106).

[0101] If writing data to the shift register 31 is prohibited (No in step S106), the input data receiving unit 30 returns to step S105. That is, the input data receiving unit 30 repeats the processing of steps S105 and S106 until writing data to the shift register 31 is permitted.

[0102] If writing data to the shift register 31 is permitted (yes in step S106), the input data receiving unit 30 returns to step S101. That is, the input data receiving unit 30 receives the input data of the compressed stream 7 constituting the next compression unit and writes it to the shift register 31.

[0103] Through the first processing described above, the input data receiving unit 30 can control the reception of compressed stream 7 from the outside and the writing to the shift register 31 for each compression unit. Specifically, the input data receiving unit 30 can prevent new input data from being written to the shift register 31 from the time the compressed stream 7 of the compression unit is stored to the end in the shift register 31 until the payload 41 of the final block in the compressed stream 7 of the compression unit is transferred from the shift register 31 to the data buffer 35.

[0104] Furthermore, the compressed stream 7 may include multiple compression units. In this case, the LAST signal 9 becomes "1" at the time point when the transmission of the last compression unit among the multiple compression units included in the compressed stream 7 is completed. The first processing step S103 described above can be replaced, for example, with the following step: the input data receiving unit 30 determines, based on the LAST signal 9, whether to store the compressed stream 7 including multiple compression units at the end in the shift register 31.

[0105] Figure 7 is a flowchart illustrating an example of the sequence of the second processing performed in the data decoding apparatus 15. The second processing is used to decode the headers 40 of each block included in the compressed stream 7. The header decoding unit 32 and DEMUX 33 perform the second processing, for example, when at least a portion of the compressed stream 7 of the compression unit is stored in the shift register 31 and not processed.

[0106] First, the header decoding unit 32 determines whether to write the header 40 of the next block (hereinafter also referred to as the object block) to the shift register 31 (step S201). The object block is either: (A) a block in the compressed stream 7 of the current compression unit that follows the block before the encoding table 42 to be restored by the header decoding unit 32; or (B) a block at the beginning of the compressed stream 7 of the next compression unit of the compression unit whose compressed stream 7 is the final block. The header decoding unit 32 determines whether the header 40 of the object block has been written, for example, based on the amount of data stored in the shift register 31.

[0107] If the header 40 of the object block is not written to the shift register 31 (No in step S201), the header decoding unit 32 returns to step S201. In other words, the header decoding unit 32 waits until the header 40 of the object block is written to the shift register 31.

[0108] When the header 40 of the target block is written to the shift register 31 (as in step S201), the header decoding unit 32 reads the header 40 of the target block from the shift register 31 (step S202). The header decoding unit 32 uses the read header 40 to restore the encoding table 42 corresponding to the target block (step S203). The header decoding unit 32 outputs the restored encoding table 42 to the payload decoding unit 36 ​​(step S204). Furthermore, the header decoding unit 32 (more specifically, the final block determination unit 321) obtains the final block information 44 from the read header 40 (step S205). The header decoding unit 32 outputs the obtained final block information 44 to the shift register 31, DEMUX 33, and MUX 34 (step S206). Furthermore, the processing of steps S203 and S204 can be performed in a different order than the processing of steps S205 and S206, or they can be performed in parallel.

[0109] Next, the header decoding unit 32 uses the acquired final block information 44 to determine whether the target block is the final block in the compressed stream 7 of the current compression unit (step S207). The final block information displays "1" if the target block is the final block, and "0" if the target block is not the final block. In this case, the header decoding unit 32 determines whether the final block information displays "1" (final block) or "0" (non-final block).

[0110] If the target block is not the final block (No in step S207), the header decoding unit 32 receives a symbol from the payload decoding unit 36 ​​(step S208). Then, the header decoding unit 32 determines whether the received symbol is an EOB symbol 45 (step S209).

[0111] If the received symbol is not EOB symbol 45 (No in step S209), the header decoding unit 32 returns to step S208. That is, the header decoding unit 32 waits until it receives EOB symbol 45 from the payload decoding unit 36.

[0112] If the received symbol is EOB symbol 45 (yes in step S209), the header decoding unit 32 returns to step S201. That is, the header decoding unit 32 obtains the EOB symbol 45 representing the terminal of the current block by decoding the payload 41 performed by the payload decoding unit 36, and therefore further performs the processing to decode the header 40 of the next block.

[0113] Furthermore, if the target block is the final block (as in step S207), the DEMUX 33 reads the data from the shift register 31 to the end of the compressed stream 7 of the current compression unit as the payload 41 of the target block (step S210). The DEMUX 33 stores the read payload 41 in the data buffer 35 (step S211). Then, the header decoding unit 32 notifies the shift register 31 of write permission (step S212) and returns to step S201. That is, the header decoding unit 32 stores (backs off) the payload 41 of the final block in the compressed stream 7 of the current compression unit to the data buffer 35, and therefore notifies the shift register 31 of write permission. In this way, the writing of the compressed stream 7 of the next compression unit can begin in the shift register 31. Moreover, the header decoding unit 32 can begin the process of decoding the header 40 of the starting block in the compressed stream 7 of the next compression unit (i.e., the second process).

[0114] Through the second processing described above, the header decoding unit 32 can decode the headers 40 of each block included in the compressed stream 7 to obtain the encoding table 42 and the final block information 44. Furthermore, when the target block is the final block, the DEMUX 33 stores the payload 41 of the final block in the compressed stream 7 of the current compression unit in the data buffer 35. This allows the shift register 31 to be written to the compressed stream 7 of the next compression unit. Therefore, in the data decoding apparatus 15, for example, at least a portion of the decoding of the payload 41 of the final block in the compressed stream 7 of the current compression unit and the decoding of the header 40 of the starting block in the compressed stream 7 of the next compression unit can be performed in parallel.

[0115] Figure 8 is a flowchart illustrating an example of the sequence of the third processing performed in the data decoding apparatus 15. The third processing is used to decode the payload 41 of each block included in the compressed stream 7. The payload decoding unit 36, DEMUX 33, and MUX 34 perform the third processing, for example, when at least a portion of the compressed stream 7 of the compression unit is stored in the shift register 31 without being processed.

[0116] First, the payload decoding unit 36 ​​receives the encoding table 42 of the next block (object block) from the header decoding unit 32 (step S301). Then, the payload decoding unit 36 ​​receives the final block information 44 from the header decoding unit 32 (step S302). Furthermore, the execution order of the processing in step S301 and the processing in step S302 can be changed. Using the received final block information 44, the payload decoding unit 36 ​​determines whether the object block is the final block in the compressed stream 7 of the current compression unit (step S303).

[0117] If the target block is not the final block (No in step S303), DEMUX 33 reads the payload 41 of the target block from shift register 31 (step S304). DEMUX 33 outputs the read payload 41 to MUX 34 (step S305). MUX 34 outputs the payload 41 received from DEMUX 33 to payload decoding unit 36 ​​(step S306). Payload decoding unit 36 ​​decodes the payload 41 received from MUX 34 using encoding table 42 to generate symbols (step S307). Payload decoding unit 36 ​​outputs the generated symbols as decoding data 43 to header decoding unit 32 (step S308), and proceeds to step S313.

[0118] On the other hand, if the target block is the final block (as in step S303), the MUX 34 reads the payload 41 of the target block (i.e., the final block) from the data buffer 35 (step S309). The MUX 34 outputs the payload 41 read from the data buffer 35 to the payload decoding unit 36 ​​(step S310). The payload decoding unit 36 ​​decodes the payload 41 received from the MUX 34 using the encoding table 42 to generate symbols (step S311). The payload decoding unit 36 ​​outputs the generated symbols as decoded data 43 (step S312) and proceeds to step S313.

[0119] Then, the payload decoding unit 36 ​​determines whether the generated symbol is an EOB symbol 45 (step S313).

[0120] If the generated symbol is not an EOB symbol 45 (No in step S313), the payload decoding unit 36 ​​returns to step S303. That is, the payload decoding unit 36 ​​obtains the payload 41 from the shift register 31 via DEMUX 33 and MUX 34, or obtains the payload 41 from the data buffer 35 via MUX 34, and continues the processing to decode the obtained payload 41.

[0121] If the generated symbol is EOB symbol 45 (as in step S313), the payload decoding unit 36 ​​returns to step S301. That is, the payload decoding unit 36 ​​further performs processing to decode the payload 41 for the next block. In this case, the next block is: (A) if the target block is not the final block, it is the block of the target block in the compressed stream 7 of the current compression unit; (B) if the target block is the final block, it is the starting block in the compressed stream 7 of the compressed stream 7 of the compressed unit that follows the current compression unit.

[0122] Through the third processing described above, the payload decoding unit 36 ​​can decode either the payload 41 obtained from the shift register 31 via DEMUX 33 and MUX 34, or the payload 41 obtained from the data buffer 35 via MUX 34. The payload decoding unit 36 ​​obtains the payload 41 of the final block in the compressed stream 7 of the compression unit from the data buffer 35, rather than from the shift register 31. This is because the payload 41 of the final block is moved from the shift register 31 to the data buffer 35 based on the header decoding unit 32's determination that the target block is the final block. This allows the shift register 31 to be written into the compressed stream 7 of the next compression unit. Furthermore, in the data decoding apparatus 15, for example, at least a portion of the decoding of the payload 41 of the final block in the compressed stream 7 of the current compression unit (i.e., the payload 41 stored in the data buffer 35) and the decoding of the header 40 of the starting block in the compressed stream 7 of the next compression unit (i.e., the header 40 stored in the shift register 31) can be performed in parallel. Therefore, in the data decoding apparatus 15, the processing capacity of decoding the compressed stream 7 can be increased.

[0123] Figure 9 is a timing diagram illustrating an example of the execution time of the header 40 decoding process and the payload 41 decoding process in the data decoding apparatus 15. In timing diagram 51, the horizontal axis represents time. Here, it is assumed that the compressed stream 7 of a compression unit includes one block. In timing diagram 51, the time for decoding the header 40 of each compression unit by the header decoding unit 32 and the time for decoding the payload 41 of each compression unit by the payload decoding unit 36 ​​are shown in chronological order.

[0124] In the data decoding apparatus 15, at least a portion of the decoding of the header 40 performed by the header decoding unit 32 and the decoding of the payload 41 performed by the payload decoding unit 36 ​​are performed concurrently. Specifically, in the data decoding apparatus 15, after decoding the header 40 of the compression unit CU0, at least a portion of the decoding of the payload 41 of the compression unit CU0 and the header 40 of the compression unit CU1 are performed concurrently. Then, at least a portion of the decoding of the payload 41 of the compression unit CU1 and the header 40 of the compression unit CU2 are performed concurrently. Finally, at least a portion of the decoding of the payload 41 of the compression unit CU2 and the header 40 of the compression unit CU3 are performed concurrently.

[0125] In other words, the header decoding unit 32 sequentially executes the processing to decode the headers 40 of compression unit CU0, CU1, CU2, and CU3. Similarly, the payload decoding unit 36 ​​sequentially executes the processing to decode the payloads 41 of compression unit CU0, CU1, CU2, and CU3. Furthermore, at least a portion of the processing performed by the header decoding unit 32 and the processing performed by the payload decoding unit 36 ​​are performed in parallel. Moreover, the decoding processing of the payload 41 belonging to a block (final block) of a certain compression unit using the payload decoding unit 36 ​​and the decoding processing of the header 40 belonging to a block (starting block) of the next compression unit using the header decoding unit 32 can either begin first or simultaneously. For example, the decoding process of the payload 41 belonging to the final block of a certain compression unit using the payload decoding unit 36 ​​begins before the decoding process of the header 40 belonging to the beginning block of the next compression unit using the header decoding unit 32.

[0126] As described above, in the data decoding apparatus 15, the decoding of the payload 41 of a compression unit (e.g., the decoding of the payload 41 of compression unit CU0) and the decoding of the header 40 of the next compression unit (e.g., the decoding of the header 40 of compression unit CU1) are performed concurrently (i.e., in parallel). Therefore, compared to the decoding of the compressed stream 7C performed using the data decoding apparatus 15C in the comparative example, the data decoding apparatus 15 can increase the processing capacity of decoding (expanding) the compressed stream 7.

[0127] As explained above, the data decoding apparatus 15 according to this embodiment can improve the amount of data decoding processed.

[0128] Shift register 31 stores a first data stream (e.g., compressed stream 7 of a compression unit) comprising one or more first blocks, each of which includes a header 40 and a payload 41. Header decoding unit 32 decodes the header 40. Data buffer 35 stores the payload 41. Payload decoding unit 36 ​​decodes the payload 41. DEMUX 33 switches the destination from shift register 31 to transmit the payload 41. MUX 34 switches the source from which the payload 41 is transmitted to the payload decoding unit 36. When a second block within one or more first blocks is the final block in the first data stream, DEMUX 33 transmits the payload 41 included in the second block from shift register 31 to data buffer 35, and MUX 34 transmits the payload 41 stored in data buffer 35 to payload decoding unit 36.

[0129] This allows for the writing of, for example, a second data stream (e.g., compressed stream 7 of the next compression unit) to the shift register 31. Furthermore, in the data decoding apparatus 15, at least a portion of the process of decoding the payload 41 of the final block of the first data stream read from the data buffer 35 and the process of decoding the header 40 of the beginning block of the second data stream read from the shift register 31 can be performed concurrently. Therefore, the data decoding apparatus 15 can improve the amount of data decoding of the compressed stream 7 compared to the comparative example's data decoding apparatus 15C.

[0130] The various functions described in this embodiment can be implemented by circuits (processing circuits). Examples of processing circuits include a programmed processor, such as a central processing unit (CPU). This processor executes the described functions by executing a computer program (command set) stored in memory. The processor can be a microprocessor that includes electrical circuits. Examples of processing circuits also include digital signal processors (DSPs), application-specific integrated circuits (ASICs), microcontrollers, controllers, and other electrical circuit components. Other components besides the CPU described in this embodiment can also be implemented by processing circuits.

[0131] Several embodiments of the present invention have been described, but these embodiments are merely illustrative examples and do not limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention described in the patent application and its equivalents.

[0132] 1: Information Processing System 2: Host 3: Memory System 4: NAND flash memory 5: DRAM 6: Controller 7, 7C: Compressed Flow 9, 90, 91: LAST signal 10: Busbar 11: CPU 12: NAND I / F 13:DRAM I / F 14: Host I / F 15, 15C: Data decoding device 30: Input Data Receiving Department 31, 31C: Shift registers 32, 32C: Header Decoding Unit 33:DEMUX 34:MUX 35: Data Buffer 36, 36C: Payload decoding unit 40, 80, 85: Header 40C: Loop Path 41, 81, 86: Payload 42, 42C: Encoding Table 43, 43C: Decoded Data 44, 80F, 85F: Final Block Information 45: EOB symbol 46: Header code consumption 47: Payload code consumption 51, 51C: Timing Diagram 70, 71, CU0, CU1, CU2, CU3: Compression units Blocks 70-1, 70-2, 70-N, 71-1, 71-2, 71-N 321: Final Block Decision Department

Claims

1. A data decoding device, comprising: A first memory unit stores a first data stream comprising one or more first blocks, each of which includes a first type of data unit and a second type of data unit; a first decoding unit decodes the first type of data unit; a second memory unit stores the second type of data unit; a second decoding unit decodes the second type of data unit; a first selection unit switches the transmission destination for transmitting the second type of data unit from the first memory unit; and a second selection unit switches the transmission source for transmitting the second type of data unit to the second decoding unit. When the second block within the one or more first blocks is the final block in the first data stream, the first selection unit transmits the second type of second data unit included in the second block from the first memory unit to the second memory unit, and the second selection unit transmits the second data unit stored in the second memory unit to the second decoding unit.

2. The data decoding apparatus as claimed in claim 1, wherein when the second block is the final block in the first data stream, the first memory unit stores a second data stream including one or more third blocks, the one or more third blocks respectively including a first-type data unit and a second-type data unit, and the decoding of the second data unit included in the second block using the second decoding unit is performed in parallel with the decoding of the first-type data unit included in the first block of the one or more third blocks using the first decoding unit.

3. The data decoding apparatus as claimed in claim 2, wherein the second data stream is input after the first data stream and first information of the terminal representing the first data stream are input to the data decoding apparatus.

4. The data decoding apparatus as described in claim 3, further comprising: The receiving unit, by receiving the first information, detects that the data input to the data decoding device is the second data stream.

5. The data decoding apparatus as claimed in claim 2, wherein the first memory unit stores the second data stream after transmitting the second data unit from the first memory unit to the second memory unit.

6. The data decoding apparatus as claimed in claim 2, wherein the first data stream and the second data stream are each a compressed stream storing one or more compression units.

7. The data decoding apparatus as claimed in claim 6, wherein the compressed stream is a compressed stream obtained using entropy coding.

8. The data decoding apparatus of claim 1, wherein the first data unit of the first type included in the second block includes second information indicating whether the second block is the final block, and the first decoding unit obtains the second information from the first data unit.

9. The data decoding apparatus of claim 8, wherein the first decoding unit outputs the second information to the first selection unit and the second selection unit, and when the second information indicates that the second block is the final block, the first selection unit transfers the second data portion included in the second block from the first memory unit to the second memory unit, and the second selection unit transfers the second data portion stored in the second memory unit to the second decoding unit.

10. The data decoding apparatus of claim 9, wherein the first selection unit and the second selection unit transmit the second data portion of the second block from the first memory unit to the second decoding unit when the second information indicates that the second block is not the final block.

11. The data decoding apparatus of claim 1, wherein the first data stream is a compressed stream obtained using entropy coding, the first decoding unit uses the first data unit of the first type included in the second block to restore an encoding table, the encoding table representing a correspondence between a plurality of symbols and a plurality of codes respectively assigned to the plurality of symbols, and the second decoding unit uses the encoding table to convert one or more codes included in the second data unit into symbols respectively.

12. The data decoding apparatus of claim 11, wherein the first decoding unit outputs the encoding table to the second decoding unit, the second decoding unit receives the encoding table from the first decoding unit, and receives the second data unit transmitted from either the first memory unit or the second memory unit.

13. The data decoding apparatus of claim 11, wherein the second decoding unit outputs the symbol to the first decoding unit, and the first decoding unit decodes the first type of data unit included in the fourth block following the second block when the second block is not the final block and the symbol is a block terminal symbol representing the terminal of the second block.

14. The data decoding apparatus as claimed in claim 1, wherein the first memory unit is a shift register and the second memory unit is a data buffer.

15. The data decoding apparatus as claimed in claim 1, further comprising: The data receiving unit receives the first data stream and stores the first data stream in the first memory unit. The second type of data unit is input to the data receiving unit after the first type of data unit.

16. A memory system, comprising: Non-volatile memory; Random access memory; The controller is configured to access the non-volatile memory and the random access memory, including a data decoding device as described in any one of claims 1 to 14, wherein the controller is configured to: read the first data stream from the non-volatile memory, store the read first data stream in the random access memory, and input the first data stream stored in the random access memory into the data decoding device.

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