Semiconductor device with covering insulation liner and method for fabricating the same

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate having an array region and a peripheral region adjacent to the array region; a first trench disposed inwardly within the array region; a basin disposed inwardly within the peripheral region; a filling insulating layer completely filling the first trench and covering an upper surface of the substrate within the array region; an upper insulating layer disposed on the filling insulating layer and within the array region; and a covering insulating pad conformally completely covering the upper insulating layer and an inner surface of the basin. The covering insulating pad and the upper insulating layer are in direct contact with each other.

Claims

1. A semiconductor element, comprising: A substrate having an array region and a peripheral region adjacent to the array region; A first trench is disposed inwardly in the array area; a basin is disposed inwardly in the peripheral area; a filling insulating layer completely fills the first trench and covers an upper surface of the substrate in the array area; an upper insulating layer is disposed on the filling insulating layer and in the array area; and a covering insulating pad conformally completely covers the upper insulating layer and an inner surface of the basin, wherein the covering insulating pad and the upper insulating layer are in direct contact with each other.

2. The semiconductor element as claimed in claim 1 further includes a peripheral insulating layer conformally disposed between the covering insulating pad and the inner surface of the basin.

3. The semiconductor device as claimed in claim 1 further includes an insulating layer conformally disposed along the first trench and disposed between the filling insulating layer and the substrate within the array region.

4. The semiconductor device as claimed in claim 3 further includes a repair layer conformally disposed between the filling insulating layer and the substrate within the array region.

5. The semiconductor device as claimed in claim 3, wherein the lower insulating layer comprises: The lower part is conformally disposed along the first trench and between the filling insulating layer and the substrate within the array region; And an upper part, which is conformally disposed between the lower part and the filling insulation layer.

6. The semiconductor device as claimed in claim 5, wherein the thickness of the upper portion is between approximately 5 nm and approximately 15 nm.

7. The semiconductor device as claimed in claim 5, wherein the thickness of the lower portion is approximately 1 nm.

8. The semiconductor element as claimed in claim 5, wherein the lower portion and the upper portion comprise silicon oxide.

9. The semiconductor device as claimed in claim 1, wherein the covering insulating pad comprises silicon nitride.

10. The semiconductor device as claimed in claim 1, wherein the upper insulating layer comprises silicon nitride.

11. The semiconductor device as claimed in claim 2, wherein the peripheral insulating layer comprises silicon oxide.

12. The semiconductor device as claimed in claim 8, wherein an atomic composition of the upper portion comprises silicon, oxygen, chlorine, and hydrogen.

13. The semiconductor device as claimed in claim 8, wherein an atomic composition of the lower portion comprises silicon and oxygen.

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