Overlay measurement method of overlay mark
Patent Information
- Application Number
- TW114131704
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2025-08-06
- Filing Date
- 2025-08-20
- Publication Date
- 2026-09-11
- Estimated Expiration
- 2045-08-19
Smart Images

Figure TWG2TB001910731_001 
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Figure TWG2TB001910731_003
Abstract
Claims
1. A method for measuring the overlap of overlapping marks, comprising: An overlay mark is provided, wherein the overlay mark includes a plurality of first patterns and a plurality of second patterns arranged in parallel in a first direction, each of the first patterns and each of the second patterns being strip-shaped and extending in a second direction orthogonal to the first direction, and the plurality of first patterns and the plurality of second patterns being arranged in the second direction; Using an overlay measurement device, multiple region selection processes are performed on the overlay mark. Each region selection process includes: defining a region corresponding to a pattern as a first region; and defining a region between adjacent patterns as a second region. After each region selection process, an offset value calculation process is performed. This offset value calculation process includes: using the overlay measurement device, performing image processing corresponding to the result of the region selection process to obtain a first grayscale signal of the plurality of first patterns and a second grayscale signal of the plurality of second patterns in the first direction; and using the overlay measurement device, calculating an initial offset value based on the first grayscale signal and the second grayscale signal. After multiple region selection processes, multiple initial offset values are obtained, including multiple good values and multiple bad values. The good values correspond to the case where neither the first region nor the second region contains the edge portion of the pattern, and the bad values include all values other than the good values. The multiple bad values are excluded, and a final offset value is obtained based on the multiple good values.
2. The method for measuring the overlap of overlapping marks as described in claim 1, wherein the defective value corresponds to the case where the first region does not contain the edge portion of the pattern, while the second region does contain the edge portion of the pattern.
3. The method for measuring the overlap of overlapping marks as described in claim 1, wherein the defective value corresponds to the case where the first region contains the edge portion of the pattern and the second region does not contain the edge portion of the pattern.
4. The method for measuring the overlap of overlapping marks as described in claim 1, wherein the defective value corresponds to the case where both the first region and the second region contain the edge portion of the pattern.
5. The method for measuring the overlap of overlapping marks as described in claim 1, wherein the final offset value is the average of the plurality of good values.
6. The method for measuring the overlap of overlapping marks as described in claim 1, wherein the region selection process is performed at least 7 times for the overlapping mark.
7. The method for measuring the overlay of overlay markers as described in claim 1, wherein the overlay markers include advanced image metrology markers.
8. The method for measuring the superposition of superposition marks as described in claim 7, wherein the superposition measuring device includes an image measurement system.
9. The method for measuring the overlap of overlap marks as described in claim 1, wherein the overlap marks are disposed in the dicing region of a semiconductor substrate.
Citation Information
Patent Citations
Overlay mark, and overlay measurement method and semiconductor device manufacturing method using same
CN108351595A
Mark for overlay measurement
TW202328699A
Method for overlay error correction and method for manufacturing a semiconductor device structure with overlay marks
TW202329211A
Single pad overlay measurement
TW202411775A
Overlay marks, methods of overlay mark design and methods of overlay measurements
US20030021466A1