Semiconductor memory devices

Abstract

This invention provides a high-speed semiconductor memory device. The semiconductor memory device includes: a plurality of memory block regions arranged in a first direction; a connection region arranged in the first direction relative to the plurality of memory block regions; and a wiring region extending in the first direction and arranged with the plurality of memory block regions in a second direction intersecting the first direction. Each of the plurality of memory block regions includes: a plurality of memory strings extending in the first direction and arranged in the second direction; and a first wiring extending in the second direction, commonly connected to the plurality of memory strings. The wiring region includes a second wiring extending in the first direction and commonly connected to the plurality of first wirings corresponding to the plurality of memory block regions. The connection region includes a contact electrode extending in a third direction intersecting the first and second directions and electrically connected to the second wiring. A first transistor is disposed in the current path between the first wiring and the second wiring.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Prior Technology

[0002] A semiconductor memory device is known to have a plurality of memory cells stacked in a direction intersecting with the surface of a substrate. Summary of the Invention

[0003] A high-speed semiconductor memory device is provided.

[0004] An embodiment of a semiconductor memory device includes: a plurality of memory block regions arranged in a first direction; a connection region arranged in the first direction relative to the plurality of memory block regions; and a wiring region extending in the first direction and arranged with the plurality of memory block regions in a second direction intersecting the first direction. Each of the plurality of memory block regions includes: a plurality of memory strings extending in the first direction and arranged in the second direction; and a first wiring extending in the second direction, commonly connected to the plurality of memory strings. The wiring region includes a second wiring extending in the first direction and commonly connected to the plurality of first wirings corresponding to the plurality of memory block regions. The connection region includes a contact electrode extending in a third direction intersecting the first and second directions and electrically connected to the second wiring. A first transistor is disposed in the current path between the first wiring and the second wiring. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic top view showing a portion of the structure of the semiconductor memory device of the first embodiment. Figure 2 is a circuit diagram showing a portion of the semiconductor memory device. Figure 3 is a schematic top view showing a portion of the semiconductor memory device. Figure 4 is a magnified schematic top view of a portion of Figure 3. Figure 5 is a schematic three-dimensional view that includes the portion shown in Figure 4. Figure 6 is a schematic cross-sectional view of the structure shown in Figure 4 cut along line A-A' and viewed in the direction of the arrow. Figure 7 is a schematic cross-sectional view of the structure shown in Figure 4 cut along line B-B' and viewed in the direction of the arrow. Figure 8 is a schematic cross-sectional view of the structure shown in Figure 4 cut along line C-C' and viewed in the direction of the arrow. Figure 9 shows a schematic top view of a portion of the RHU (Relative Hub) connection area. Figure 10 is a schematic cross-sectional view of the structure shown in Figure 9 cut along line D-D' and viewed in the direction of the arrow. Figure 11 is a schematic cross-sectional view of the structure shown in Figure 9 cut along line E-E' and viewed in the direction of the arrow. Figure 12 is a schematic top view used to illustrate a variation of the semiconductor memory device of the first embodiment. Figure 13 is a circuit diagram showing a portion of the semiconductor memory device of the second embodiment. Figure 14 is a schematic top view showing a portion of the semiconductor memory device. Figure 15 is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device in the first and second embodiments. Figure 16 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 17 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 18 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 19 is a schematic top view used to illustrate the manufacturing method. Figure 20 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 21 is a schematic top view used to illustrate the manufacturing method. Figure 22 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 23 is a schematic top view used to illustrate the manufacturing method. Figure 24 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 25 is a schematic top view used to illustrate the manufacturing method. Figure 26 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 27 is a schematic top view used to illustrate the manufacturing method. Figure 28 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 29 is a schematic top view used to illustrate the manufacturing method. Figure 30 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 31 is a schematic top view used to illustrate the manufacturing method. Figure 32 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 33 is a schematic top view showing a portion of the semiconductor memory device of the third embodiment. Figure 34 is a schematic top view showing a portion of the semiconductor memory device of the fourth embodiment. Figure 35 is a schematic cross-sectional view showing a portion of the semiconductor memory device of the fifth embodiment. Figure 36 is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device. Figure 37 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 38 is a schematic cross-sectional view used to illustrate the manufacturing method. Implementation

[0006] Next, the semiconductor memory device of each embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic; for ease of explanation, some components may be omitted. Also, common parts in multiple embodiments may be labeled with the same symbols, and descriptions may be omitted.

[0007] Furthermore, when the term "semiconductor memory device" is used in this specification, it sometimes refers to a memory chip, and sometimes to a memory system that includes a controller chip, such as a memory chip, memory card, or SSD (Solid State Drive). Additionally, it sometimes refers to a device including a host computer, such as a smartphone, tablet, or personal computer.

[0008] Furthermore, in this specification, when the first component and the second component are "electrically connected," the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is still "electrically connected" to the third transistor.

[0009] Furthermore, in this specification, when referring to the situation where the first component is "connected" to the second and third components, it is intended to mean that the first, second, and third components are connected in series, and that the second component is connected to the third component via the first component.

[0010] Furthermore, in this specification, when referring to a situation where a circuit or the like "conducts" two wirings, for example, it sometimes means that the circuit or the like includes a transistor or the like, which is placed in the current path between the two wirings, and the transistor or the like is in an ON state.

[0011] Furthermore, in this specification, the specified direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0012] Furthermore, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specified surface is referred to as the third direction. These first, second, and third directions may correspond to any of the X, Y, and Z directions, or they may not correspond to each other.

[0013] Furthermore, in this specification, the terms "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Also, when referring to a component as a lower surface or lower end, it means the surface or end of that component on the substrate side; when referring to an upper surface or upper end, it means the surface or end of that component opposite to the substrate. Also, the surface intersecting the X or Y direction is called a side surface, etc.

[0014] [First Implementation Form] [constitute] Figure 1 is a schematic top view showing a portion of the configuration of a semiconductor memory device according to a first embodiment. Figure 2 is a circuit diagram showing a portion of the configuration of a semiconductor memory device according to a first embodiment. For example, as shown in Figure 1, the semiconductor memory device of this embodiment includes a plurality of memory block regions RBLK, connection regions RHU, and a plurality of connection line regions RLBIY. The memory block regions RBLK are arranged in a matrix in the X and Y directions. The connection regions RHU are correspondingly arranged with the plurality of memory block regions RBLK arranged in the Y direction. The connection regions RHU are adjacent to the memory block regions RBLK in the Y direction. The connection line regions RLBIY are respectively arranged with the plurality of memory block regions RBLK arranged in the Y direction and with the corresponding connection regions RHU. The connection line regions RLBIY are arranged with the plurality of memory block regions RBLK in the X direction.

[0015] In the memory block region RBLK, there are a plurality of memory strings MS extending in the Y direction and arranged in the X direction, and a local block connection line LBIX extending in the X direction and commonly connected to the plurality of memory strings MS.

[0016] For example, as shown in Figure 2, a memory string MS includes a plurality of memory transistors (memory cells MC) connected in series, and select transistors SG connected to them. One end of the memory string MS is connected to the local block connection line LBIX, and the other end is connected to the source line CSL.

[0017] In the connection area RLBIEY (Fig. 1), a local block connection line LBIY extending in the Y direction is provided. A plurality of local block connection lines LBIX arranged in the Y direction are commonly connected to the local block connection line LBIY. Furthermore, the local block connection line LBIY is electrically connected to a peripheral circuit (not shown) via at least one of a plurality of contact electrodes CC provided in the connection area RHU.

[0018] In the examples shown in Figures 1 and 2, a local block select transistor SWX1 is provided between the plurality of memory strings MS disposed in a memory block region RBLK and the local block connection line LBIY. Also, in the example shown in Figure 1, a local block select transistor SWY1 is provided between the local block connection line LBIY and the contact electrode CC.

[0019] The local block selection transistor SWX1 functions as a switch for selecting at least one memory block region RBLK.

[0020] In the following context, during write and read operations, the memory block region RBLK containing the memory cell MC that is the object of the operation is sometimes referred to as the selected memory block region RBLK, and the memory block region RBLK that does not contain the memory cell MC that is the object of the operation is sometimes referred to as the non-selected memory block region RBLK.

[0021] During write and read operations, for example, the local block selection transistor SWX1, which is set to the on state between the selected memory block region RBLK and the local block connection line LBIY connected to the selected memory block region RBLK, is set to the off state.

[0022] The local block selection transistor SWY1 functions as a switch for selecting at least one local block connection line LBIY.

[0023] During write and read operations, for example, the local block selection transistor SWY1, which is set to the ON state between the local block connection line LBIY connected to the selected memory block area RBLK and the contact electrode CC connected to the local block connection line LBIY, is set to the OFF state.

[0024] Figure 3 is a schematic top view showing a portion of the semiconductor memory device according to the first embodiment. Figure 3 shows a portion of two adjacent memory block regions RBLK in the Y direction. Figure 4 is a schematic top view showing an enlarged portion of Figure 3. Figures 3 and 4 are also schematic top views showing the structure of the memory layer ML, which will be described later. Figure 5 is a schematic perspective view including the portion shown in Figure 4. Figure 6 is a schematic cross-sectional view taken along line A-A' of the structure shown in Figure 4, viewed in the direction of the arrow. Figure 7 is a schematic cross-sectional view taken along line B-B' of the structure shown in Figure 4, viewed in the direction of the arrow. Figure 8 is a schematic cross-sectional view taken along line C-C' of the structure shown in Figure 4, viewed in the direction of the arrow.

[0025] Figure 3 shows a plurality of memory strings MS set in the memory block region RBLK, local block connection line LBIX, region RSWX, and local block connection line LBIY set in the connection line region RLBIY.

[0026] Additionally, in the following description, the region within a plurality of memory strings MS containing a plurality of memory cells MC is sometimes referred to as the memory cell region RMC, and the region containing a plurality of select transistors SG is referred to as select transistor regions RSG1 and RSG2. Select transistor region RSG1 is located closer to the local block interconnect line LBIX than select transistor region RSG2.

[0027] Figure 5 shows a portion of the semiconductor substrate Sub. The semiconductor substrate Sub is, for example, a semiconductor substrate containing silicon (Si) or other P-type impurities such as boron (B). As shown in Figure 5, the semiconductor memory device of this embodiment has a plurality of memory layers ML arranged in the Z direction above the semiconductor substrate Sub. An insulating layer 101, such as silicon oxide (SiO2), is disposed between two adjacent memory layers ML in the Z direction.

[0028] The memory layer ML comprises a plurality of semiconductor layers 110 arranged in the X direction. Each of these semiconductor layers 110 extends along the Y direction, spanning a plurality of memory cell regions RMC and a plurality of select transistor regions RSG1 and RSG2 as illustrated in FIG3. The semiconductor layer 110 functions, for example, as a channel region for a plurality of memory cells MC and select transistors SG connected in series. The semiconductor layer 110 may, for example, contain undoped polycrystalline silicon (Si).

[0029] For example, as shown in Figure 4, in the memory block region RBLK, an insulating layer 123 such as silicon oxide (SiO2) is provided between adjacent semiconductor layers 110 in the X direction.

[0030] For example, as shown in Figure 4, in the memory cell region RMC, a plurality of conductive layers 120 arranged in the Y direction are disposed between the semiconductor layer 110 and the insulating layer 123, and gate insulating layers 130 are disposed between the plurality of conductive layers 120 and the semiconductor layer 110 respectively.

[0031] The conductive layer 120 functions, for example, as the gate electrode of a plurality of memory transistors and the word lines connected thereto. The conductive layer 120 may include, for example, a multilayer film of titanium nitride (TiN), tungsten (W), and the like. For example, as shown in Figures 5 and 6, the conductive layer 120 extends along the Z direction through a plurality of memory layers ML and is aligned with the semiconductor layer 110 of each memory layer ML.

[0032] For example, as shown in Figure 6, the gate insulating layer 130 includes a tunnel insulating layer 131 disposed on the X-direction side of the semiconductor layer 110, a charge storage layer 132 disposed on the X-direction side thereof, and a barrier insulating layer 133 disposed on the X-direction side thereof.

[0033] The tunnel insulation layer 131 may, for example, contain silicon oxide (SiO2) or the like.

[0034] The charge storage layer 132 may include, for example, polycrystalline silicon (Si). Furthermore, the polycrystalline silicon (Si) may contain N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may not contain such impurities.

[0035] The barrier insulating layer 133 may include, for example, silicon oxide (SiO2). Alternatively, the barrier insulating layer 133 may include aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0036] For example, as shown in Figure 4, a conductive layer 140 is provided in the selected transistor regions RSG1 and RSG2, and a conductive layer 144 is provided near the selected transistor region RSG2.

[0037] The conductive layer 140 functions, for example, as a contact electrode for supplying voltage to the semiconductor layer 110. The conductive layer 140 may, for example, comprise a semiconductor layer containing p-type impurities such as boron (B) or polycrystalline silicon (Si). The conductive layer 140 extends along the Z-direction, penetrating a plurality of memory layers ML.

[0038] Additionally, the conductive layer 140 is sometimes also used as a contact electrode for supplying voltage to the semiconductor layer 110, and is disposed in areas other than the selected transistor regions RSG1 and RSG2.

[0039] The conductive layer 144 functions, for example, as a contact electrode for supplying voltage to the semiconductor layer 110. The conductive layer 144 may, for example, comprise a semiconductor layer such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P). The conductive layer 144 extends along the Z-direction, penetrating a plurality of memory layers ML. The conductive layer 144 may function as part of the source line CSL.

[0040] Additionally, the conductive layer 144 is sometimes also used as a contact electrode for supplying voltage to the semiconductor layer 110, and is disposed in a region other than the vicinity of the selected transistor region RSG2.

[0041] For example, as shown in Figure 4, in the selected transistor regions RSG1 and RSG2, a plurality of conductive layers 150 arranged in the Y direction are disposed between the semiconductor layer 110 and the insulating layer 123, and a gate insulating layer 160 is disposed between the plurality of conductive layers 150 and the semiconductor layer 110, respectively.

[0042] The conductive layer 150 functions, for example, as the gate electrode of the select transistor SG and the wiring connected thereto. The conductive layer 150 may include, for example, a multilayer film of titanium nitride (TiN), tungsten (W), and the like. For example, as shown in FIG7, the conductive layer 150 extends along the Z direction through a plurality of memory layers ML and is aligned with the semiconductor layer 110 of each memory layer ML.

[0043] For example, as shown in FIG7, the gate insulating layer 160 includes an insulating layer 161 disposed on the side of the semiconductor layer 110 in the X direction and an insulating layer 163 disposed on the side of the semiconductor layer 110 in the X direction.

[0044] The insulating layer 161 may, for example, contain silicon oxide (SiO2) or the like.

[0045] The insulating layer 163 may include, for example, silicon oxide (SiO2). Alternatively, the insulating layer 163 may include aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0046] Furthermore, the configuration of the gate insulating layer 160 shown in Figure 7 is merely an example. For instance, the gate insulating layer 160 may have the same configuration as the gate insulating layer 130. In such cases, for example, the gate insulating layer 160 may have the same layer as the charge storage layer 132 (Figure 6) disposed between the insulating layers 161 and 163.

[0047] For example, as shown in Figure 4, in the region adjacent to the selected transistor region RSG1 in the Y direction, the memory layer ML has a conductive layer 170 extending in approximately the X direction. Furthermore, a plurality of insulating layers 171 are provided arranged along the conductive layer 170.

[0048] The conductive layer 170 functions, for example, as a local block interconnect (LBIX) (Figures 1 and 2). The conductive layer 170 may, for example, comprise a conductive layer such as titanium nitride (TiN). The conductive layer 170 is connected to a plurality of semiconductor layers 110 via semiconductor layers 111. The conductive layer 170 is electrically connected, for example, to semiconductor layers 110 arranged on both sides of the conductive layer 170 in the Y direction.

[0049] Semiconductor layers 111 are disposed on both sides of conductive layer 170 in the Y direction. Semiconductor layers 111 may include, for example, polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P).

[0050] The insulating layer 171 may include, for example, silicon oxide (SiO2). The insulating layer 171 extends along the Z direction through a plurality of memory layers ML.

[0051] For example, as shown in Figure 4, in the connection line region RLBIEY, the memory layer ML has a conductive layer 180 extending in the Y direction. Furthermore, a plurality of insulating layers 181 arranged along the conductive layer 180 are provided in the connection line region RLBIEY.

[0052] The conductive layer 180 functions, for example, as a local block interconnect line LBIY (Figures 1 and 2). The conductive layer 180 may include, for example, a conductive layer such as titanium nitride (TiN). The conductive layer 180 is connected to the semiconductor layer 110 in the region RSWX via the semiconductor layer 112.

[0053] Semiconductor layer 112 is disposed on a portion of the side of conductive layer 180. Semiconductor layer 112 may, for example, contain the same material as semiconductor layer 111.

[0054] The insulating layer 181 may include, for example, silicon oxide (SiO2). For example, as shown in FIG5, the insulating layer 181 extends along the Z direction through a plurality of memory layers ML.

[0055] For example, as shown in Figures 3 and 4, region RSWX is positioned adjacent to local block connection lines LBIX and LBIY. A local block selection transistor SWX1 is located in region RSWX (Figure 4).

[0056] For example, as shown in Figure 4, in region RSWX, a plurality of conductive layers 350 arranged in the Y direction are disposed between semiconductor layer 110 and insulating layer 123, and gate insulating layers 360 are disposed between the plurality of conductive layers 350 and semiconductor layer 110 respectively.

[0057] The conductive layer 350 functions, for example, as the gate electrode of the local block select transistor SWX1 and the wiring connected thereto. The conductive layer 350 may include, for example, a multilayer film of titanium nitride (TiN), tungsten (W), and the like. For example, as shown in FIG8, the conductive layer 350 extends along the Z direction through a plurality of memory layers ML and is aligned with the semiconductor layer 110 of each memory layer ML.

[0058] For example, as shown in Figure 8, the gate insulating layer 360 includes an insulating layer 361 disposed on the side of the semiconductor layer 110 in the X direction and an insulating layer 363 disposed on the side of the semiconductor layer 110 in the X direction.

[0059] The insulating layer 361 may, for example, contain silicon oxide (SiO2) or the like.

[0060] The insulating layer 363 may, for example, contain silicon oxide (SiO2). Alternatively, the insulating layer 363 may contain aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0061] Furthermore, the configuration of the gate insulating layer 360 shown in Figure 8 is merely an example. For instance, the gate insulating layer 360 may have the same configuration as the gate insulating layer 130. In such a case, for example, the gate insulating layer 360 may have the same layer as the charge storage layer 132 (Figure 6) disposed between the insulating layers 361 and 363.

[0062] In the example shown in Figure 4, in region RSWX, a plurality of conductive layers 350 are provided on one side of the region relative to the semiconductor layer 110 in the X direction, and a conductive layer 140 is provided on the other side of the region in the X direction. The conductive layer 140 is disposed between the insulating layer 123 and the semiconductor layer 110. This conductive layer 140 functions, for example, as the main contact electrode of the local block select transistor SWX1.

[0063] Furthermore, this configuration is merely an example and the specific configuration can be adjusted accordingly. For example, in region RSWX, a plurality of conductive layers 350 can be provided not only on one side of the region relative to the semiconductor layer 110 in the X direction, but also on the other side of the region relative to the semiconductor layer 110 in the X direction. These plurality of conductive layers 350 can, for example, be provided between the insulating layer 123 and the semiconductor layer 110. Alternatively, gate insulating layers 360 can be provided between each of these plurality of conductive layers 350 and the semiconductor layer 110.

[0064] Alternatively, as shown in Figure 4, conductive layers 120, 150, and 350 can be arranged at equal intervals in the Y direction.

[0065] Figure 9 is a schematic top view showing a portion of the connected region RHU. Figure 10 is a schematic cross-sectional view taken along line D-D', cutting through the structure shown in Figure 9 and viewed in the direction of the arrow. Figure 11 is a schematic cross-sectional view taken along line E-E', cutting through the structure shown in Figure 9 and viewed in the direction of the arrow.

[0066] For example, as shown in Figure 9, in the connection region RHU, the memory layer ML has a plurality of conductive layers 190 extending in a generally X direction. Furthermore, the connection region RHU has a plurality of insulating layers 191 arranged along the conductive layers 190. Also, a region RSWY is provided between the connection region RHU and the connection line region RLBIY.

[0067] The conductive layer 190 functions, for example, as a lead-out wiring from the contact electrode CC to each memory layer ML. The conductive layer 190 may include, for example, a conductive layer such as titanium nitride (TiN). The conductive layer 190 is connected to the semiconductor layer 110 in the region RSWY via the semiconductor layer 113.

[0068] Semiconductor layer 113 is disposed on a portion of the side of conductive layer 190. Semiconductor layer 113 may, for example, contain the same material as semiconductor layer 111.

[0069] The insulating layer 191 may include, for example, an insulating layer such as silicon oxide (SiO2). The insulating layer 191 extends along the Z direction through a plurality of memory layers ML.

[0070] Furthermore, as shown in Figure 9, a plurality of contact electrodes CC are provided in the connection region RHU, arranged along the conductive layer 190 in the X and Y directions. Between the plurality of contact electrodes CC, the memory layer ML has an insulating layer 102, such as silicon nitride (SiN).

[0071] For example, as shown in Figure 10, the contact electrode CC has a generally cylindrical portion 192 and a generally disk-shaped portion 193 disposed at the lower end of the portion 192.

[0072] Part 192 may include, for example, a barrier conductive layer 194 of titanium nitride (TiN) and a conductive layer 195 of tungsten (W). Part 192 extends along the Z direction through a plurality of memory layers ML.

[0073] Part 193 may include, for example, a barrier conductive layer 194 such as titanium nitride (TiN). Part 193 is included in any memory layer ML and is connected to the side of the conductive layer 190 contained in any memory layer ML in the X direction. Additionally, contact electrodes CC corresponding to all memory layers ML may be provided in the connection region RHU. In this case, the number of contact electrodes CC may be the same as the number of memory layers ML, or it may be greater than the number of memory layers ML.

[0074] A local block selection transistor SWY1 is set in the RSWY region.

[0075] For example, as shown in Figure 9, in region RSWY, a plurality of conductive layers 450 arranged in the Y direction are disposed between semiconductor layer 110 and insulating layer 123, and gate insulating layers 460 are disposed between the plurality of conductive layers 450 and semiconductor layer 110 respectively.

[0076] The conductive layer 450 functions, for example, as the gate electrode of the local block select transistor SWY1 and the wiring connected thereto. The conductive layer 450 may include, for example, a multilayer film of titanium nitride (TiN), tungsten (W), and the like. For example, as shown in FIG11, the conductive layer 450 extends along the Z direction through a plurality of memory layers ML and is aligned with the semiconductor layer 110 of each memory layer ML.

[0077] For example, as shown in FIG11, the gate insulating layer 460 includes an insulating layer 461 disposed on the side of the semiconductor layer 110 in the X direction and an insulating layer 463 disposed on the side of the semiconductor layer 110 in the X direction.

[0078] The insulating layer 461 may, for example, contain silicon oxide (SiO2) or the like.

[0079] The insulating layer 463 may include, for example, silicon oxide (SiO2). Alternatively, the insulating layer 463 may include aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0080] Furthermore, the configuration of the gate insulating layer 460 shown in Figure 11 is merely an example. For instance, the gate insulating layer 460 may have the same configuration as the gate insulating layer 130. In such cases, for example, the gate insulating layer 460 may have the same layer as the charge storage layer 132 (Figure 6) disposed between the insulating layers 461 and 463.

[0081] Additionally, the conductive layer 180 (local block interconnect line LBIY) is connected to the semiconductor layer 110 in region RSWY via the semiconductor layer 114.

[0082] Semiconductor layer 114 is disposed on a portion of the side of conductive layer 180. Semiconductor layer 114 may, for example, contain the same material as semiconductor layer 111.

[0083] In the example shown in Figure 9, in region RSWY, a plurality of conductive layers 450 are provided on one side of the region relative to the semiconductor layer 110 in the X direction, and a conductive layer 140 is provided on the other side of the region in the X direction. The conductive layer 140 is disposed between the insulating layer 123 and the semiconductor layer 110. This conductive layer 140 functions, for example, as the main contact electrode of the local block select transistor SWY1.

[0084] Furthermore, this configuration is merely an example and the specific configuration can be adjusted accordingly. For example, in region RSWY, a plurality of conductive layers 450 can be provided not only on one side of the semiconductor layer 110 in the X direction but also on the other side of the semiconductor layer 110 in the X direction. These plurality of conductive layers 450 can, for example, be provided between the insulating layer 123 and the semiconductor layer 110. Alternatively, gate insulating layers 460 can be provided between each of these plurality of conductive layers 450 and the semiconductor layer 110.

[0085] [Effect] A semiconductor memory device is known, comprising layers arranged in the Z-direction, each layer having a plurality of semiconductor layers and a plurality of conductive layers. In this semiconductor memory device, connection regions are provided for connecting the layers arranged in the Z-direction to peripheral circuitry. A plurality of contact electrodes extending in the Z-direction are provided in the connection regions. Furthermore, in this semiconductor memory device, local wiring is provided in each layer arranged in the Z-direction to connect the contact electrodes to the plurality of semiconductor layers.

[0086] In the Z-direction, increasing the number of semiconductor layers connected to the local wiring can reduce the wafer area, but sometimes it can lead to an increase in the load capacitance attached to the local wiring and semiconductor layers, resulting in a decrease in operating speed.

[0087] In this embodiment, a local block selector transistor SWX1 is provided between the local block connection line LBIX and the local block connection line LBIY, and a local block selector transistor SWY1 is provided between the local block connection line LBIY and the contact electrode CC.

[0088] Based on this configuration, by setting the local block selection transistor SWX1 connected to the selected memory block area RBLK to the ON state and setting the local block selection transistor SWX1 connected to the non-selected memory block area RBLK to the OFF state, the load capacitance originating from the non-selected memory block area RBLK can be reduced, thereby improving the operating speed.

[0089] Furthermore, by setting the local block selection transistor SWY1 connected to the selected memory block region RBLK to the ON state, and setting the local block selection transistor SWY1 of all connected memory block regions RBLK to the OFF state, the load capacitance of the local block connection line LBIY from which all connected memory block regions RBLK are not selected can be reduced, thereby further improving the operating speed.

[0090] [Example of variation] The configuration of the local block connection line LBIX and the region RSWX shown in Figures 3 to 5 is only an example and the specific configuration can be adjusted appropriately.

[0091] Figure 12 is a schematic top view used to illustrate a variation of the semiconductor memory device of the first embodiment. For example, in the configuration of this variation illustrated in Figure 12, two local block connection lines LBIXa arranged in the Y direction are provided instead of local block connection lines LBIX, and two regions RSWXa disposed between the two local block connection lines LBIXa are provided instead of regions RSWX.

[0092] The local block interconnect LBIXa is basically set in the same way as the local block interconnect LBIX (Fig. 4). However, the conductive layer 170 (Fig. 12) that functions as the local block interconnect LBIXa is electrically connected, for example, to the semiconductor layer 110 in a plurality of memory strings MS arranged on one side of the conductive layer 170 in the Y direction.

[0093] A local block selection transistor SWX1a is set in region RSWXa.

[0094] The local block select transistor SWX1a is disposed in essentially the same manner as the local block select transistor SWX1 (FIG. 4). However, the local block select transistor SWX1a is connected to the conductive layer 180, for example, via a semiconductor layer 112a disposed on the side of the conductive layer 180. The semiconductor layer 112a contains the same material as the semiconductor layer 112.

[0095] In this configuration, since the number of memory strings MS connected to a local block connection line LBIXa is half that of the configuration in the first embodiment (Figs. 3 to 5), the load capacity can be further reduced.

[0096] [Second Implementation] [constitute] Figure 13 is a circuit diagram showing a portion of the configuration of the semiconductor memory device according to the second embodiment. Figure 14 is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the second embodiment.

[0097] Furthermore, in the following description, the same symbols are used for components that are the same as those in the first embodiment, and the explanations are omitted.

[0098] The semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of this embodiment, the local block select transistor SWX1 (Fig. 1) is not provided between the local block connection line LBIX and the local block connection line LBIY. Instead, local block select transistors SWX2N and SWX2P (Fig. 13) are provided in parallel.

[0099] The local block selection transistors SWX2N and SWX2P function as switches for selecting at least one memory block region RBLK. The local block selection transistor SWX2N is an N-type transistor with electrons as carriers. It is connected to conductive layers 170 and 180 via semiconductor layers 111 and 112, such as polycrystalline silicon (Si) containing N-type impurities. The local block selection transistor SWX2P is a P-type transistor with holes as carriers. It is connected to conductive layers 170 and 180 via semiconductor layers 115 and 115b, such as polycrystalline silicon (Si) containing P-type impurities.

[0100] During write and read operations, for example, at least one of the local block selection transistors SWX2N and SWX2P, which are set to the selected memory block region RBLK and the local block connection line LBIY connected to the selected memory block region RBLK, is set to the ON state, and both of the local block selection transistors SWX2N and SWX2P, which are set to the OFF state, are set to the OFF state.

[0101] Furthermore, as shown in Figure 14, the semiconductor memory device of this embodiment replaces one region RSWX (Figure 4) and has regions RSWX2N and RSWX2P (Figure 14).

[0102] For example, as shown in Figure 14, the region RSWX2N is located on one side of the local block connection line LBIX in the Y direction and adjacent to the local block connection line LBIY. A local block selection transistor SWX2N is provided in the region RSWX2N.

[0103] The local block select transistor SWX2N is configured in essentially the same way as the local block select transistor SWX1 (Figure 4).

[0104] For example, as shown in Figure 14, the region RSWX2P is located on the other side of the local block connection line LBIX in the Y direction and adjacent to the local block connection line LBIY. A local block selection transistor SWX2P is provided in the region RSWX2P.

[0105] The local block select transistor SWX2P is basically set in the same way as the local block select transistor SWX1 (Figure 4). However, the area where the local block select transistor SWX2P is set has a conductive layer 144 instead of a conductive layer 140.

[0106] Furthermore, the local block selected transistor SWX2P is connected to the conductive layer 170 via a semiconductor layer 115 disposed on a portion of the side surface of the conductive layer 170 in the Y direction. The semiconductor layer 115 may, for example, contain polycrystalline silicon (Si) with P-type impurities such as boron (B).

[0107] Furthermore, the local block selected transistor SWX2P is connected to the conductive layer 180, for example, via a semiconductor layer 115b disposed on the side of the conductive layer 180 in the X direction. The semiconductor layer 115b may contain the same material as the semiconductor layer 115.

[0108] [Effect] In this embodiment, N-type and P-type transistors, namely local block select transistors SWX2N and SWX2P, are respectively connected in parallel between local block connection line LBIX and local block connection line LBIY. With this configuration, even when the capacitive coupling between adjacent memory layers ML in the Z direction is strong, voltage transmission between local block connection line LBIX and local block connection line LBIY can be reliably performed in the memory layer ML of the operating object.

[0109] [Manufacturing Method] Figures 15-32 are schematic top views or cross-sectional views used to illustrate the manufacturing methods of the semiconductor memory devices of the first and second embodiments. Figures 15, 19, 21, 23, 25, 27, 29, and 31 are schematically shown on a single plane to illustrate the manufacturing methods of the semiconductor layers 110, 111, 112, 115, conductive layers 120, 140, 144, 150, 170, 180, 350, insulating layers 123, 171, 181, and gate insulating layers 130, 160, 360 of the first and second embodiments. The conductive layer 450 and gate insulating layer 460 are formed essentially the same as the conductive layers 150, 350, and gate insulating layers 160, 360, and are therefore omitted.

[0110] Figure 16 is a schematic sectional view taken along line F1-F1', cutting through the structure shown in Figure 15 and viewed in the direction of the arrows. Figures 17 and 18 are sectional views of the corresponding portions of Figure 16. Figure 20 is a schematic sectional view taken along line F1-F1', cutting through the structure shown in Figure 19 and viewed in the direction of the arrows. Figure 22 is a schematic sectional view taken along line F1-F1', cutting through the structure shown in Figure 21 and viewed in the direction of the arrows. Figure 24 is a schematic sectional view taken along line F2-F2', cutting through the structure shown in Figure 23 and viewed in the direction of the arrows. Figure 26 is a schematic sectional view taken along line F3-F3', cutting through the structure shown in Figure 25 and viewed in the direction of the arrows. Figure 28 is a schematic sectional view taken along line F4-F4', cutting through the structure shown in Figure 27 and viewed in the direction of the arrows. Figure 30 is a schematic sectional view taken along line F5-F5', cutting through the structure shown in Figure 29 and viewed in the direction of the arrows. Figure 32 is a schematic cross-sectional view of the structure shown in Figure 29 cut along line F6-F6' and viewed in the direction of the arrow.

[0111] In this manufacturing method, for example as shown in FIG16, a plurality of insulating layers 101 and a plurality of insulating layers 102 are alternately formed. This step is performed, for example, by CVD (Chemical Vapor Deposition).

[0112] Next, as shown in Figures 15 and 16, openings 120A, 123A, 140A, 144A, 150A, 171A, 181A, and 350A are formed. These openings 120A, 123A, 140A, 144A, 150A, 171A, 181A, and 350A, like openings 120A and 123A shown in Figure 16, extend in the Z-direction, exposing the X-direction sides of the plurality of insulating layers 101 and 102 arranged in the Z-direction. This step is performed, for example, by RIE (Reactive Ion Etching).

[0113] Next, as shown in Figure 17, sacrificial layers 120B and 123B, comprising silicon oxide (SiO2) and amorphous silicon (Si) or carbon (C), and insulating layers 120O and 123O, comprising silicon oxide (SiO2), are sequentially formed inside the openings 120A and 123A. This step is performed, for example, by CVD.

[0114] Similarly to the steps shown in Figure 17, sacrificial layers 140B, 144B, 150B, 171B, 181B, and 350B are also formed inside the openings 140A, 144A, 150A, 171A, 181A, and 350A (see Figure 19). Insulating layers 140O, 144O, 150O, 171O, 181O, and 350O, such as silicon oxide (SiO2), are formed on top of these insulating layers.

[0115] Next, as shown in Figure 18, after removing the insulating layer 123O and the sacrificial layer 123B to form an opening, a portion of the insulating layer 102 is removed through the opening to form an opening 123A'. A portion of the X-direction side of the sacrificial layer 120B is exposed at the opening 123A'. This step is performed, for example, by RIE, wet etching, etc.

[0116] Next, as shown in Figures 19 and 20, for example, an insulating layer 123 is formed inside the opening 123A'. This step is performed, for example, by CVD.

[0117] Next, as shown in Figures 21 and 22, after forming an opening 120A (see Figure 6) by removing the insulating layer 120O and the sacrificial layer 120B, a portion of the insulating layer 102 is removed through the opening 120A. Furthermore, in the space formed by removing a portion of the insulating layer 102 through the opening 120A, a semiconductor layer 110, a tunnel insulating layer 131, and a charge storage layer 132 are sequentially formed. Additionally, a barrier insulating layer 133, a conductive layer 120, and an insulating layer 120O are formed in the opening 120A. This step is performed, for example, by RIE, CVD, wet etching, etc.

[0118] Next, as shown in Figures 23 and 24, after removing insulating layers 150O and 350O and sacrificial layers 150B and 350B to form openings 150A and 350A, a portion of the insulating layer 102 is removed through openings 150A and 350A. Furthermore, in the space formed by removing a portion of the insulating layer 102 through openings 150A and 350A, a semiconductor layer 110 and insulating layers 161 and 361 are sequentially formed. Also, insulating layers 163 and 363, conductive layers 150 and 350, and insulating layers 150O and 350O are formed in openings 150A and 350A. This step is performed, for example, by RIE, CVD, wet etching, etc.

[0119] Next, as shown in Figures 25 and 26, for example, the insulating layer 144O and the sacrificial layer 144B are removed to form an opening 144A, and a conductive layer 144 and an insulating layer 144O are formed in the opening 144A. This step is performed, for example, by RIE, CVD, etc.

[0120] Next, as shown in Figures 27 and 28, for example, the insulating layer 140O and the sacrificial layer 140B are removed to form an opening 140A, and a conductive layer 140 and an insulating layer 140O are formed in the opening 140A. This step is performed, for example, by RIE, CVD, etc.

[0121] Next, as shown in Figures 29 and 30, after removing portions of insulating layer 171O and sacrificial layer 171B, and insulating layer 181O and sacrificial layer 181B to form openings 171A and 181A, portions of semiconductor layer 110 and insulating layer 102 are removed through openings 171A and 181A. Furthermore, in the space formed by removing portions of insulating layer 102 through openings 171A and 181A, semiconductor layers 110, 111, and 112, and conductive layers 170 and 180 are sequentially formed. Insulating layers 171 and 171O are formed in opening 171A, and insulating layers 181 and 181O are formed in opening 181A. This step is performed, for example, by RIE, CVD, wet etching, etc.

[0122] Next, as shown in Figures 31 and 32, after forming an opening 181A by removing a portion of the remaining portion of the insulating layer 181O and the sacrificial layer 181B, a portion of the semiconductor layer 110, a portion of the insulating layer 102, and a portion of the semiconductor layer 112 are removed through the opening 181A. Furthermore, in the space formed by removing a portion of the insulating layer 102 through the opening 181A, the semiconductor layer 110, the semiconductor layer 115, and the conductive layer 180 are sequentially formed. Then, the insulating layer 181 and the insulating layer 181O are formed in the opening 181A. This step is performed, for example, by RIE, CVD, or wet etching.

[0123] [Third Implementation Form] [constitute] Figure 33 is a schematic top view showing a portion of the semiconductor memory device of the third embodiment.

[0124] Furthermore, in the following description, the same symbols are used for components that are the same as those in the first embodiment, and the explanations are omitted.

[0125] The semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of this embodiment (Fig. 33) does not have a local block select transistor SWY1 (Fig. 1) between the local block connection line LBIY and the contact electrode CC. The semiconductor memory device of this embodiment (Fig. 33) has a local block select transistor SWX1 between the plurality of memory strings MS and the contact electrode CC.

[0126] [Effect] In this embodiment, the local block selection transistor SWX1 connected to the selected memory block region RBLK is set to the ON state, and the local block selection transistor SWX1 connected to the non-selected memory block region RBLK is set to the OFF state. With this configuration, the load capacitance originating from the non-selected memory block region RBLK can be reduced, thereby improving operating speed.

[0127] [Fourth Implementation Form] [constitute] Figure 34 is a schematic top view showing a portion of the semiconductor memory device of the fourth embodiment.

[0128] Furthermore, in the following description, the same symbols are used for components that are the same as those in the first embodiment, and the explanations are omitted.

[0129] The semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of this embodiment (Fig. 34) does not have a local block select transistor SWX1 (Fig. 1) between the local block connection line LBIX and the local block connection line LBIY. The semiconductor memory device of this embodiment (Fig. 33) has a local block select transistor SWY1 between the contact electrode CC and the plurality of memory block regions RBLK.

[0130] [Effect] In this embodiment, the local block selection transistor SWY1 connected to the selected memory block region RBLK is set to the ON state, while the local block selection transistor SWY1 for all of the connected memory block regions RBLK being non-selected is set to the OFF state. With this configuration, the load capacitance of the memory block regions RBLK and local block connection lines LBIY connected to the OFF local block selection transistor SWY1 can be reduced, and the operating speed can be improved.

[0131] [Fifth Implementation Form] [constitute] Figure 35 is a schematic top view showing a portion of the semiconductor memory device according to the fifth embodiment. Figure 35 is a cross-sectional view of the portion corresponding to Figure 7, showing a cross-section of the select transistor SG.

[0132] Furthermore, in the following description, the same symbols are used for components that are the same as those in the first embodiment, and the explanations are omitted.

[0133] The semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment (Fig. 7). However, the semiconductor memory device of this embodiment (Fig. 35) has a semiconductor layer 110-5 instead of semiconductor layer 110, and a gate insulating layer 160-5 instead of gate insulating layer 160.

[0134] Semiconductor layer 110_5 is constructed in essentially the same manner as semiconductor layer 110 (Fig. 7). However, as shown in Fig. 35, for example, semiconductor layer 110_5 has a portion protruding toward the conductive layer 150 on its side facing the conductive layer 150. The side of semiconductor layer 110_5 facing the conductive layer 150, that is, the side closest to the conductive layer 150, is called surface SS1. The side of insulating layer 101 facing the conductive layer 150 is called surface SS2. Surface SS1 is positioned closer to the conductive layer 150 than surface SS2.

[0135] The gate insulating layer 160_5 is basically constructed in the same way as the gate insulating layer 160 (Fig. 7). However, the gate insulating layer 160_5 replaces the insulating layer 161 and has an insulating layer 161_5.

[0136] The insulating layer 161_5 is constructed in essentially the same manner as the insulating layer 161. However, the insulating layer 161_5 is disposed, for example, on a portion of the X-direction side of the conductive layer 150 side of the semiconductor layer 110_5 and a portion of the Z-direction side of the semiconductor layer 110_5. The insulating layer 161_5 includes a portion PT1 covering at least a portion of the X-direction side of the semiconductor layer 110_5 and a portion PT2 covering at least a portion of the Z-direction side of the semiconductor layer 110_5.

[0137] Furthermore, the semiconductor layer 110 (Figures 8 and 11) included in the local block selective transistors SWX1 and SWY1, similar to semiconductor layer 110_5, may have a portion protruding towards the conductive layers 350 and 450 on the side facing them. In this configuration, the insulating layers 361 and 461 included in the local block selective transistors SWX1 and SWY1, similar to insulating layer 161_5, may be disposed on a portion of the X-direction side of the semiconductor layer 110 on the conductive layers 350 and 450 side, and a portion of the Z-direction side of the semiconductor layer 110.

[0138] [Manufacturing Method] Figures 36-38 are schematic cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the fifth embodiment. Figures 36-38 correspond to a portion of the configuration shown in Figure 35.

[0139] The manufacturing method is basically the same as that of the first and second embodiments. However, in the manufacturing method of the fifth embodiment, instead of the steps corresponding to FIG23 and FIG24, the following steps are performed with reference to FIG36 to FIG38.

[0140] For example, in the steps shown in Figure 36, after removing the insulating layer 150O and the sacrificial layer 150B to form an opening 150A, a portion of the insulating layer 102 is removed through the opening 150A, and a semiconductor layer 110_5B is formed in the space formed by removing a portion of the insulating layer 102 through the opening 150A. The semiconductor layer 110_5B contains the same material as the semiconductor layer 110_5.

[0141] Next, for example, in the step shown in FIG37, a portion of the insulating layers 101 and 123 on the opening 150A side is removed through the opening 150A to form the opening 150A_5. A portion of the X-direction side and Z-direction side of the semiconductor layer 110_5B is exposed at the opening 150A_5. This step is performed, for example, by RIE, wet etching, etc.

[0142] Next, as shown in Figure 38, an insulating layer 161_5 is formed on a portion of the side surface of the semiconductor layer 110_5 on the side of the opening 150A_5 and on a portion of the side surface of the semiconductor layer 110_5 in the Z direction. This step is performed, for example, by thermal oxidation.

[0143] Next, an insulating layer 163 and a conductive layer 150 are sequentially formed at the opening 150A_5 to form the structure described with reference to FIG35.

[0144] [Effect] In a semiconductor memory device having layers arranged in the Z direction, each layer having a plurality of semiconductor layers and a plurality of conductive layers, when the semiconductor layers arranged in the Z direction function as channel regions of transistors, there is a situation where the threshold voltage of the transistors increases due to interference between channels in the Z direction.

[0145] In this embodiment, in the select transistor SG (FIG. 35) where the conductive layer 150 is the gate electrode, and in the local block select transistors SWX1 and SWY1 where the conductive layers 350 and 450 are the gate electrodes, a portion of the insulating layer 101 disposed between the memory layers ML is removed and moved back. With this structure, a portion of the semiconductor layer 110_5, which functions as the channel region, is covered by the conductive layers 150, 350, and 450 in the Z direction, thereby electrically shielding both sides in the Z direction.

[0146] Based on this configuration, in the selective transistor SG, local block selective transistors SWX1 and SWY1, inter-channel interference in the Z direction can be suppressed, the threshold voltage of the transistor can be prevented from rising, and the operating current can be increased.

[0147] [other] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0148] 101: Insulation layer 102: Insulation layer 110: Semiconductor layer 110_5: Semiconductor layer 110_5B: Semiconductor layer 111: Semiconductor layer 112: Semiconductor layer 112a: Semiconductor layer 113: Semiconductor layer 114: Semiconductor layer 115: Semiconductor layer 115b: Semiconductor layer 120: Conductive layer 120A: Open 120B: Sacrificial Layer 120O: Insulation layer 123: Insulation layer 123A: Opening 123A': Open 123B: Sacrificial Layer 123O: Insulation layer 130: Gate insulation layer 131: Tunnel insulation layer 132: Charge Accumulation Layer 133: Barrier Insulation Layer 140: Conductive layer 140A: Opening 140B: Sacrificial Layer 140O: Insulation layer 144: Conductive layer 144A: Opening 144B: Sacrificial Layer 144O: Insulating layer 150: Conductive layer 150A: Opening 150A_5: Opening 150B: Sacrificial Layer 150O: Insulation layer 160: Gate insulation layer 160_5: Gate insulation layer 161: Insulation layer 161_5: Insulation layer 163: Insulation layer 170: Conductive layer 171: Insulation layer 171A: Opening 171B: Sacrificial Layer 171O: Insulation layer 180: Conductive layer 181: Insulation layer 181A: Opening 181B: Sacrificial Layer 181O: Insulation layer 190: Conductive layer 191: Insulation layer 192: Part 193: Part 194: Barrier Conductive Layer 195: Conductive layer 350: Conductive layer 350A: Opening 350B: Sacrificial Layer 360: Gate insulation layer 361: Insulation layer 363: Insulation layer 450: Conductive layer 460: Gate insulation layer 461: Insulation layer 463: Insulation layer CC: Contact Electrode CSL: Source Line LBIX: Local Block Connector LBIXa: Local Block Connector LBIY: Local Block Connector MC: Memory Cell ML: Memory Layer MS: Memory String PT1: Part PT2: Partial RBLK: Memory Block Region RHU: Connecting Area RLBIY: Connector area RMC: Memory Cell Region RSG1: Select transistor region RSG2: Select Transistor Region RSWX: Region RSWX2N: Area RSWX2P: Area RSWXa: Region RSWY: Area SG: Select Transistor SS1: Face SS2: Face Sub: Semiconductor substrate SWX1: Local Block Select Transistor SWX1a: Local Block Select Transistor SWX2N: Local Block Select Transistor SWX2P: Local Block Select Transistor SWY1: Local Block Select Transistor

Claims

1. A semiconductor memory device comprising: a plurality of memory block regions arranged in a first direction; a connection region arranged in the first direction relative to the plurality of memory block regions; and a wiring region extending in the first direction and arranged with the plurality of memory block regions in a second direction intersecting the first direction; each of the plurality of memory block regions comprising: a plurality of memory strings extending in the first direction and arranged in the second direction; and a first wiring extending in the second direction and commonly connected to the plurality of memory strings; and the wiring region comprising extending in the first direction and commonly connected to a second wiring of a plurality of the first wirings corresponding to the plurality of memory block regions; the connection region comprising extending in a third direction intersecting the first and second directions and electrically connected to a contact electrode of the second wiring; A first transistor is installed in the current path between the first wiring and the second wiring.

2. The semiconductor memory device of claim 1, comprising: a plurality of memory layers arranged in the third direction as described above; and each of the plurality of memory layers comprising the plurality of memory strings, the first wiring, the second wiring, and the first transistor; and the connection region comprising a plurality of the contact electrodes corresponding to the plurality of memory layers.

3. The semiconductor memory device of claim 1, wherein a second transistor is disposed in the current path between the second wiring and the contact electrode.

4. The semiconductor memory device of claim 1, wherein a third transistor is provided in parallel with the first transistor in the current path between the first wiring and the second wiring, wherein the first transistor is an N-type transistor and the third transistor is a P-type transistor.

5. The semiconductor memory device of claim 1, wherein the gate electrode of the first transistor comprises: a plurality of first electrodes extending in the third direction; and the plurality of first electrodes are arranged in the first direction.

6. The semiconductor memory device of claim 5, wherein each of the plurality of memory strings comprises: a plurality of memory cells arranged in the first direction; and a plurality of memory gate electrodes arranged in the first direction corresponding to the plurality of memory cells arranged in the first direction; and the distance between the plurality of first electrode arrangements is equal to the distance between the plurality of memory gate electrode arrangements.

7. A semiconductor memory device comprising: a first memory layer and a second memory layer, each comprising: a plurality of memory block regions arranged in a first direction; and a wiring region extending in the first direction and arranged with the plurality of memory block regions in a second direction intersecting the first direction; wherein the first memory layer and the second memory layer are arranged in a third direction intersecting the first direction and the second direction; and an interlayer insulating layer disposed between the first memory layer and the second memory layer; wherein each of the plurality of memory block regions comprises: a plurality of semiconductor portions extending in the first direction and arranged in the second direction; and a first wiring extending in the second direction and commonly connected to the plurality of semiconductor portions; wherein the wiring region includes a second wiring extending in the first direction and commonly connected to a plurality of the first wirings corresponding to the plurality of memory block regions; and wherein: A plurality of memory gate electrodes are arranged in the first direction and extend in the third direction, facing one of the plurality of semiconductor portions, namely the first semiconductor layer and the interlayer insulating layer; and a select gate electrode is disposed between the plurality of memory gate electrodes and the first wiring, extends in the third direction, and faces the first semiconductor layer and the interlayer insulating layer; and at least a portion of the side of the first semiconductor layer facing the select gate electrode is disposed closer to the select gate electrode side than the side of the interlayer insulating layer facing the select gate electrode.

8. The semiconductor memory device of claim 7, wherein a gate insulating layer is included between the first semiconductor layer and the selected gate electrode; the gate insulating layer includes: a first portion covering at least a portion of the side surface of the first semiconductor layer in the second direction; and a second portion covering at least a portion of the side surface of the first semiconductor layer in the third direction.

9. The semiconductor memory device of claim 7, wherein the first memory layer and the second memory layer each contain a first transistor in the current path between the first wiring and the second wiring.

10. The semiconductor memory device of claim 9, wherein the first transistor system includes a second semiconductor layer and a first electrode is disposed extending in the third direction and facing the second semiconductor layer and the interlayer insulating layer, wherein the side of the second semiconductor layer facing the first electrode is disposed closer to the first electrode than the side of the interlayer insulating layer facing the first electrode.

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