Cache circuit access method and associated system on chip

Abstract

This invention discloses a cache circuit access method comprising the following steps: reading a first block of data from a system memory and writing the first block of data into a first cache circuit; reading a first piece of data from a non-shared area of ​​a second block of data from the system memory, wherein the non-shared area is a portion of the second block of data that is not present in the first block of data; reading a second piece of data from a shared area of ​​the second block of data and the first block of data from the first cache circuit; and writing the first piece of data and the second piece of data into a second cache circuit.

Claims

1. A cache circuit access method, comprising: reading a first block of data from a system memory and writing the first block of data into a first cache circuit; reading a first piece of data from a non-shared region of a second block of data from the system memory, wherein the non-shared region is a portion of the second block of data that is not present in the first block of data; reading a second piece of data from the first cache circuit from a shared region of the second block of data and the first block of data; and writing the first piece of data and the second piece of data into a second cache circuit.

2. The cache circuit access method as described in claim 1 further includes: setting a first write indicator, a second write indicator, and a read indicator; and the steps of reading the first data of the non-shared area of ​​the second block data from the system memory, reading the second data of the second block data and the shared area of ​​the first block data from the first cache circuit, and writing the first data and the second data to the second cache circuit include: using the first write indicator to write the first data read from the system memory to the second cache circuit; using the read indicator to read the second data of the second block data and the shared area of ​​the first block data from the first cache circuit; and using the second write indicator to write the second data read from the first cache circuit to the second cache circuit.

3. The cache circuit access method as described in claim 2, wherein the read index is a second read index, and the cache circuit access method further includes: setting a first read index; and using the first read index to read data from the first cache circuit for processing by a processing circuit to generate a processed first block of data, and transmitting the processed first block of data to the system memory.

4. The cache circuit access method as described in claim 1 further includes: establishing a first mapping table that records the addresses in the first cache circuit and the corresponding system memory addresses; and the step of reading the second block data and the second data of the shared area of ​​the first block data from the first cache circuit includes: reading the second block data and the second data of the shared area of ​​the first block data from the first cache circuit according to the first mapping table.

5. The cache circuit access method as described in claim 4 further includes: establishing a second mapping table that records the addresses in the second cache circuit and the corresponding addresses of the system memory.

6. A system chip comprising: a first cache circuit; a second cache circuit; and a control circuit for reading a first block of data from a system memory and writing the first block of data into the first cache circuit, reading first data from a non-shared region of a second block of data from the system memory, and reading second data from the first cache circuit from a shared region of the second block of data and the first block of data, and writing the first data and the second data into the second cache circuit, wherein the non-shared region is a portion of the second block of data that is not present in the first block of data.

7. The system chip as described in claim 6, wherein the control circuit sets a first write indicator, a second write indicator, and a read indicator; and the control circuit uses the first write indicator to write the first data read from the system memory to the second cache circuit, uses the read indicator to read the second data of the second block data and the common area of ​​the first block data from the first cache circuit, and uses the second write indicator to write the second data read from the first cache circuit to the second cache circuit.

8. The system chip as described in claim 7, wherein the read index is a second read index, the control circuit further sets a first read index, and uses the first read index to read data from the first cache circuit for processing by a processing circuit to generate a processed first block of data, and transmits the processed first block of data to the system memory.

9. The system chip as described in claim 6, wherein the control circuit establishes a first mapping table that records the addresses in the first cache circuit and the corresponding addresses of the system memory; and the control circuit reads the second block data and the second data of the shared area of ​​the first block data from the first cache circuit according to the first mapping table.

10. The system chip as described in claim 9, wherein the control circuit establishes a second mapping table that records the addresses in the second cache circuit and the corresponding addresses of the system memory.

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