Semiconductor device with vertically aligned bit line contact and channel layer

Abstract

This application discloses a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device includes a bit line structure extending along a first direction in a top view; a bit line contact point disposed on the bit line structure; a channel layer disposed on the bit line contact point and perpendicularly aligned with the bit line contact point; and a plurality of bit line structures disposed above the bit line structure, extending along a second direction perpendicular to the first direction in the top view and laterally surrounding a first sidewall of the channel layer.

Claims

1. A semiconductor element, comprising: A single-element line structure extends along a first direction from a top-view angle; A bit line contact point is set on the bit line structure; A channel layer is disposed on the bit line contact point and perpendicularly aligned with the bit line contact point; and a plurality of bit line structures are disposed above the bit line structures, extending along a second direction perpendicular to the first direction in the top view angle, and laterally surrounding the first sidewall of the channel layer, wherein the bit line structure includes: a bit line conductive layer disposed below the bit line contact point; And a bit line isolation layer, surrounding the sidewalls and lower surface of the bit line conductive layer.

2. The semiconductor device as claimed in claim 1, wherein the channel layer comprises indium gallium zinc oxide.

3. The semiconductor device as claimed in claim 2 further includes a bit line capping layer disposed between the bit line structure and the plurality of word line structures, wherein the bit line capping layer electrically isolates the bit line structure from the plurality of word line structures.

4. The semiconductor device of claim 3, wherein a ratio of the height of the bit line conductive layer to the height of the bit line isolation layer is between about 15% and about 90%.

5. The semiconductor device as claimed in claim 3 further includes a capacitor structure disposed on the channel layer.

6. The semiconductor device as claimed in claim 5, wherein the bit line contact, the channel layer, and the capacitor structure are topologically aligned.

7. The semiconductor element as claimed in claim 6, wherein the plurality of character line structures each include: An inner character line dielectric layer is disposed on the first sidewall of the channel layer; A character line conductive layer is laterally disposed on the inner character line dielectric layer and electrically isolated from the channel layer through the inner character line dielectric layer; and an outer character line dielectric layer is laterally disposed on the character line conductive layer.

8. The semiconductor device as claimed in claim 6 further includes a plurality of spacer dielectric layers laterally disposed on the second sidewall of the channel layer and disposed between the plurality of character line structures.

9. The semiconductor device as claimed in claim 8 further includes a word line capping layer covering the plurality of word line structures, the plurality of spacer dielectric layers, and the bit line capping layer.

10. The semiconductor device of claim 7, wherein the outer word line dielectric layer and the inner word line dielectric layer comprise the same material.

11. The semiconductor device as claimed in claim 7, wherein the outer word line dielectric layer and the inner word line dielectric layer comprise different materials.

12. The semiconductor element of claim 9, wherein an upper surface of the bit line contact and a lower surface of the plurality of word line structures are substantially coplanar.

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