Method for preparing semiconductor device structure with through-substrate via

Abstract

A method for manufacturing a semiconductor device structure includes: forming an opening through a semiconductor substrate, and forming a barrier layer lining the opening. The method further includes forming a conductive layer in the opening and over the barrier layer and the semiconductor substrate. The method also includes implanting a dopant into the conductive layer during its formation. Furthermore, the method includes annealing the conductive layer after implanting the dopant, and planarizing the conductive layer and the barrier layer after annealing.

Claims

1. A method for manufacturing a semiconductor device structure, comprising: An opening is formed that penetrates a semiconductor substrate; A barrier layer is formed as a liner within the opening; A conductive layer is formed in the opening and on the barrier layer and the semiconductor substrate; a dopant is implanted into the conductive layer during the formation of the conductive layer; the conductive layer is annealed after the dopant is implanted, wherein before the annealing, the conductive layer has a protrusion that overlaps with the opening, and the dopant is implanted into the protrusion of the conductive layer. And after the annealing, the conductive layer and the barrier layer are planarized.

2. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the dopant includes nitrogen (N).

3. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the dopant is implanted into the conductive layer and the barrier layer during the formation of the conductive layer.

4. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the placement is performed at an energy between about 1 keV and about 3 keV.

5. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the implantation is performed using an implantation dose between about 3 × 10⁶ atoms / cm² and about 6 × 10⁶ atoms / cm².

6. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the annealing is performed at a temperature between about 350°C and about 420°C.

7. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the conductive layer is formed by an electroplating process, and the conductive layer comprises copper (Cu).

8. A method for manufacturing a semiconductor element structure as claimed in claim 1, wherein the thickness of the conductive layer located above a top surface of the semiconductor substrate ranges from about 0.5 µm to about 2 µm.

9. A method of manufacturing a semiconductor element structure as claimed in claim 1, wherein the barrier layer extends onto the semiconductor substrate prior to the formation of the conductive layer.

10. A method of manufacturing a semiconductor element structure as claimed in claim 1, wherein the thickness of the barrier layer located above a top surface of the semiconductor substrate is in the range of about 50 nm to about 100 nm.

11. The method for manufacturing a semiconductor device structure as described in claim 1, further comprising: Before forming the barrier layer, an isolation layer is formed inside the opening and located on the semiconductor substrate.

12. A method of manufacturing a semiconductor device structure as claimed in claim 11, wherein a portion of the isolation layer located on the semiconductor substrate is removed by the planarization.

13. A method of manufacturing a semiconductor device structure as claimed in claim 11, wherein after planarization, a top surface of the conductive layer is slightly recessed, and a top surface of the barrier layer and a top surface of the isolation layer are substantially coplanar.

Images