Off-chip driver and memory chip

Abstract

An off-chip driver (OCD) includes a first driving circuit. The first driving circuit includes a first impedance circuit and a plurality of first driving units. The first impedance circuit is coupled to a signal pad. The first impedance circuit includes a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a drain terminal coupled to the signal pad, a source terminal coupled to the signal pad, and a gate terminal coupled to the drain terminal of the first MOS transistor. The second MOS transistor has a drain terminal coupled to the signal pad, a source terminal coupled to the source terminal of the first MOS transistor, and a gate terminal coupled to receive a first impedance adjustment signal. The first driving units are coupled in parallel between a first power supply voltage VDD and the source terminal of the first MOS transistor.

Claims

1. An off-chip driver (OCD) comprising: a first driving circuit comprising: a first impedance circuit coupled to a signal pad and controlled by a first impedance adjustment signal, the first impedance circuit comprising: a first metal-oxide-semiconductor (MOS) transistor having a drain terminal coupled to the signal pad, a source terminal, and a gate terminal coupled to the drain terminal of the first MOS transistor; And a second MOS transistor having a drain terminal coupled to the signal pad, a source terminal coupled to the source terminal of the first MOS transistor, and a gate terminal coupled to receive the first impedance adjustment signal; and a plurality of first driving units, coupled in parallel between a first power supply voltage and the source terminal of the first MOS transistor, wherein the plurality of first driving units are controlled by a plurality of first driving signals to drive the signal pad to a first predetermined voltage level.

2. The OCD as claimed in claim 1, wherein the equivalent resistance of the first impedance circuit is adjusted by the voltage level of the first impedance adjustment signal.

3. The OCD as claimed in claim 1, wherein the first driving circuit further includes a second driving unit, the plurality of first driving units and the second driving unit being coupled in parallel between the first power supply voltage and the first impedance circuit, the plurality of first driving units serving as a plurality of auxiliary driving units and the second driving unit serving as a main driver to drive the signal pad to the first predetermined voltage level.

4. The OCD as claimed in claim 1, wherein the first driving circuit further includes a first resistor coupled between the signal pad and the first impedance circuit.

5. The OCD as claimed in claim 1, wherein the first driving circuit further comprises: a second impedance circuit coupled to a signal pad and controlled by a second impedance adjustment signal; and a second driving unit coupled between the first power supply voltage and the second impedance circuit, the second driving unit being controlled by a second driving signal to drive the signal pad to the first predetermined voltage level.

6. The OCD as claimed in claim 5, wherein the first driving circuit further includes a second resistor coupled between the second impedance circuit and the signal pad.

7. The OCD as claimed in claim 1 further includes a second driving circuit coupled between the signal pad and the second power supply voltage, the second driving circuit comprising: a third impedance circuit coupled to the signal pad and controlled by a third impedance adjustment signal, the third impedance circuit comprising: a third MOS transistor having a drain terminal coupled to the signal pad, a source terminal, and a gate terminal coupled to the drain terminal of the first MOS transistor; And a fourth MOS transistor having a drain terminal coupled to the signal pad, a source terminal coupled to the source terminal of the first MOS transistor, and a gate terminal coupled to receive the third impedance adjustment signal; And a plurality of third driving units, coupled in parallel between the second power supply voltage and the third impedance circuit, wherein the plurality of third driving units are controlled by a plurality of third driving signals to drive the signal pads to a second predetermined voltage level.

8. The OCD as claimed in claim 7, wherein the first power supply voltage is higher than the second power supply voltage, the first predetermined voltage level is a predetermined high voltage level, the second predetermined voltage level is a predetermined low voltage level, all transistors in the first driving circuit are P-type MOS transistors, and all transistors in the second driving circuit are N-type MOS transistors.

9. The OCD as claimed in claim 7, wherein the equivalent resistance of the third impedance circuit is adjusted by the voltage level of the third impedance adjustment signal.

10. The OCD as claimed in claim 7, wherein the second driving circuit further includes a fourth driving unit, the plurality of third driving units being coupled in parallel with the fourth driving unit between the second power supply voltage and the third impedance circuit, the plurality of third driving units serving as a plurality of auxiliary driving units and the fourth driving unit serving as a master driver to drive the signal pad to the second predetermined voltage level.

11. The OCD as claimed in claim 7, wherein the second driving circuit further includes a third resistor coupled between the signal pad and the third impedance circuit.

12. The OCD as claimed in claim 7, wherein the second driving circuit further comprises: a fourth impedance circuit coupled to the signal pad and controlled by a fourth impedance adjustment signal; and a fourth driving unit coupled between the second power supply voltage and the fourth impedance circuit, the fourth driving unit being controlled by a fourth driving signal to drive the signal pad to the second predetermined voltage level.

13. The OCD as claimed in claim 12, wherein the second driving circuit further includes a fourth resistor coupled between the fourth impedance circuit and the signal pad.

14. A memory chip, comprising: an off-chip driver (OCD), comprising: a first driving circuit, comprising: a first impedance circuit coupled to a signal pad and controlled by a first impedance adjustment signal, the first impedance circuit comprising: a first metal-oxide-semiconductor (MOS) transistor having a drain terminal coupled to the signal pad, a source terminal, and a gate terminal coupled to the drain terminal of the first MOS transistor; And a second MOS transistor having a drain terminal coupled to the signal pad, a source terminal coupled to the source terminal of the first MOS transistor, and a gate terminal coupled to receive the first impedance adjustment signal; And a plurality of first driving units, coupled in parallel between a first power supply voltage and the source terminal of the first MOS transistor, wherein the plurality of first driving units are controlled by a plurality of first driving signals to drive the signal pad to a first predetermined voltage level.

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