Base memory unit, semiconductor device, and method for fabricating the same

Abstract

This disclosure provides a basic memory cell, a semiconductor device, and a method for fabricating the same. The basic memory cell is configured as an oxide semiconductor random access memory and includes: a substrate including an array region and a peripheral region adjacent to the array region; a first bit line located on the array region; a first word line located on the first bit line; a channel structure located on the first bit line and passing through the first word line; a first dielectric layer located on the first bit line and a second dielectric layer located on the first word line; a trench capacitor located on the channel structure; a first substrate via located in the array region and below the first bit line; and a first cell via located in the peripheral region and passing through the basic memory cell.

Claims

1. A basic memory unit, comprising: A substrate includes an array region and a peripheral region, wherein the peripheral region is adjacent to the array region; A first bit line, located on the array region and extending along a first direction; a first word line, located on the first bit line and extending along a second direction, wherein the second direction is perpendicular to the first direction; a channel structure, located on the first bit line and passing through the first word line, wherein the channel structure is separated from the first word line by a gate dielectric layer; a first dielectric layer on the first bit line and a second dielectric layer on the first word line, wherein the second dielectric layer includes a first air gap structure; a trench capacitor, located on the channel structure; a first substrate via, located in the array region and below the first bit line; and a first cell via, located in the peripheral region and passing through the basic memory cell, wherein the basic memory cell is configured as an oxide semiconductor random access memory.

2. The basic memory cell as described in claim 1 further includes a first landing pad located between the channel structure and the first bit line.

3. The basic memory cell as described in claim 2, wherein the first landing pad is in contact with the first element line through a titanium nitride layer.

4. The basic memory cell as described in claim 2 further includes an indium tin oxide layer located between the channel structure and the first landing pad.

5. The basic memory cell as described in claim 1 further includes a second landing pad located between the trench capacitor and the channel structure.

6. The basic memory unit as described in claim 1, further comprising: A first conductive layer is located between the substrate and the first element line; And a first contact, located on and electrically connected to the first conductive layer, wherein the first contact is spaced apart from the channel structure.

7. The basic memory cell as described in claim 6, wherein the first contact is a single-crystal structure.

8. The basic memory cell as described in claim 6 further includes a second contact disposed between the first word line and the first conductive layer, wherein the second contact is spaced apart from the channel structure.

9. The basic memory cell as claimed in claim 1 further includes a polysilicon layer on the trench capacitor, opposite to the channel structure, wherein the polysilicon layer has a first sidewall.

10. The basic memory cell as described in claim 9, wherein the first sidewall is non-planar.

11. The basic memory cell as claimed in claim 9 further includes a second conductive layer on the polysilicon layer, wherein the second conductive layer has a second sidewall, and wherein the first sidewall is recessed from the second sidewall of the second conductive layer.

12. The basic memory cell as claimed in claim 1, wherein the first air gap structure of the second dielectric layer includes an air gap closed by a liner.

13. The basic memory cell as described in claim 12, wherein the fabrication technique of the first air gap structure includes a heat treatment process.

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