Semiconductor structure and method of forming the same

Abstract

This disclosure provides a method comprising forming bitline structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; forming trenches between the bitline structures in the first direction; forming a conductive layer in the trenches; forming an isolation structure extending in the second direction through the conductive layer and the top of the bitline structures; removing the top of the conductive layer to form a contact, wherein the boundary of the contact is defined by the bitline structures and the isolation structure; removing corners of the contact to form a recess, wherein the corners are adjacent to the bitline structures and the isolation structure; and forming a spacer in the recess, wherein the top surface of the spacer is flush with the top surface of the contact.

Claims

1. A method for forming a semiconductor structure, comprising: A plurality of bitline structures are formed, extending along a first direction and separated from each other along a second direction, the first direction being perpendicular to the second direction; a first trench is formed between adjacent bitline structures along the first direction; a first conductive layer is formed in the first trench; a plurality of isolation structures are formed, passing through the first conductive layer and a top of the bitline structures along the second direction; a top of the first conductive layer is removed to form a contact, wherein a boundary of the contact is defined by adjacent bitline structures and adjacent isolation structures; a plurality of corners of the contact are removed to form a plurality of recesses, wherein the corners are adjacent to the bitline structures and isolation structures; and a plurality of first spacers are formed in the recesses, wherein a top surface of the first spacers is flush with a top surface of the contact.

2. The method as described in claim 1, wherein forming the first conductive layer in the first trench comprises: A conductive material is deposited to fill the first trench; And remove one top of the conductive material.

3. The method as described in claim 1, wherein forming the isolation structures through the top of the first conductive layer and the bit line structures comprises: A plurality of second trenches are formed, passing through the top of the first conductive layer and the bit line structures along the second direction; A conformal liner is formed in the second trench; and a nitride layer is formed on the liner.

4. The method as described in claim 1, wherein removing the corners of the contact to form the recesses comprises: Remove one of the first opposite corner portions of the contact; And remove a second opposite corner of the contact, wherein the first opposite corner is different from the second opposite corner.

5. The method as described in claim 4, wherein removing the first opposite corner of the contact comprises: A first photoresist layer is formed on the semiconductor structure; the first photoresist layer is patterned to form a first photoresist feature, wherein the first photoresist feature has a plurality of first slits to expose the first opposite corner of the contact; the first opposite corner of the contact is etched; and the first photoresist feature is removed.

6. The method as described in claim 5, wherein removing the second opposite corner of the contact comprises: A second photoresist layer is formed on the semiconductor structure; the second photoresist layer is patterned to form a second photoresist feature, wherein the second photoresist feature has a plurality of second slits to expose the second opposite corner of the contact, the first opposite corner of the contact being different from the second opposite corner of the contact; the second opposite corner of the contact is etched; and the second photoresist feature is removed.

7. The method as described in claim 6, wherein the first slits extend along a third direction, which is different from the first direction and the second direction, and the third direction is inclined to the first direction, and the second slits extend along a fourth direction, which is different from the first direction, the second direction and the third direction.

8. The method as described in claim 7, wherein the third direction is orthogonal to the fourth direction.

9. The method as described in claim 1, wherein after removing the corners of the contact, the width of the contact adjacent to the bit line structures is smaller than the width of the contact between the adjacent isolation structures.

10. The method as described in claim 9, wherein the width of the contact adjacent to the bit line structures has a ratio greater than 80% to the width of the contact between the adjacent isolation structures.

11. The method as described in claim 1, wherein each bitline structure comprises: A second conductive layer; A capping layer is placed on the second conductive layer; And a plurality of second spacers on a plurality of sidewalls of the second conductive layer and the capping layer, wherein, after the isolation structures are formed, in a cross section parallel to the first direction, the isolation structures extend through a top of the capping layer of the bit line structures.

12. A semiconductor structure, comprising: A plurality of bitline structures are arranged along a first direction and separated from each other along a second direction, the first direction being perpendicular to the second direction; a plurality of isolation structures are arranged along the second direction and extend through a top of the bitline structures; a contact member is disposed between adjacent bitline structures and adjacent isolation structures; and a plurality of first spacers are adjacent to the bitline structures, the isolation structures and the contact member, wherein a top surface of the contact member is flush with a top surface of the first spacers, and the width of the contact member adjacent to the bitline structures and the width of the contact member between the adjacent isolation structures have a ratio greater than 80%.

13. The semiconductor structure as claimed in claim 12, wherein the top surface of the contact is lower than a top surface of the bit line structure.

14. The semiconductor structure as claimed in claim 12, wherein the contact directly contacts the bit line structures, the isolation structures, and the first spacers.

15. The semiconductor structure as described in claim 12, wherein each bit line structure comprises: A conductive layer; A capping layer is placed on the conductive layer; And a plurality of second spacers on a plurality of sidewalls of the conductive layer and the capping layer, wherein, in a cross section parallel to the first direction, the spacers extend through a top of the capping layer of the bit line structures.

16. The semiconductor structure as claimed in claim 12, wherein in a cross section parallel to the second direction and extending through the first spacers, a cross section of the contact has a downwardly pointed shape.

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