Semiconductor structure and manufacturing method thereof

Abstract

A method for manufacturing a semiconductor structure is provided. The method includes the following steps: A substrate is provided. An oxide layer is formed on the silicon surface of the substrate in an active region at a first temperature through a first gas precursor, wherein the first gas precursor includes oxygen, and silicon dangling bonds are present at the interface between the substrate and the oxide layer. The interface between the substrate and the oxide layer is passivated at a second temperature through a second gas precursor to remove the silicon dangling bonds, wherein the second gas precursor includes hydrogen and nitrogen, and the second temperature is lower than the first temperature. A passivation interface is formed at the interface between the substrate and the oxide layer, the passivation interface including silicon-hydrogen bonds, wherein the interface defect density (Dit) of the passivation interface is 1.2E+10 q / cm²-eV at 2.5 eV.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, wherein the substrate has an active region and a peripheral region surrounding the active region, and the substrate has a silicon crystal surface in the active region; an oxide layer is formed on the silicon crystal surface of the substrate in the active region by passing through a first gas precursor at a first temperature, wherein the first gas precursor includes oxygen, and a silicon dangling bond is formed at an interface between the substrate and the oxide layer; a passivation treatment is performed on the interface between the substrate and the oxide layer at a second temperature by passing through a second gas precursor to remove the silicon dangling bond, wherein the second gas precursor includes hydrogen and nitrogen, the concentration of hydrogen is between 11 vol% and 15 vol%, and the concentration of nitrogen is between 85 vol% and 89 vol%, the second temperature being lower than the first temperature; and a passivation interface is formed at the interface between the substrate and the oxide layer, the passivation interface including a silicon hydrogen bond, wherein at 2.5 The interface defect density (Dit) of this passivated interface at eV is 1.2E+10 q / cm2-eV.

2. The method as described in claim 1, wherein the thickness of the oxide layer is 115 angstroms before the passivation treatment and the thickness of the oxide layer remains unchanged after the passivation treatment.

3. The method as described in claim 1, wherein the concentration of hydrogen is 12% by volume and the concentration of nitrogen is 88% by volume.

4. The method as described in claim 1, wherein the flow rate of hydrogen is between 1800 standard cubic centimeters per minute (sccm) and 2700 sccm.

5. The method as described in claim 1, wherein the flow rate of nitrogen is between 10,000 sccm and 20,000 sccm.

6. The method as described in claim 1, wherein the passivation treatment is performed at 1 standard atmosphere (atm).

7. The method as described in claim 1, wherein the passivation process takes between 20 and 25 minutes.

8. The method as described in claim 1, wherein the first temperature is in the range of 700°C to 800°C.

9. The method as described in claim 1, wherein the second temperature is in the range of 400°C to 450°C.

10. A semiconductor structure, comprising: A substrate has an active region and a peripheral region, the peripheral region surrounding the active region, and the substrate has a silicon crystal surface in the active region; A gate structure is located on the substrate, the gate structure including: an oxide layer located on the substrate; A passivation interface is located on the silicon surface of the substrate, between the substrate and the oxide layer, and the passivation interface has a silicon-hydrogen bond, wherein the interface defect density (Dit) of the passivation interface is 1.2E+10 q / cm2-eV at 2.5 eV; a conductive layer is located on the oxide layer; a hard masking layer is located on the conductive layer; and a spacer is located on a common sidewall of the oxide layer, the conductive layer and the hard masking layer.

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